summaryrefslogtreecommitdiffstats
path: root/drivers/fpga/dfl-fme-pr.c
blob: 0b840531ef33a2e1f387d15f550fb808df5ae8bf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for FPGA Management Engine (FME) Partial Reconfiguration
 *
 * Copyright (C) 2017-2018 Intel Corporation, Inc.
 *
 * Authors:
 *   Kang Luwei <luwei.kang@intel.com>
 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
 *   Wu Hao <hao.wu@intel.com>
 *   Joseph Grecco <joe.grecco@intel.com>
 *   Enno Luebbers <enno.luebbers@intel.com>
 *   Tim Whisonant <tim.whisonant@intel.com>
 *   Ananda Ravuri <ananda.ravuri@intel.com>
 *   Christopher Rauer <christopher.rauer@intel.com>
 *   Henry Mitchel <henry.mitchel@intel.com>
 */

#include <linux/types.h>
#include <linux/device.h>
#include <linux/vmalloc.h>
#include <linux/uaccess.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/fpga/fpga-bridge.h>
#include <linux/fpga/fpga-region.h>
#include <linux/fpga-dfl.h>

#include "dfl.h"
#include "dfl-fme.h"
#include "dfl-fme-pr.h"

static struct dfl_fme_region *
dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
{
	struct dfl_fme_region *fme_region;

	list_for_each_entry(fme_region, &fme->region_list, node)
		if (fme_region->port_id == port_id)
			return fme_region;

	return NULL;
}

static int dfl_fme_region_match(struct device *dev, const void *data)
{
	return dev->parent == data;
}

static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
{
	struct dfl_fme_region *fme_region;
	struct fpga_region *region;

	fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
	if (!fme_region)
		return NULL;

	region = fpga_region_class_find(NULL, &fme_region->region->dev,
					dfl_fme_region_match);
	if (!region)
		return NULL;

	return region;
}

static int fme_pr(struct platform_device *pdev, unsigned long arg)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
	void __user *argp = (void __user *)arg;
	struct dfl_fpga_fme_port_pr port_pr;
	struct fpga_image_info *info;
	struct fpga_region *region;
	void __iomem *fme_hdr;
	struct dfl_fme *fme;
	unsigned long minsz;
	void *buf = NULL;
	int ret = 0;
	u64 v;

	minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);

	if (copy_from_user(&port_pr, argp, minsz))
		return -EFAULT;

	if (port_pr.argsz < minsz || port_pr.flags)
		return -EINVAL;

	if (!IS_ALIGNED(port_pr.buffer_size, 4))
		return -EINVAL;

	/* get fme header region */
	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
					       FME_FEATURE_ID_HEADER);

	/* check port id */
	v = readq(fme_hdr + FME_HDR_CAP);
	if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
		dev_dbg(&pdev->dev, "port number more than maximum\n");
		return -EINVAL;
	}

	if (!access_ok(VERIFY_READ,
		       (void __user *)(unsigned long)port_pr.buffer_address,
		       port_pr.buffer_size))
		return -EFAULT;

	buf = vmalloc(port_pr.buffer_size);
	if (!buf)
		return -ENOMEM;

	if (copy_from_user(buf,
			   (void __user *)(unsigned long)port_pr.buffer_address,
			   port_pr.buffer_size)) {
		ret = -EFAULT;
		goto free_exit;
	}

	/* prepare fpga_image_info for PR */
	info = fpga_image_info_alloc(&pdev->dev);
	if (!info) {
		ret = -ENOMEM;
		goto free_exit;
	}

	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;

	mutex_lock(&pdata->lock);
	fme = dfl_fpga_pdata_get_private(pdata);
	/* fme device has been unregistered. */
	if (!fme) {
		ret = -EINVAL;
		goto unlock_exit;
	}

	region = dfl_fme_region_find(fme, port_pr.port_id);
	if (!region) {
		ret = -EINVAL;
		goto unlock_exit;
	}

	fpga_image_info_free(region->info);

	info->buf = buf;
	info->count = port_pr.buffer_size;
	info->region_id = port_pr.port_id;
	region->info = info;

	ret = fpga_region_program_fpga(region);

	/*
	 * it allows userspace to reset the PR region's logic by disabling and
	 * reenabling the bridge to clear things out between accleration runs.
	 * so no need to hold the bridges after partial reconfiguration.
	 */
	if (region->get_bridges)
		fpga_bridges_put(&region->bridge_list);

	put_device(&region->dev);
unlock_exit:
	mutex_unlock(&pdata->lock);
free_exit:
	vfree(buf);
	if (copy_to_user((void __user *)arg, &port_pr, minsz))
		return -EFAULT;

	return ret;
}

/**
 * dfl_fme_create_mgr - create fpga mgr platform device as child device
 *
 * @pdata: fme platform_device's pdata
 *
 * Return: mgr platform device if successful, and error code otherwise.
 */
static struct platform_device *
dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
		   struct dfl_feature *feature)
{
	struct platform_device *mgr, *fme = pdata->dev;
	struct dfl_fme_mgr_pdata mgr_pdata;
	int ret = -ENOMEM;

	if (!feature->ioaddr)
		return ERR_PTR(-ENODEV);

	mgr_pdata.ioaddr = feature->ioaddr;

	/*
	 * Each FME has only one fpga-mgr, so allocate platform device using
	 * the same FME platform device id.
	 */
	mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
	if (!mgr)
		return ERR_PTR(ret);

	mgr->dev.parent = &fme->dev;

	ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
	if (ret)
		goto create_mgr_err;

	ret = platform_device_add(mgr);
	if (ret)
		goto create_mgr_err;

	return mgr;

create_mgr_err:
	platform_device_put(mgr);
	return ERR_PTR(ret);
}

/**
 * dfl_fme_destroy_mgr - destroy fpga mgr platform device
 * @pdata: fme platform device's pdata
 */
static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
{
	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);

	platform_device_unregister(priv->mgr);
}

/**
 * dfl_fme_create_bridge - create fme fpga bridge platform device as child
 *
 * @pdata: fme platform device's pdata
 * @port_id: port id for the bridge to be created.
 *
 * Return: bridge platform device if successful, and error code otherwise.
 */
static struct dfl_fme_bridge *
dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
{
	struct device *dev = &pdata->dev->dev;
	struct dfl_fme_br_pdata br_pdata;
	struct dfl_fme_bridge *fme_br;
	int ret = -ENOMEM;

	fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
	if (!fme_br)
		return ERR_PTR(ret);

	br_pdata.cdev = pdata->dfl_cdev;
	br_pdata.port_id = port_id;

	fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
					   PLATFORM_DEVID_AUTO);
	if (!fme_br->br)
		return ERR_PTR(ret);

	fme_br->br->dev.parent = dev;

	ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
	if (ret)
		goto create_br_err;

	ret = platform_device_add(fme_br->br);
	if (ret)
		goto create_br_err;

	return fme_br;

create_br_err:
	platform_device_put(fme_br->br);
	return ERR_PTR(ret);
}

/**
 * dfl_fme_destroy_bridge - destroy fpga bridge platform device
 * @fme_br: fme bridge to destroy
 */
static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
{
	platform_device_unregister(fme_br->br);
}

/**
 * dfl_fme_destroy_bridge - destroy all fpga bridge platform device
 * @pdata: fme platform device's pdata
 */
static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
{
	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
	struct dfl_fme_bridge *fbridge, *tmp;

	list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
		list_del(&fbridge->node);
		dfl_fme_destroy_bridge(fbridge);
	}
}

/**
 * dfl_fme_create_region - create fpga region platform device as child
 *
 * @pdata: fme platform device's pdata
 * @mgr: mgr platform device needed for region
 * @br: br platform device needed for region
 * @port_id: port id
 *
 * Return: fme region if successful, and error code otherwise.
 */
static struct dfl_fme_region *
dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
		      struct platform_device *mgr,
		      struct platform_device *br, int port_id)
{
	struct dfl_fme_region_pdata region_pdata;
	struct device *dev = &pdata->dev->dev;
	struct dfl_fme_region *fme_region;
	int ret = -ENOMEM;

	fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
	if (!fme_region)
		return ERR_PTR(ret);

	region_pdata.mgr = mgr;
	region_pdata.br = br;

	/*
	 * Each FPGA device may have more than one port, so allocate platform
	 * device using the same port platform device id.
	 */
	fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
	if (!fme_region->region)
		return ERR_PTR(ret);

	fme_region->region->dev.parent = dev;

	ret = platform_device_add_data(fme_region->region, &region_pdata,
				       sizeof(region_pdata));
	if (ret)
		goto create_region_err;

	ret = platform_device_add(fme_region->region);
	if (ret)
		goto create_region_err;

	fme_region->port_id = port_id;

	return fme_region;

create_region_err:
	platform_device_put(fme_region->region);
	return ERR_PTR(ret);
}

/**
 * dfl_fme_destroy_region - destroy fme region
 * @fme_region: fme region to destroy
 */
static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
{
	platform_device_unregister(fme_region->region);
}

/**
 * dfl_fme_destroy_regions - destroy all fme regions
 * @pdata: fme platform device's pdata
 */
static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
{
	struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
	struct dfl_fme_region *fme_region, *tmp;

	list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
		list_del(&fme_region->node);
		dfl_fme_destroy_region(fme_region);
	}
}

static int pr_mgmt_init(struct platform_device *pdev,
			struct dfl_feature *feature)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct dfl_fme_region *fme_region;
	struct dfl_fme_bridge *fme_br;
	struct platform_device *mgr;
	struct dfl_fme *priv;
	void __iomem *fme_hdr;
	int ret = -ENODEV, i = 0;
	u64 fme_cap, port_offset;

	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
					       FME_FEATURE_ID_HEADER);

	mutex_lock(&pdata->lock);
	priv = dfl_fpga_pdata_get_private(pdata);

	/* Initialize the region and bridge sub device list */
	INIT_LIST_HEAD(&priv->region_list);
	INIT_LIST_HEAD(&priv->bridge_list);

	/* Create fpga mgr platform device */
	mgr = dfl_fme_create_mgr(pdata, feature);
	if (IS_ERR(mgr)) {
		dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
		goto unlock;
	}

	priv->mgr = mgr;

	/* Read capability register to check number of regions and bridges */
	fme_cap = readq(fme_hdr + FME_HDR_CAP);
	for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
		port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
		if (!(port_offset & FME_PORT_OFST_IMP))
			continue;

		/* Create bridge for each port */
		fme_br = dfl_fme_create_bridge(pdata, i);
		if (IS_ERR(fme_br)) {
			ret = PTR_ERR(fme_br);
			goto destroy_region;
		}

		list_add(&fme_br->node, &priv->bridge_list);

		/* Create region for each port */
		fme_region = dfl_fme_create_region(pdata, mgr,
						   fme_br->br, i);
		if (IS_ERR(fme_region)) {
			ret = PTR_ERR(fme_region);
			goto destroy_region;
		}

		list_add(&fme_region->node, &priv->region_list);
	}
	mutex_unlock(&pdata->lock);

	return 0;

destroy_region:
	dfl_fme_destroy_regions(pdata);
	dfl_fme_destroy_bridges(pdata);
	dfl_fme_destroy_mgr(pdata);
unlock:
	mutex_unlock(&pdata->lock);
	return ret;
}

static void pr_mgmt_uinit(struct platform_device *pdev,
			  struct dfl_feature *feature)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct dfl_fme *priv;

	mutex_lock(&pdata->lock);
	priv = dfl_fpga_pdata_get_private(pdata);

	dfl_fme_destroy_regions(pdata);
	dfl_fme_destroy_bridges(pdata);
	dfl_fme_destroy_mgr(pdata);
	mutex_unlock(&pdata->lock);
}

static long fme_pr_ioctl(struct platform_device *pdev,
			 struct dfl_feature *feature,
			 unsigned int cmd, unsigned long arg)
{
	long ret;

	switch (cmd) {
	case DFL_FPGA_FME_PORT_PR:
		ret = fme_pr(pdev, arg);
		break;
	default:
		ret = -ENODEV;
	}

	return ret;
}

const struct dfl_feature_ops pr_mgmt_ops = {
	.init = pr_mgmt_init,
	.uinit = pr_mgmt_uinit,
	.ioctl = fme_pr_ioctl,
};