summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/adreno/a6xx.xml.h
blob: 920c5e6b8e9673af6e1d293a54db646c383e6ee9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
7010
7011
7012
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123
7124
7125
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140
7141
7142
7143
7144
7145
7146
7147
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282
7283
7284
7285
7286
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
#ifndef A6XX_XML
#define A6XX_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git

The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)

Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


enum a6xx_tile_mode {
	TILE6_LINEAR = 0,
	TILE6_2 = 2,
	TILE6_3 = 3,
};

enum a6xx_format {
	FMT6_A8_UNORM = 2,
	FMT6_8_UNORM = 3,
	FMT6_8_SNORM = 4,
	FMT6_8_UINT = 5,
	FMT6_8_SINT = 6,
	FMT6_4_4_4_4_UNORM = 8,
	FMT6_5_5_5_1_UNORM = 10,
	FMT6_1_5_5_5_UNORM = 12,
	FMT6_5_6_5_UNORM = 14,
	FMT6_8_8_UNORM = 15,
	FMT6_8_8_SNORM = 16,
	FMT6_8_8_UINT = 17,
	FMT6_8_8_SINT = 18,
	FMT6_L8_A8_UNORM = 19,
	FMT6_16_UNORM = 21,
	FMT6_16_SNORM = 22,
	FMT6_16_FLOAT = 23,
	FMT6_16_UINT = 24,
	FMT6_16_SINT = 25,
	FMT6_8_8_8_UNORM = 33,
	FMT6_8_8_8_SNORM = 34,
	FMT6_8_8_8_UINT = 35,
	FMT6_8_8_8_SINT = 36,
	FMT6_8_8_8_8_UNORM = 48,
	FMT6_8_8_8_X8_UNORM = 49,
	FMT6_8_8_8_8_SNORM = 50,
	FMT6_8_8_8_8_UINT = 51,
	FMT6_8_8_8_8_SINT = 52,
	FMT6_9_9_9_E5_FLOAT = 53,
	FMT6_10_10_10_2_UNORM = 54,
	FMT6_10_10_10_2_UNORM_DEST = 55,
	FMT6_10_10_10_2_SNORM = 57,
	FMT6_10_10_10_2_UINT = 58,
	FMT6_10_10_10_2_SINT = 59,
	FMT6_11_11_10_FLOAT = 66,
	FMT6_16_16_UNORM = 67,
	FMT6_16_16_SNORM = 68,
	FMT6_16_16_FLOAT = 69,
	FMT6_16_16_UINT = 70,
	FMT6_16_16_SINT = 71,
	FMT6_32_UNORM = 72,
	FMT6_32_SNORM = 73,
	FMT6_32_FLOAT = 74,
	FMT6_32_UINT = 75,
	FMT6_32_SINT = 76,
	FMT6_32_FIXED = 77,
	FMT6_16_16_16_UNORM = 88,
	FMT6_16_16_16_SNORM = 89,
	FMT6_16_16_16_FLOAT = 90,
	FMT6_16_16_16_UINT = 91,
	FMT6_16_16_16_SINT = 92,
	FMT6_16_16_16_16_UNORM = 96,
	FMT6_16_16_16_16_SNORM = 97,
	FMT6_16_16_16_16_FLOAT = 98,
	FMT6_16_16_16_16_UINT = 99,
	FMT6_16_16_16_16_SINT = 100,
	FMT6_32_32_UNORM = 101,
	FMT6_32_32_SNORM = 102,
	FMT6_32_32_FLOAT = 103,
	FMT6_32_32_UINT = 104,
	FMT6_32_32_SINT = 105,
	FMT6_32_32_FIXED = 106,
	FMT6_32_32_32_UNORM = 112,
	FMT6_32_32_32_SNORM = 113,
	FMT6_32_32_32_UINT = 114,
	FMT6_32_32_32_SINT = 115,
	FMT6_32_32_32_FLOAT = 116,
	FMT6_32_32_32_FIXED = 117,
	FMT6_32_32_32_32_UNORM = 128,
	FMT6_32_32_32_32_SNORM = 129,
	FMT6_32_32_32_32_FLOAT = 130,
	FMT6_32_32_32_32_UINT = 131,
	FMT6_32_32_32_32_SINT = 132,
	FMT6_32_32_32_32_FIXED = 133,
	FMT6_G8R8B8R8_422_UNORM = 140,
	FMT6_R8G8R8B8_422_UNORM = 141,
	FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
	FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
	FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
	FMT6_8_PLANE_UNORM = 148,
	FMT6_Z24_UNORM_S8_UINT = 160,
	FMT6_ETC2_RG11_UNORM = 171,
	FMT6_ETC2_RG11_SNORM = 172,
	FMT6_ETC2_R11_UNORM = 173,
	FMT6_ETC2_R11_SNORM = 174,
	FMT6_ETC1 = 175,
	FMT6_ETC2_RGB8 = 176,
	FMT6_ETC2_RGBA8 = 177,
	FMT6_ETC2_RGB8A1 = 178,
	FMT6_DXT1 = 179,
	FMT6_DXT3 = 180,
	FMT6_DXT5 = 181,
	FMT6_RGTC1_UNORM = 183,
	FMT6_RGTC1_SNORM = 184,
	FMT6_RGTC2_UNORM = 187,
	FMT6_RGTC2_SNORM = 188,
	FMT6_BPTC_UFLOAT = 190,
	FMT6_BPTC_FLOAT = 191,
	FMT6_BPTC = 192,
	FMT6_ASTC_4x4 = 193,
	FMT6_ASTC_5x4 = 194,
	FMT6_ASTC_5x5 = 195,
	FMT6_ASTC_6x5 = 196,
	FMT6_ASTC_6x6 = 197,
	FMT6_ASTC_8x5 = 198,
	FMT6_ASTC_8x6 = 199,
	FMT6_ASTC_8x8 = 200,
	FMT6_ASTC_10x5 = 201,
	FMT6_ASTC_10x6 = 202,
	FMT6_ASTC_10x8 = 203,
	FMT6_ASTC_10x10 = 204,
	FMT6_ASTC_12x10 = 205,
	FMT6_ASTC_12x12 = 206,
	FMT6_S8Z24_UINT = 234,
	FMT6_NONE = 255,
};

enum a6xx_polygon_mode {
	POLYMODE6_POINTS = 1,
	POLYMODE6_LINES = 2,
	POLYMODE6_TRIANGLES = 3,
};

enum a6xx_depth_format {
	DEPTH6_NONE = 0,
	DEPTH6_16 = 1,
	DEPTH6_24_8 = 2,
	DEPTH6_32 = 4,
};

enum a6xx_shader_id {
	A6XX_TP0_TMO_DATA = 9,
	A6XX_TP0_SMO_DATA = 10,
	A6XX_TP0_MIPMAP_BASE_DATA = 11,
	A6XX_TP1_TMO_DATA = 25,
	A6XX_TP1_SMO_DATA = 26,
	A6XX_TP1_MIPMAP_BASE_DATA = 27,
	A6XX_SP_INST_DATA = 41,
	A6XX_SP_LB_0_DATA = 42,
	A6XX_SP_LB_1_DATA = 43,
	A6XX_SP_LB_2_DATA = 44,
	A6XX_SP_LB_3_DATA = 45,
	A6XX_SP_LB_4_DATA = 46,
	A6XX_SP_LB_5_DATA = 47,
	A6XX_SP_CB_BINDLESS_DATA = 48,
	A6XX_SP_CB_LEGACY_DATA = 49,
	A6XX_SP_UAV_DATA = 50,
	A6XX_SP_INST_TAG = 51,
	A6XX_SP_CB_BINDLESS_TAG = 52,
	A6XX_SP_TMO_UMO_TAG = 53,
	A6XX_SP_SMO_TAG = 54,
	A6XX_SP_STATE_DATA = 55,
	A6XX_HLSQ_CHUNK_CVS_RAM = 73,
	A6XX_HLSQ_CHUNK_CPS_RAM = 74,
	A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
	A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
	A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
	A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
	A6XX_HLSQ_CVS_MISC_RAM = 80,
	A6XX_HLSQ_CPS_MISC_RAM = 81,
	A6XX_HLSQ_INST_RAM = 82,
	A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
	A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
	A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
	A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
	A6XX_HLSQ_INST_RAM_TAG = 87,
	A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
	A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
	A6XX_HLSQ_PWR_REST_RAM = 90,
	A6XX_HLSQ_PWR_REST_TAG = 91,
	A6XX_HLSQ_DATAPATH_META = 96,
	A6XX_HLSQ_FRONTEND_META = 97,
	A6XX_HLSQ_INDIRECT_META = 98,
	A6XX_HLSQ_BACKEND_META = 99,
};

enum a6xx_debugbus_id {
	A6XX_DBGBUS_CP = 1,
	A6XX_DBGBUS_RBBM = 2,
	A6XX_DBGBUS_VBIF = 3,
	A6XX_DBGBUS_HLSQ = 4,
	A6XX_DBGBUS_UCHE = 5,
	A6XX_DBGBUS_DPM = 6,
	A6XX_DBGBUS_TESS = 7,
	A6XX_DBGBUS_PC = 8,
	A6XX_DBGBUS_VFDP = 9,
	A6XX_DBGBUS_VPC = 10,
	A6XX_DBGBUS_TSE = 11,
	A6XX_DBGBUS_RAS = 12,
	A6XX_DBGBUS_VSC = 13,
	A6XX_DBGBUS_COM = 14,
	A6XX_DBGBUS_LRZ = 16,
	A6XX_DBGBUS_A2D = 17,
	A6XX_DBGBUS_CCUFCHE = 18,
	A6XX_DBGBUS_GMU_CX = 19,
	A6XX_DBGBUS_RBP = 20,
	A6XX_DBGBUS_DCS = 21,
	A6XX_DBGBUS_DBGC = 22,
	A6XX_DBGBUS_CX = 23,
	A6XX_DBGBUS_GMU_GX = 24,
	A6XX_DBGBUS_TPFCHE = 25,
	A6XX_DBGBUS_GBIF_GX = 26,
	A6XX_DBGBUS_GPC = 29,
	A6XX_DBGBUS_LARC = 30,
	A6XX_DBGBUS_HLSQ_SPTP = 31,
	A6XX_DBGBUS_RB_0 = 32,
	A6XX_DBGBUS_RB_1 = 33,
	A6XX_DBGBUS_UCHE_WRAPPER = 36,
	A6XX_DBGBUS_CCU_0 = 40,
	A6XX_DBGBUS_CCU_1 = 41,
	A6XX_DBGBUS_VFD_0 = 56,
	A6XX_DBGBUS_VFD_1 = 57,
	A6XX_DBGBUS_VFD_2 = 58,
	A6XX_DBGBUS_VFD_3 = 59,
	A6XX_DBGBUS_SP_0 = 64,
	A6XX_DBGBUS_SP_1 = 65,
	A6XX_DBGBUS_TPL1_0 = 72,
	A6XX_DBGBUS_TPL1_1 = 73,
	A6XX_DBGBUS_TPL1_2 = 74,
	A6XX_DBGBUS_TPL1_3 = 75,
};

enum a6xx_cp_perfcounter_select {
	PERF_CP_ALWAYS_COUNT = 0,
	PERF_CP_BUSY_GFX_CORE_IDLE = 1,
	PERF_CP_BUSY_CYCLES = 2,
	PERF_CP_NUM_PREEMPTIONS = 3,
	PERF_CP_PREEMPTION_REACTION_DELAY = 4,
	PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
	PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
	PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
	PERF_CP_PREDICATED_DRAWS_KILLED = 8,
	PERF_CP_MODE_SWITCH = 9,
	PERF_CP_ZPASS_DONE = 10,
	PERF_CP_CONTEXT_DONE = 11,
	PERF_CP_CACHE_FLUSH = 12,
	PERF_CP_LONG_PREEMPTIONS = 13,
	PERF_CP_SQE_I_CACHE_STARVE = 14,
	PERF_CP_SQE_IDLE = 15,
	PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
	PERF_CP_SQE_PM4_STARVE_SDS = 17,
	PERF_CP_SQE_MRB_STARVE = 18,
	PERF_CP_SQE_RRB_STARVE = 19,
	PERF_CP_SQE_VSD_STARVE = 20,
	PERF_CP_VSD_DECODE_STARVE = 21,
	PERF_CP_SQE_PIPE_OUT_STALL = 22,
	PERF_CP_SQE_SYNC_STALL = 23,
	PERF_CP_SQE_PM4_WFI_STALL = 24,
	PERF_CP_SQE_SYS_WFI_STALL = 25,
	PERF_CP_SQE_T4_EXEC = 26,
	PERF_CP_SQE_LOAD_STATE_EXEC = 27,
	PERF_CP_SQE_SAVE_SDS_STATE = 28,
	PERF_CP_SQE_DRAW_EXEC = 29,
	PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
	PERF_CP_SQE_EXEC_PROFILED = 31,
	PERF_CP_MEMORY_POOL_EMPTY = 32,
	PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
	PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
	PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
	PERF_CP_AHB_STALL_SQE_GMU = 36,
	PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
	PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
	PERF_CP_CLUSTER0_EMPTY = 39,
	PERF_CP_CLUSTER1_EMPTY = 40,
	PERF_CP_CLUSTER2_EMPTY = 41,
	PERF_CP_CLUSTER3_EMPTY = 42,
	PERF_CP_CLUSTER4_EMPTY = 43,
	PERF_CP_CLUSTER5_EMPTY = 44,
	PERF_CP_PM4_DATA = 45,
	PERF_CP_PM4_HEADERS = 46,
	PERF_CP_VBIF_READ_BEATS = 47,
	PERF_CP_VBIF_WRITE_BEATS = 48,
	PERF_CP_SQE_INSTR_COUNTER = 49,
};

enum a6xx_rbbm_perfcounter_select {
	PERF_RBBM_ALWAYS_COUNT = 0,
	PERF_RBBM_ALWAYS_ON = 1,
	PERF_RBBM_TSE_BUSY = 2,
	PERF_RBBM_RAS_BUSY = 3,
	PERF_RBBM_PC_DCALL_BUSY = 4,
	PERF_RBBM_PC_VSD_BUSY = 5,
	PERF_RBBM_STATUS_MASKED = 6,
	PERF_RBBM_COM_BUSY = 7,
	PERF_RBBM_DCOM_BUSY = 8,
	PERF_RBBM_VBIF_BUSY = 9,
	PERF_RBBM_VSC_BUSY = 10,
	PERF_RBBM_TESS_BUSY = 11,
	PERF_RBBM_UCHE_BUSY = 12,
	PERF_RBBM_HLSQ_BUSY = 13,
};

enum a6xx_pc_perfcounter_select {
	PERF_PC_BUSY_CYCLES = 0,
	PERF_PC_WORKING_CYCLES = 1,
	PERF_PC_STALL_CYCLES_VFD = 2,
	PERF_PC_STALL_CYCLES_TSE = 3,
	PERF_PC_STALL_CYCLES_VPC = 4,
	PERF_PC_STALL_CYCLES_UCHE = 5,
	PERF_PC_STALL_CYCLES_TESS = 6,
	PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
	PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
	PERF_PC_PASS1_TF_STALL_CYCLES = 9,
	PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
	PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
	PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
	PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
	PERF_PC_STARVE_CYCLES_DI = 14,
	PERF_PC_VIS_STREAMS_LOADED = 15,
	PERF_PC_INSTANCES = 16,
	PERF_PC_VPC_PRIMITIVES = 17,
	PERF_PC_DEAD_PRIM = 18,
	PERF_PC_LIVE_PRIM = 19,
	PERF_PC_VERTEX_HITS = 20,
	PERF_PC_IA_VERTICES = 21,
	PERF_PC_IA_PRIMITIVES = 22,
	PERF_PC_GS_PRIMITIVES = 23,
	PERF_PC_HS_INVOCATIONS = 24,
	PERF_PC_DS_INVOCATIONS = 25,
	PERF_PC_VS_INVOCATIONS = 26,
	PERF_PC_GS_INVOCATIONS = 27,
	PERF_PC_DS_PRIMITIVES = 28,
	PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
	PERF_PC_3D_DRAWCALLS = 30,
	PERF_PC_2D_DRAWCALLS = 31,
	PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
	PERF_TESS_BUSY_CYCLES = 33,
	PERF_TESS_WORKING_CYCLES = 34,
	PERF_TESS_STALL_CYCLES_PC = 35,
	PERF_TESS_STARVE_CYCLES_PC = 36,
	PERF_PC_TSE_TRANSACTION = 37,
	PERF_PC_TSE_VERTEX = 38,
	PERF_PC_TESS_PC_UV_TRANS = 39,
	PERF_PC_TESS_PC_UV_PATCHES = 40,
	PERF_PC_TESS_FACTOR_TRANS = 41,
};

enum a6xx_vfd_perfcounter_select {
	PERF_VFD_BUSY_CYCLES = 0,
	PERF_VFD_STALL_CYCLES_UCHE = 1,
	PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
	PERF_VFD_STALL_CYCLES_SP_INFO = 3,
	PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
	PERF_VFD_STARVE_CYCLES_UCHE = 5,
	PERF_VFD_RBUFFER_FULL = 6,
	PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
	PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
	PERF_VFD_NUM_ATTRIBUTES = 9,
	PERF_VFD_UPPER_SHADER_FIBERS = 10,
	PERF_VFD_LOWER_SHADER_FIBERS = 11,
	PERF_VFD_MODE_0_FIBERS = 12,
	PERF_VFD_MODE_1_FIBERS = 13,
	PERF_VFD_MODE_2_FIBERS = 14,
	PERF_VFD_MODE_3_FIBERS = 15,
	PERF_VFD_MODE_4_FIBERS = 16,
	PERF_VFD_TOTAL_VERTICES = 17,
	PERF_VFDP_STALL_CYCLES_VFD = 18,
	PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
	PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
	PERF_VFDP_STARVE_CYCLES_PC = 21,
	PERF_VFDP_VS_STAGE_WAVES = 22,
};

enum a6xx_hlsq_perfcounter_select {
	PERF_HLSQ_BUSY_CYCLES = 0,
	PERF_HLSQ_STALL_CYCLES_UCHE = 1,
	PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
	PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
	PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
	PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
	PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
	PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
	PERF_HLSQ_QUADS = 8,
	PERF_HLSQ_CS_INVOCATIONS = 9,
	PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
	PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
	PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
	PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
	PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
	PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
	PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
	PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
	PERF_HLSQ_STALL_CYCLES_VPC = 18,
	PERF_HLSQ_PIXELS = 19,
	PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
};

enum a6xx_vpc_perfcounter_select {
	PERF_VPC_BUSY_CYCLES = 0,
	PERF_VPC_WORKING_CYCLES = 1,
	PERF_VPC_STALL_CYCLES_UCHE = 2,
	PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
	PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
	PERF_VPC_STALL_CYCLES_PC = 5,
	PERF_VPC_STALL_CYCLES_SP_LM = 6,
	PERF_VPC_STARVE_CYCLES_SP = 7,
	PERF_VPC_STARVE_CYCLES_LRZ = 8,
	PERF_VPC_PC_PRIMITIVES = 9,
	PERF_VPC_SP_COMPONENTS = 10,
	PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
	PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
	PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
	PERF_VPC_LM_TRANSACTION = 14,
	PERF_VPC_STREAMOUT_TRANSACTION = 15,
	PERF_VPC_VS_BUSY_CYCLES = 16,
	PERF_VPC_PS_BUSY_CYCLES = 17,
	PERF_VPC_VS_WORKING_CYCLES = 18,
	PERF_VPC_PS_WORKING_CYCLES = 19,
	PERF_VPC_STARVE_CYCLES_RB = 20,
	PERF_VPC_NUM_VPCRAM_READ_POS = 21,
	PERF_VPC_WIT_FULL_CYCLES = 22,
	PERF_VPC_VPCRAM_FULL_CYCLES = 23,
	PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
	PERF_VPC_NUM_VPCRAM_WRITE = 25,
	PERF_VPC_NUM_VPCRAM_READ_SO = 26,
	PERF_VPC_NUM_ATTR_REQ_LM = 27,
};

enum a6xx_tse_perfcounter_select {
	PERF_TSE_BUSY_CYCLES = 0,
	PERF_TSE_CLIPPING_CYCLES = 1,
	PERF_TSE_STALL_CYCLES_RAS = 2,
	PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
	PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
	PERF_TSE_STARVE_CYCLES_PC = 5,
	PERF_TSE_INPUT_PRIM = 6,
	PERF_TSE_INPUT_NULL_PRIM = 7,
	PERF_TSE_TRIVAL_REJ_PRIM = 8,
	PERF_TSE_CLIPPED_PRIM = 9,
	PERF_TSE_ZERO_AREA_PRIM = 10,
	PERF_TSE_FACENESS_CULLED_PRIM = 11,
	PERF_TSE_ZERO_PIXEL_PRIM = 12,
	PERF_TSE_OUTPUT_NULL_PRIM = 13,
	PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
	PERF_TSE_CINVOCATION = 15,
	PERF_TSE_CPRIMITIVES = 16,
	PERF_TSE_2D_INPUT_PRIM = 17,
	PERF_TSE_2D_ALIVE_CYCLES = 18,
	PERF_TSE_CLIP_PLANES = 19,
};

enum a6xx_ras_perfcounter_select {
	PERF_RAS_BUSY_CYCLES = 0,
	PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
	PERF_RAS_STALL_CYCLES_LRZ = 2,
	PERF_RAS_STARVE_CYCLES_TSE = 3,
	PERF_RAS_SUPER_TILES = 4,
	PERF_RAS_8X4_TILES = 5,
	PERF_RAS_MASKGEN_ACTIVE = 6,
	PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
	PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
	PERF_RAS_PRIM_KILLED_INVISILBE = 9,
	PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
	PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
	PERF_RAS_BLOCKS = 12,
};

enum a6xx_uche_perfcounter_select {
	PERF_UCHE_BUSY_CYCLES = 0,
	PERF_UCHE_STALL_CYCLES_ARBITER = 1,
	PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
	PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
	PERF_UCHE_VBIF_READ_BEATS_TP = 4,
	PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
	PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
	PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
	PERF_UCHE_VBIF_READ_BEATS_SP = 8,
	PERF_UCHE_READ_REQUESTS_TP = 9,
	PERF_UCHE_READ_REQUESTS_VFD = 10,
	PERF_UCHE_READ_REQUESTS_HLSQ = 11,
	PERF_UCHE_READ_REQUESTS_LRZ = 12,
	PERF_UCHE_READ_REQUESTS_SP = 13,
	PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
	PERF_UCHE_WRITE_REQUESTS_SP = 15,
	PERF_UCHE_WRITE_REQUESTS_VPC = 16,
	PERF_UCHE_WRITE_REQUESTS_VSC = 17,
	PERF_UCHE_EVICTS = 18,
	PERF_UCHE_BANK_REQ0 = 19,
	PERF_UCHE_BANK_REQ1 = 20,
	PERF_UCHE_BANK_REQ2 = 21,
	PERF_UCHE_BANK_REQ3 = 22,
	PERF_UCHE_BANK_REQ4 = 23,
	PERF_UCHE_BANK_REQ5 = 24,
	PERF_UCHE_BANK_REQ6 = 25,
	PERF_UCHE_BANK_REQ7 = 26,
	PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
	PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
	PERF_UCHE_GMEM_READ_BEATS = 29,
	PERF_UCHE_TPH_REF_FULL = 30,
	PERF_UCHE_TPH_VICTIM_FULL = 31,
	PERF_UCHE_TPH_EXT_FULL = 32,
	PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
	PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
	PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
	PERF_UCHE_VBIF_READ_BEATS_PC = 36,
	PERF_UCHE_READ_REQUESTS_PC = 37,
	PERF_UCHE_RAM_READ_REQ = 38,
	PERF_UCHE_RAM_WRITE_REQ = 39,
};

enum a6xx_tp_perfcounter_select {
	PERF_TP_BUSY_CYCLES = 0,
	PERF_TP_STALL_CYCLES_UCHE = 1,
	PERF_TP_LATENCY_CYCLES = 2,
	PERF_TP_LATENCY_TRANS = 3,
	PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
	PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
	PERF_TP_L1_CACHELINE_REQUESTS = 6,
	PERF_TP_L1_CACHELINE_MISSES = 7,
	PERF_TP_SP_TP_TRANS = 8,
	PERF_TP_TP_SP_TRANS = 9,
	PERF_TP_OUTPUT_PIXELS = 10,
	PERF_TP_FILTER_WORKLOAD_16BIT = 11,
	PERF_TP_FILTER_WORKLOAD_32BIT = 12,
	PERF_TP_QUADS_RECEIVED = 13,
	PERF_TP_QUADS_OFFSET = 14,
	PERF_TP_QUADS_SHADOW = 15,
	PERF_TP_QUADS_ARRAY = 16,
	PERF_TP_QUADS_GRADIENT = 17,
	PERF_TP_QUADS_1D = 18,
	PERF_TP_QUADS_2D = 19,
	PERF_TP_QUADS_BUFFER = 20,
	PERF_TP_QUADS_3D = 21,
	PERF_TP_QUADS_CUBE = 22,
	PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
	PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
	PERF_TP_OUTPUT_PIXELS_POINT = 25,
	PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
	PERF_TP_OUTPUT_PIXELS_MIP = 27,
	PERF_TP_OUTPUT_PIXELS_ANISO = 28,
	PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
	PERF_TP_FLAG_CACHE_REQUESTS = 30,
	PERF_TP_FLAG_CACHE_MISSES = 31,
	PERF_TP_L1_5_L2_REQUESTS = 32,
	PERF_TP_2D_OUTPUT_PIXELS = 33,
	PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
	PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
	PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
	PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
	PERF_TP_TPA2TPC_TRANS = 38,
	PERF_TP_L1_MISSES_ASTC_1TILE = 39,
	PERF_TP_L1_MISSES_ASTC_2TILE = 40,
	PERF_TP_L1_MISSES_ASTC_4TILE = 41,
	PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
	PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
	PERF_TP_L1_BANK_CONFLICT = 44,
	PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
	PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
	PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
	PERF_TP_FRONTEND_WORKING_CYCLES = 48,
	PERF_TP_L1_TAG_WORKING_CYCLES = 49,
	PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
	PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
	PERF_TP_BACKEND_WORKING_CYCLES = 52,
	PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
	PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
	PERF_TP_STARVE_CYCLES_SP = 55,
	PERF_TP_STARVE_CYCLES_UCHE = 56,
};

enum a6xx_sp_perfcounter_select {
	PERF_SP_BUSY_CYCLES = 0,
	PERF_SP_ALU_WORKING_CYCLES = 1,
	PERF_SP_EFU_WORKING_CYCLES = 2,
	PERF_SP_STALL_CYCLES_VPC = 3,
	PERF_SP_STALL_CYCLES_TP = 4,
	PERF_SP_STALL_CYCLES_UCHE = 5,
	PERF_SP_STALL_CYCLES_RB = 6,
	PERF_SP_NON_EXECUTION_CYCLES = 7,
	PERF_SP_WAVE_CONTEXTS = 8,
	PERF_SP_WAVE_CONTEXT_CYCLES = 9,
	PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
	PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
	PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
	PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
	PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
	PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
	PERF_SP_WAVE_CTRL_CYCLES = 16,
	PERF_SP_WAVE_LOAD_CYCLES = 17,
	PERF_SP_WAVE_EMIT_CYCLES = 18,
	PERF_SP_WAVE_NOP_CYCLES = 19,
	PERF_SP_WAVE_WAIT_CYCLES = 20,
	PERF_SP_WAVE_FETCH_CYCLES = 21,
	PERF_SP_WAVE_IDLE_CYCLES = 22,
	PERF_SP_WAVE_END_CYCLES = 23,
	PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
	PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
	PERF_SP_WAVE_JOIN_CYCLES = 26,
	PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
	PERF_SP_LM_STORE_INSTRUCTIONS = 28,
	PERF_SP_LM_ATOMICS = 29,
	PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
	PERF_SP_GM_STORE_INSTRUCTIONS = 31,
	PERF_SP_GM_ATOMICS = 32,
	PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
	PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
	PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
	PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
	PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
	PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
	PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
	PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
	PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
	PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
	PERF_SP_VS_INSTRUCTIONS = 43,
	PERF_SP_FS_INSTRUCTIONS = 44,
	PERF_SP_ADDR_LOCK_COUNT = 45,
	PERF_SP_UCHE_READ_TRANS = 46,
	PERF_SP_UCHE_WRITE_TRANS = 47,
	PERF_SP_EXPORT_VPC_TRANS = 48,
	PERF_SP_EXPORT_RB_TRANS = 49,
	PERF_SP_PIXELS_KILLED = 50,
	PERF_SP_ICL1_REQUESTS = 51,
	PERF_SP_ICL1_MISSES = 52,
	PERF_SP_HS_INSTRUCTIONS = 53,
	PERF_SP_DS_INSTRUCTIONS = 54,
	PERF_SP_GS_INSTRUCTIONS = 55,
	PERF_SP_CS_INSTRUCTIONS = 56,
	PERF_SP_GPR_READ = 57,
	PERF_SP_GPR_WRITE = 58,
	PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
	PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
	PERF_SP_LM_BANK_CONFLICTS = 61,
	PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
	PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
	PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
	PERF_SP_LM_WORKING_CYCLES = 65,
	PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
	PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
	PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
	PERF_SP_STARVE_CYCLES_HLSQ = 69,
	PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
	PERF_SP_WORKING_EU = 71,
	PERF_SP_ANY_EU_WORKING = 72,
	PERF_SP_WORKING_EU_FS_STAGE = 73,
	PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
	PERF_SP_WORKING_EU_VS_STAGE = 75,
	PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
	PERF_SP_WORKING_EU_CS_STAGE = 77,
	PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
	PERF_SP_GPR_READ_PREFETCH = 79,
	PERF_SP_GPR_READ_CONFLICT = 80,
	PERF_SP_GPR_WRITE_CONFLICT = 81,
	PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
	PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
	PERF_SP_EXECUTABLE_WAVES = 84,
};

enum a6xx_rb_perfcounter_select {
	PERF_RB_BUSY_CYCLES = 0,
	PERF_RB_STALL_CYCLES_HLSQ = 1,
	PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
	PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
	PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
	PERF_RB_STARVE_CYCLES_SP = 5,
	PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
	PERF_RB_STARVE_CYCLES_CCU = 7,
	PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
	PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
	PERF_RB_Z_WORKLOAD = 10,
	PERF_RB_HLSQ_ACTIVE = 11,
	PERF_RB_Z_READ = 12,
	PERF_RB_Z_WRITE = 13,
	PERF_RB_C_READ = 14,
	PERF_RB_C_WRITE = 15,
	PERF_RB_TOTAL_PASS = 16,
	PERF_RB_Z_PASS = 17,
	PERF_RB_Z_FAIL = 18,
	PERF_RB_S_FAIL = 19,
	PERF_RB_BLENDED_FXP_COMPONENTS = 20,
	PERF_RB_BLENDED_FP16_COMPONENTS = 21,
	PERF_RB_PS_INVOCATIONS = 22,
	PERF_RB_2D_ALIVE_CYCLES = 23,
	PERF_RB_2D_STALL_CYCLES_A2D = 24,
	PERF_RB_2D_STARVE_CYCLES_SRC = 25,
	PERF_RB_2D_STARVE_CYCLES_SP = 26,
	PERF_RB_2D_STARVE_CYCLES_DST = 27,
	PERF_RB_2D_VALID_PIXELS = 28,
	PERF_RB_3D_PIXELS = 29,
	PERF_RB_BLENDER_WORKING_CYCLES = 30,
	PERF_RB_ZPROC_WORKING_CYCLES = 31,
	PERF_RB_CPROC_WORKING_CYCLES = 32,
	PERF_RB_SAMPLER_WORKING_CYCLES = 33,
	PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
	PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
	PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
	PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
	PERF_RB_STALL_CYCLES_VPC = 38,
	PERF_RB_2D_INPUT_TRANS = 39,
	PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
	PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
	PERF_RB_BLENDED_FP32_COMPONENTS = 42,
	PERF_RB_COLOR_PIX_TILES = 43,
	PERF_RB_STALL_CYCLES_CCU = 44,
	PERF_RB_EARLY_Z_ARB3_GRANT = 45,
	PERF_RB_LATE_Z_ARB3_GRANT = 46,
	PERF_RB_EARLY_Z_SKIP_GRANT = 47,
};

enum a6xx_vsc_perfcounter_select {
	PERF_VSC_BUSY_CYCLES = 0,
	PERF_VSC_WORKING_CYCLES = 1,
	PERF_VSC_STALL_CYCLES_UCHE = 2,
	PERF_VSC_EOT_NUM = 3,
	PERF_VSC_INPUT_TILES = 4,
};

enum a6xx_ccu_perfcounter_select {
	PERF_CCU_BUSY_CYCLES = 0,
	PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
	PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
	PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
	PERF_CCU_DEPTH_BLOCKS = 4,
	PERF_CCU_COLOR_BLOCKS = 5,
	PERF_CCU_DEPTH_BLOCK_HIT = 6,
	PERF_CCU_COLOR_BLOCK_HIT = 7,
	PERF_CCU_PARTIAL_BLOCK_READ = 8,
	PERF_CCU_GMEM_READ = 9,
	PERF_CCU_GMEM_WRITE = 10,
	PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
	PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
	PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
	PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
	PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
	PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
	PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
	PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
	PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
	PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
	PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
	PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
	PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
	PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
	PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
	PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
	PERF_CCU_2D_RD_REQ = 27,
	PERF_CCU_2D_WR_REQ = 28,
};

enum a6xx_lrz_perfcounter_select {
	PERF_LRZ_BUSY_CYCLES = 0,
	PERF_LRZ_STARVE_CYCLES_RAS = 1,
	PERF_LRZ_STALL_CYCLES_RB = 2,
	PERF_LRZ_STALL_CYCLES_VSC = 3,
	PERF_LRZ_STALL_CYCLES_VPC = 4,
	PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
	PERF_LRZ_STALL_CYCLES_UCHE = 6,
	PERF_LRZ_LRZ_READ = 7,
	PERF_LRZ_LRZ_WRITE = 8,
	PERF_LRZ_READ_LATENCY = 9,
	PERF_LRZ_MERGE_CACHE_UPDATING = 10,
	PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
	PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
	PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
	PERF_LRZ_FULL_8X8_TILES = 14,
	PERF_LRZ_PARTIAL_8X8_TILES = 15,
	PERF_LRZ_TILE_KILLED = 16,
	PERF_LRZ_TOTAL_PIXEL = 17,
	PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
	PERF_LRZ_FULLY_COVERED_TILES = 19,
	PERF_LRZ_PARTIAL_COVERED_TILES = 20,
	PERF_LRZ_FEEDBACK_ACCEPT = 21,
	PERF_LRZ_FEEDBACK_DISCARD = 22,
	PERF_LRZ_FEEDBACK_STALL = 23,
	PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
	PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
	PERF_LRZ_STALL_CYCLES_VC = 26,
	PERF_LRZ_RAS_MASK_TRANS = 27,
};

enum a6xx_cmp_perfcounter_select {
	PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
	PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
	PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
	PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
	PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
	PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
	PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
	PERF_CMPDECMP_VBIF_READ_DATA = 7,
	PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
	PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
	PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
	PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
	PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
	PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
	PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
	PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
	PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
	PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
	PERF_CMPDECMP_2D_RD_DATA = 28,
	PERF_CMPDECMP_2D_WR_DATA = 29,
	PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
	PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
	PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
	PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
	PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
	PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
	PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
	PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
	PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
	PERF_CMPDECMP_2D_PIXELS = 39,
};

enum a6xx_2d_ifmt {
	R2D_UNORM8 = 16,
	R2D_INT32 = 7,
	R2D_INT16 = 6,
	R2D_INT8 = 5,
	R2D_FLOAT32 = 4,
	R2D_FLOAT16 = 3,
	R2D_UNORM8_SRGB = 1,
	R2D_RAW = 0,
};

enum a6xx_ztest_mode {
	A6XX_EARLY_Z = 0,
	A6XX_LATE_Z = 1,
	A6XX_EARLY_LRZ_LATE_Z = 2,
};

enum a6xx_rotation {
	ROTATE_0 = 0,
	ROTATE_90 = 1,
	ROTATE_180 = 2,
	ROTATE_270 = 3,
	ROTATE_HFLIP = 4,
	ROTATE_VFLIP = 5,
};

enum a6xx_tess_spacing {
	TESS_EQUAL = 0,
	TESS_FRACTIONAL_ODD = 2,
	TESS_FRACTIONAL_EVEN = 3,
};

enum a6xx_tess_output {
	TESS_POINTS = 0,
	TESS_LINES = 1,
	TESS_CW_TRIS = 2,
	TESS_CCW_TRIS = 3,
};

enum a6xx_tex_filter {
	A6XX_TEX_NEAREST = 0,
	A6XX_TEX_LINEAR = 1,
	A6XX_TEX_ANISO = 2,
	A6XX_TEX_CUBIC = 3,
};

enum a6xx_tex_clamp {
	A6XX_TEX_REPEAT = 0,
	A6XX_TEX_CLAMP_TO_EDGE = 1,
	A6XX_TEX_MIRROR_REPEAT = 2,
	A6XX_TEX_CLAMP_TO_BORDER = 3,
	A6XX_TEX_MIRROR_CLAMP = 4,
};

enum a6xx_tex_aniso {
	A6XX_TEX_ANISO_1 = 0,
	A6XX_TEX_ANISO_2 = 1,
	A6XX_TEX_ANISO_4 = 2,
	A6XX_TEX_ANISO_8 = 3,
	A6XX_TEX_ANISO_16 = 4,
};

enum a6xx_reduction_mode {
	A6XX_REDUCTION_MODE_AVERAGE = 0,
	A6XX_REDUCTION_MODE_MIN = 1,
	A6XX_REDUCTION_MODE_MAX = 2,
};

enum a6xx_tex_swiz {
	A6XX_TEX_X = 0,
	A6XX_TEX_Y = 1,
	A6XX_TEX_Z = 2,
	A6XX_TEX_W = 3,
	A6XX_TEX_ZERO = 4,
	A6XX_TEX_ONE = 5,
};

enum a6xx_tex_type {
	A6XX_TEX_1D = 0,
	A6XX_TEX_2D = 1,
	A6XX_TEX_CUBE = 2,
	A6XX_TEX_3D = 3,
};

#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR			0x00000002
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW	0x00000040
#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
#define A6XX_RBBM_INT_0_MASK_CP_SW				0x00000100
#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
#define A6XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
#define A6XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
#define A6XX_RBBM_INT_0_MASK_CP_RB				0x00008000
#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT			0x00800000
#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
#define A6XX_CP_INT_CP_OPCODE_ERROR				0x00000001
#define A6XX_CP_INT_CP_UCODE_ERROR				0x00000002
#define A6XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
#define A6XX_CP_INT_CP_AHB_ERROR				0x00000020
#define A6XX_CP_INT_CP_VSD_PARITY_ERROR				0x00000040
#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR			0x00000080
#define REG_A6XX_CP_RB_BASE					0x00000800

#define REG_A6XX_CP_RB_BASE_HI					0x00000801

#define REG_A6XX_CP_RB_CNTL					0x00000802

#define REG_A6XX_CP_RB_RPTR_ADDR_LO				0x00000804

#define REG_A6XX_CP_RB_RPTR_ADDR_HI				0x00000805

#define REG_A6XX_CP_RB_RPTR					0x00000806

#define REG_A6XX_CP_RB_WPTR					0x00000807

#define REG_A6XX_CP_SQE_CNTL					0x00000808

#define REG_A6XX_CP_CP2GMU_STATUS				0x00000812
#define A6XX_CP_CP2GMU_STATUS_IFPC				0x00000001

#define REG_A6XX_CP_HW_FAULT					0x00000821

#define REG_A6XX_CP_INTERRUPT_STATUS				0x00000823

#define REG_A6XX_CP_PROTECT_STATUS				0x00000824

#define REG_A6XX_CP_SQE_INSTR_BASE_LO				0x00000830

#define REG_A6XX_CP_SQE_INSTR_BASE_HI				0x00000831

#define REG_A6XX_CP_MISC_CNTL					0x00000840

#define REG_A6XX_CP_APRIV_CNTL					0x00000844

#define REG_A6XX_CP_ROQ_THRESHOLDS_1				0x000008c1
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK			0x000000ff
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT			0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK			0x0000ff00
#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT			8
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK		0x00ff0000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT		16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK		0xff000000
#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT		24
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
}

#define REG_A6XX_CP_ROQ_THRESHOLDS_2				0x000008c2
#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK		0x000001ff
#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT		0
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
}
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK			0xffff0000
#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT		16
static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
{
	return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
}

#define REG_A6XX_CP_MEM_POOL_SIZE				0x000008c3

#define REG_A6XX_CP_CHICKEN_DBG					0x00000841

#define REG_A6XX_CP_ADDR_MODE_CNTL				0x00000842

#define REG_A6XX_CP_DBG_ECO_CNTL				0x00000843

#define REG_A6XX_CP_PROTECT_CNTL				0x0000084f

static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }

static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }

static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }

static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0003ffff
#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
{
	return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
}
#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK			0x7ffc0000
#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT			18
static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
{
	return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
#define A6XX_CP_PROTECT_REG_READ				0x80000000

#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL				0x000008a0

#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO			0x000008a1

#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI			0x000008a2

#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO	0x000008a3

#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI	0x000008a4

#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO	0x000008a5

#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI	0x000008a6

#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO	0x000008a7

#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI	0x000008a8

#define REG_A6XX_CP_PERFCTR_CP_SEL_0				0x000008d0

#define REG_A6XX_CP_PERFCTR_CP_SEL_1				0x000008d1

#define REG_A6XX_CP_PERFCTR_CP_SEL_2				0x000008d2

#define REG_A6XX_CP_PERFCTR_CP_SEL_3				0x000008d3

#define REG_A6XX_CP_PERFCTR_CP_SEL_4				0x000008d4

#define REG_A6XX_CP_PERFCTR_CP_SEL_5				0x000008d5

#define REG_A6XX_CP_PERFCTR_CP_SEL_6				0x000008d6

#define REG_A6XX_CP_PERFCTR_CP_SEL_7				0x000008d7

#define REG_A6XX_CP_PERFCTR_CP_SEL_8				0x000008d8

#define REG_A6XX_CP_PERFCTR_CP_SEL_9				0x000008d9

#define REG_A6XX_CP_PERFCTR_CP_SEL_10				0x000008da

#define REG_A6XX_CP_PERFCTR_CP_SEL_11				0x000008db

#define REG_A6XX_CP_PERFCTR_CP_SEL_12				0x000008dc

#define REG_A6XX_CP_PERFCTR_CP_SEL_13				0x000008dd

#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO			0x00000900

#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI			0x00000901

#define REG_A6XX_CP_CRASH_DUMP_CNTL				0x00000902

#define REG_A6XX_CP_CRASH_DUMP_STATUS				0x00000903

#define REG_A6XX_CP_SQE_STAT_ADDR				0x00000908

#define REG_A6XX_CP_SQE_STAT_DATA				0x00000909

#define REG_A6XX_CP_DRAW_STATE_ADDR				0x0000090a

#define REG_A6XX_CP_DRAW_STATE_DATA				0x0000090b

#define REG_A6XX_CP_ROQ_DBG_ADDR				0x0000090c

#define REG_A6XX_CP_ROQ_DBG_DATA				0x0000090d

#define REG_A6XX_CP_MEM_POOL_DBG_ADDR				0x0000090e

#define REG_A6XX_CP_MEM_POOL_DBG_DATA				0x0000090f

#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR				0x00000910

#define REG_A6XX_CP_SQE_UCODE_DBG_DATA				0x00000911

#define REG_A6XX_CP_IB1_BASE					0x00000928

#define REG_A6XX_CP_IB1_BASE_HI					0x00000929

#define REG_A6XX_CP_IB1_REM_SIZE				0x0000092a

#define REG_A6XX_CP_IB2_BASE					0x0000092b

#define REG_A6XX_CP_IB2_BASE_HI					0x0000092c

#define REG_A6XX_CP_IB2_REM_SIZE				0x0000092d

#define REG_A6XX_CP_SDS_BASE					0x0000092e

#define REG_A6XX_CP_SDS_BASE_HI					0x0000092f

#define REG_A6XX_CP_SDS_REM_SIZE				0x0000092e

#define REG_A6XX_CP_BIN_SIZE_ADDRESS				0x00000931

#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI				0x00000932

#define REG_A6XX_CP_BIN_DATA_ADDR				0x00000934

#define REG_A6XX_CP_BIN_DATA_ADDR_HI				0x00000935

#define REG_A6XX_CP_CSQ_IB1_STAT				0x00000949
#define A6XX_CP_CSQ_IB1_STAT_REM__MASK				0xffff0000
#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT				16
static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
{
	return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
}

#define REG_A6XX_CP_CSQ_IB2_STAT				0x0000094a
#define A6XX_CP_CSQ_IB2_STAT_REM__MASK				0xffff0000
#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT				16
static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
{
	return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
}

#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO			0x00000980

#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI			0x00000981

#define REG_A6XX_CP_AHB_CNTL					0x0000098d

#define REG_A6XX_CP_APERTURE_CNTL_HOST				0x00000a00

#define REG_A6XX_CP_APERTURE_CNTL_CD				0x00000a03

#define REG_A6XX_VSC_ADDR_MODE_CNTL				0x00000c01

#define REG_A6XX_RBBM_INT_0_STATUS				0x00000201

#define REG_A6XX_RBBM_STATUS					0x00000210
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB			0x00800000
#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP			0x00400000
#define A6XX_RBBM_STATUS_HLSQ_BUSY				0x00200000
#define A6XX_RBBM_STATUS_VSC_BUSY				0x00100000
#define A6XX_RBBM_STATUS_TPL1_BUSY				0x00080000
#define A6XX_RBBM_STATUS_SP_BUSY				0x00040000
#define A6XX_RBBM_STATUS_UCHE_BUSY				0x00020000
#define A6XX_RBBM_STATUS_VPC_BUSY				0x00010000
#define A6XX_RBBM_STATUS_VFD_BUSY				0x00008000
#define A6XX_RBBM_STATUS_TESS_BUSY				0x00004000
#define A6XX_RBBM_STATUS_PC_VSD_BUSY				0x00002000
#define A6XX_RBBM_STATUS_PC_DCALL_BUSY				0x00001000
#define A6XX_RBBM_STATUS_COM_DCOM_BUSY				0x00000800
#define A6XX_RBBM_STATUS_LRZ_BUSY				0x00000400
#define A6XX_RBBM_STATUS_A2D_BUSY				0x00000200
#define A6XX_RBBM_STATUS_CCU_BUSY				0x00000100
#define A6XX_RBBM_STATUS_RB_BUSY				0x00000080
#define A6XX_RBBM_STATUS_RAS_BUSY				0x00000040
#define A6XX_RBBM_STATUS_TSE_BUSY				0x00000020
#define A6XX_RBBM_STATUS_VBIF_BUSY				0x00000010
#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY				0x00000008
#define A6XX_RBBM_STATUS_CP_BUSY				0x00000004
#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER			0x00000002
#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER			0x00000001

#define REG_A6XX_RBBM_STATUS3					0x00000213
#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000

#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS			0x00000215

#define REG_A6XX_RBBM_PERFCTR_CP_0_LO				0x00000400

#define REG_A6XX_RBBM_PERFCTR_CP_0_HI				0x00000401

#define REG_A6XX_RBBM_PERFCTR_CP_1_LO				0x00000402

#define REG_A6XX_RBBM_PERFCTR_CP_1_HI				0x00000403

#define REG_A6XX_RBBM_PERFCTR_CP_2_LO				0x00000404

#define REG_A6XX_RBBM_PERFCTR_CP_2_HI				0x00000405

#define REG_A6XX_RBBM_PERFCTR_CP_3_LO				0x00000406

#define REG_A6XX_RBBM_PERFCTR_CP_3_HI				0x00000407

#define REG_A6XX_RBBM_PERFCTR_CP_4_LO				0x00000408

#define REG_A6XX_RBBM_PERFCTR_CP_4_HI				0x00000409

#define REG_A6XX_RBBM_PERFCTR_CP_5_LO				0x0000040a

#define REG_A6XX_RBBM_PERFCTR_CP_5_HI				0x0000040b

#define REG_A6XX_RBBM_PERFCTR_CP_6_LO				0x0000040c

#define REG_A6XX_RBBM_PERFCTR_CP_6_HI				0x0000040d

#define REG_A6XX_RBBM_PERFCTR_CP_7_LO				0x0000040e

#define REG_A6XX_RBBM_PERFCTR_CP_7_HI				0x0000040f

#define REG_A6XX_RBBM_PERFCTR_CP_8_LO				0x00000410

#define REG_A6XX_RBBM_PERFCTR_CP_8_HI				0x00000411

#define REG_A6XX_RBBM_PERFCTR_CP_9_LO				0x00000412

#define REG_A6XX_RBBM_PERFCTR_CP_9_HI				0x00000413

#define REG_A6XX_RBBM_PERFCTR_CP_10_LO				0x00000414

#define REG_A6XX_RBBM_PERFCTR_CP_10_HI				0x00000415

#define REG_A6XX_RBBM_PERFCTR_CP_11_LO				0x00000416

#define REG_A6XX_RBBM_PERFCTR_CP_11_HI				0x00000417

#define REG_A6XX_RBBM_PERFCTR_CP_12_LO				0x00000418

#define REG_A6XX_RBBM_PERFCTR_CP_12_HI				0x00000419

#define REG_A6XX_RBBM_PERFCTR_CP_13_LO				0x0000041a

#define REG_A6XX_RBBM_PERFCTR_CP_13_HI				0x0000041b

#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO				0x0000041c

#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI				0x0000041d

#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO				0x0000041e

#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI				0x0000041f

#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO				0x00000420

#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI				0x00000421

#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO				0x00000422

#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI				0x00000423

#define REG_A6XX_RBBM_PERFCTR_PC_0_LO				0x00000424

#define REG_A6XX_RBBM_PERFCTR_PC_0_HI				0x00000425

#define REG_A6XX_RBBM_PERFCTR_PC_1_LO				0x00000426

#define REG_A6XX_RBBM_PERFCTR_PC_1_HI				0x00000427

#define REG_A6XX_RBBM_PERFCTR_PC_2_LO				0x00000428

#define REG_A6XX_RBBM_PERFCTR_PC_2_HI				0x00000429

#define REG_A6XX_RBBM_PERFCTR_PC_3_LO				0x0000042a

#define REG_A6XX_RBBM_PERFCTR_PC_3_HI				0x0000042b

#define REG_A6XX_RBBM_PERFCTR_PC_4_LO				0x0000042c

#define REG_A6XX_RBBM_PERFCTR_PC_4_HI				0x0000042d

#define REG_A6XX_RBBM_PERFCTR_PC_5_LO				0x0000042e

#define REG_A6XX_RBBM_PERFCTR_PC_5_HI				0x0000042f

#define REG_A6XX_RBBM_PERFCTR_PC_6_LO				0x00000430

#define REG_A6XX_RBBM_PERFCTR_PC_6_HI				0x00000431

#define REG_A6XX_RBBM_PERFCTR_PC_7_LO				0x00000432

#define REG_A6XX_RBBM_PERFCTR_PC_7_HI				0x00000433

#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO				0x00000434

#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI				0x00000435

#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO				0x00000436

#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI				0x00000437

#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO				0x00000438

#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI				0x00000439

#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO				0x0000043a

#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI				0x0000043b

#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO				0x0000043c

#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI				0x0000043d

#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO				0x0000043e

#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI				0x0000043f

#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO				0x00000440

#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI				0x00000441

#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO				0x00000442

#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI				0x00000443

#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO				0x00000444

#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI				0x00000445

#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO				0x00000446

#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI				0x00000447

#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO				0x00000448

#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI				0x00000449

#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO				0x0000044a

#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI				0x0000044b

#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO				0x0000044c

#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI				0x0000044d

#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO				0x0000044e

#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI				0x0000044f

#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO				0x00000450

#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI				0x00000451

#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO				0x00000452

#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI				0x00000453

#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO				0x00000454

#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI				0x00000455

#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO				0x00000456

#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI				0x00000457

#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO				0x00000458

#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI				0x00000459

#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO				0x0000045a

#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI				0x0000045b

#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO				0x0000045c

#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI				0x0000045d

#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO				0x0000045e

#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI				0x0000045f

#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO				0x00000460

#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI				0x00000461

#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO				0x00000462

#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI				0x00000463

#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO				0x00000464

#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI				0x00000465

#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO				0x00000466

#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI				0x00000467

#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO				0x00000468

#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI				0x00000469

#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO				0x0000046a

#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI				0x0000046b

#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO				0x0000046c

#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI				0x0000046d

#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO				0x0000046e

#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI				0x0000046f

#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO				0x00000470

#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI				0x00000471

#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO				0x00000472

#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI				0x00000473

#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO				0x00000474

#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI				0x00000475

#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO				0x00000476

#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI				0x00000477

#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO				0x00000478

#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI				0x00000479

#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO				0x0000047a

#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI				0x0000047b

#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO				0x0000047c

#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI				0x0000047d

#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO				0x0000047e

#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI				0x0000047f

#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO				0x00000480

#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI				0x00000481

#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO				0x00000482

#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI				0x00000483

#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO				0x00000484

#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI				0x00000485

#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO				0x00000486

#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI				0x00000487

#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO				0x00000488

#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI				0x00000489

#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO			0x0000048a

#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI			0x0000048b

#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO			0x0000048c

#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI			0x0000048d

#define REG_A6XX_RBBM_PERFCTR_TP_0_LO				0x0000048e

#define REG_A6XX_RBBM_PERFCTR_TP_0_HI				0x0000048f

#define REG_A6XX_RBBM_PERFCTR_TP_1_LO				0x00000490

#define REG_A6XX_RBBM_PERFCTR_TP_1_HI				0x00000491

#define REG_A6XX_RBBM_PERFCTR_TP_2_LO				0x00000492

#define REG_A6XX_RBBM_PERFCTR_TP_2_HI				0x00000493

#define REG_A6XX_RBBM_PERFCTR_TP_3_LO				0x00000494

#define REG_A6XX_RBBM_PERFCTR_TP_3_HI				0x00000495

#define REG_A6XX_RBBM_PERFCTR_TP_4_LO				0x00000496

#define REG_A6XX_RBBM_PERFCTR_TP_4_HI				0x00000497

#define REG_A6XX_RBBM_PERFCTR_TP_5_LO				0x00000498

#define REG_A6XX_RBBM_PERFCTR_TP_5_HI				0x00000499

#define REG_A6XX_RBBM_PERFCTR_TP_6_LO				0x0000049a

#define REG_A6XX_RBBM_PERFCTR_TP_6_HI				0x0000049b

#define REG_A6XX_RBBM_PERFCTR_TP_7_LO				0x0000049c

#define REG_A6XX_RBBM_PERFCTR_TP_7_HI				0x0000049d

#define REG_A6XX_RBBM_PERFCTR_TP_8_LO				0x0000049e

#define REG_A6XX_RBBM_PERFCTR_TP_8_HI				0x0000049f

#define REG_A6XX_RBBM_PERFCTR_TP_9_LO				0x000004a0

#define REG_A6XX_RBBM_PERFCTR_TP_9_HI				0x000004a1

#define REG_A6XX_RBBM_PERFCTR_TP_10_LO				0x000004a2

#define REG_A6XX_RBBM_PERFCTR_TP_10_HI				0x000004a3

#define REG_A6XX_RBBM_PERFCTR_TP_11_LO				0x000004a4

#define REG_A6XX_RBBM_PERFCTR_TP_11_HI				0x000004a5

#define REG_A6XX_RBBM_PERFCTR_SP_0_LO				0x000004a6

#define REG_A6XX_RBBM_PERFCTR_SP_0_HI				0x000004a7

#define REG_A6XX_RBBM_PERFCTR_SP_1_LO				0x000004a8

#define REG_A6XX_RBBM_PERFCTR_SP_1_HI				0x000004a9

#define REG_A6XX_RBBM_PERFCTR_SP_2_LO				0x000004aa

#define REG_A6XX_RBBM_PERFCTR_SP_2_HI				0x000004ab

#define REG_A6XX_RBBM_PERFCTR_SP_3_LO				0x000004ac

#define REG_A6XX_RBBM_PERFCTR_SP_3_HI				0x000004ad

#define REG_A6XX_RBBM_PERFCTR_SP_4_LO				0x000004ae

#define REG_A6XX_RBBM_PERFCTR_SP_4_HI				0x000004af

#define REG_A6XX_RBBM_PERFCTR_SP_5_LO				0x000004b0

#define REG_A6XX_RBBM_PERFCTR_SP_5_HI				0x000004b1

#define REG_A6XX_RBBM_PERFCTR_SP_6_LO				0x000004b2

#define REG_A6XX_RBBM_PERFCTR_SP_6_HI				0x000004b3

#define REG_A6XX_RBBM_PERFCTR_SP_7_LO				0x000004b4

#define REG_A6XX_RBBM_PERFCTR_SP_7_HI				0x000004b5

#define REG_A6XX_RBBM_PERFCTR_SP_8_LO				0x000004b6

#define REG_A6XX_RBBM_PERFCTR_SP_8_HI				0x000004b7

#define REG_A6XX_RBBM_PERFCTR_SP_9_LO				0x000004b8

#define REG_A6XX_RBBM_PERFCTR_SP_9_HI				0x000004b9

#define REG_A6XX_RBBM_PERFCTR_SP_10_LO				0x000004ba

#define REG_A6XX_RBBM_PERFCTR_SP_10_HI				0x000004bb

#define REG_A6XX_RBBM_PERFCTR_SP_11_LO				0x000004bc

#define REG_A6XX_RBBM_PERFCTR_SP_11_HI				0x000004bd

#define REG_A6XX_RBBM_PERFCTR_SP_12_LO				0x000004be

#define REG_A6XX_RBBM_PERFCTR_SP_12_HI				0x000004bf

#define REG_A6XX_RBBM_PERFCTR_SP_13_LO				0x000004c0

#define REG_A6XX_RBBM_PERFCTR_SP_13_HI				0x000004c1

#define REG_A6XX_RBBM_PERFCTR_SP_14_LO				0x000004c2

#define REG_A6XX_RBBM_PERFCTR_SP_14_HI				0x000004c3

#define REG_A6XX_RBBM_PERFCTR_SP_15_LO				0x000004c4

#define REG_A6XX_RBBM_PERFCTR_SP_15_HI				0x000004c5

#define REG_A6XX_RBBM_PERFCTR_SP_16_LO				0x000004c6

#define REG_A6XX_RBBM_PERFCTR_SP_16_HI				0x000004c7

#define REG_A6XX_RBBM_PERFCTR_SP_17_LO				0x000004c8

#define REG_A6XX_RBBM_PERFCTR_SP_17_HI				0x000004c9

#define REG_A6XX_RBBM_PERFCTR_SP_18_LO				0x000004ca

#define REG_A6XX_RBBM_PERFCTR_SP_18_HI				0x000004cb

#define REG_A6XX_RBBM_PERFCTR_SP_19_LO				0x000004cc

#define REG_A6XX_RBBM_PERFCTR_SP_19_HI				0x000004cd

#define REG_A6XX_RBBM_PERFCTR_SP_20_LO				0x000004ce

#define REG_A6XX_RBBM_PERFCTR_SP_20_HI				0x000004cf

#define REG_A6XX_RBBM_PERFCTR_SP_21_LO				0x000004d0

#define REG_A6XX_RBBM_PERFCTR_SP_21_HI				0x000004d1

#define REG_A6XX_RBBM_PERFCTR_SP_22_LO				0x000004d2

#define REG_A6XX_RBBM_PERFCTR_SP_22_HI				0x000004d3

#define REG_A6XX_RBBM_PERFCTR_SP_23_LO				0x000004d4

#define REG_A6XX_RBBM_PERFCTR_SP_23_HI				0x000004d5

#define REG_A6XX_RBBM_PERFCTR_RB_0_LO				0x000004d6

#define REG_A6XX_RBBM_PERFCTR_RB_0_HI				0x000004d7

#define REG_A6XX_RBBM_PERFCTR_RB_1_LO				0x000004d8

#define REG_A6XX_RBBM_PERFCTR_RB_1_HI				0x000004d9

#define REG_A6XX_RBBM_PERFCTR_RB_2_LO				0x000004da

#define REG_A6XX_RBBM_PERFCTR_RB_2_HI				0x000004db

#define REG_A6XX_RBBM_PERFCTR_RB_3_LO				0x000004dc

#define REG_A6XX_RBBM_PERFCTR_RB_3_HI				0x000004dd

#define REG_A6XX_RBBM_PERFCTR_RB_4_LO				0x000004de

#define REG_A6XX_RBBM_PERFCTR_RB_4_HI				0x000004df

#define REG_A6XX_RBBM_PERFCTR_RB_5_LO				0x000004e0

#define REG_A6XX_RBBM_PERFCTR_RB_5_HI				0x000004e1

#define REG_A6XX_RBBM_PERFCTR_RB_6_LO				0x000004e2

#define REG_A6XX_RBBM_PERFCTR_RB_6_HI				0x000004e3

#define REG_A6XX_RBBM_PERFCTR_RB_7_LO				0x000004e4

#define REG_A6XX_RBBM_PERFCTR_RB_7_HI				0x000004e5

#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO				0x000004e6

#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI				0x000004e7

#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO				0x000004e8

#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI				0x000004e9

#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO				0x000004ea

#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI				0x000004eb

#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO				0x000004ec

#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI				0x000004ed

#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO				0x000004ee

#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI				0x000004ef

#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO				0x000004f0

#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI				0x000004f1

#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO				0x000004f2

#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI				0x000004f3

#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO				0x000004f4

#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI				0x000004f5

#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO				0x000004f6

#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI				0x000004f7

#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO				0x000004f8

#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI				0x000004f9

#define REG_A6XX_RBBM_PERFCTR_CNTL				0x00000500

#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0				0x00000501

#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1				0x00000502

#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2				0x00000503

#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3				0x00000504

#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000505

#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000506

#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0			0x00000507

#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1			0x00000508

#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2			0x00000509

#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3			0x0000050a

#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000050b

#define REG_A6XX_RBBM_ISDB_CNT					0x00000533

#define REG_A6XX_RBBM_PRIMCTR_0_LO				0x00000540

#define REG_A6XX_RBBM_PRIMCTR_0_HI				0x00000541

#define REG_A6XX_RBBM_PRIMCTR_1_LO				0x00000542

#define REG_A6XX_RBBM_PRIMCTR_1_HI				0x00000543

#define REG_A6XX_RBBM_PRIMCTR_2_LO				0x00000544

#define REG_A6XX_RBBM_PRIMCTR_2_HI				0x00000545

#define REG_A6XX_RBBM_PRIMCTR_3_LO				0x00000546

#define REG_A6XX_RBBM_PRIMCTR_3_HI				0x00000547

#define REG_A6XX_RBBM_PRIMCTR_4_LO				0x00000548

#define REG_A6XX_RBBM_PRIMCTR_4_HI				0x00000549

#define REG_A6XX_RBBM_PRIMCTR_5_LO				0x0000054a

#define REG_A6XX_RBBM_PRIMCTR_5_HI				0x0000054b

#define REG_A6XX_RBBM_PRIMCTR_6_LO				0x0000054c

#define REG_A6XX_RBBM_PRIMCTR_6_HI				0x0000054d

#define REG_A6XX_RBBM_PRIMCTR_7_LO				0x0000054e

#define REG_A6XX_RBBM_PRIMCTR_7_HI				0x0000054f

#define REG_A6XX_RBBM_PRIMCTR_8_LO				0x00000550

#define REG_A6XX_RBBM_PRIMCTR_8_HI				0x00000551

#define REG_A6XX_RBBM_PRIMCTR_9_LO				0x00000552

#define REG_A6XX_RBBM_PRIMCTR_9_HI				0x00000553

#define REG_A6XX_RBBM_PRIMCTR_10_LO				0x00000554

#define REG_A6XX_RBBM_PRIMCTR_10_HI				0x00000555

#define REG_A6XX_RBBM_SECVID_TRUST_CNTL				0x0000f400

#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800

#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI		0x0000f801

#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802

#define REG_A6XX_RBBM_SECVID_TSB_CNTL				0x0000f803

#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810

#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL			0x00000010

#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL			0x00000011

#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD			0x0000001c
#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE		0x00000001

#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000001f

#define REG_A6XX_RBBM_INT_CLEAR_CMD				0x00000037

#define REG_A6XX_RBBM_INT_0_MASK				0x00000038

#define REG_A6XX_RBBM_SP_HYST_CNT				0x00000042

#define REG_A6XX_RBBM_SW_RESET_CMD				0x00000043

#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT				0x00000044

#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045

#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046

#define REG_A6XX_RBBM_CLOCK_CNTL				0x000000ae

#define REG_A6XX_RBBM_CLOCK_CNTL_SP0				0x000000b0

#define REG_A6XX_RBBM_CLOCK_CNTL_SP1				0x000000b1

#define REG_A6XX_RBBM_CLOCK_CNTL_SP2				0x000000b2

#define REG_A6XX_RBBM_CLOCK_CNTL_SP3				0x000000b3

#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0				0x000000b4

#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1				0x000000b5

#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2				0x000000b6

#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3				0x000000b7

#define REG_A6XX_RBBM_CLOCK_DELAY_SP0				0x000000b8

#define REG_A6XX_RBBM_CLOCK_DELAY_SP1				0x000000b9

#define REG_A6XX_RBBM_CLOCK_DELAY_SP2				0x000000ba

#define REG_A6XX_RBBM_CLOCK_DELAY_SP3				0x000000bb

#define REG_A6XX_RBBM_CLOCK_HYST_SP0				0x000000bc

#define REG_A6XX_RBBM_CLOCK_HYST_SP1				0x000000bd

#define REG_A6XX_RBBM_CLOCK_HYST_SP2				0x000000be

#define REG_A6XX_RBBM_CLOCK_HYST_SP3				0x000000bf

#define REG_A6XX_RBBM_CLOCK_CNTL_TP0				0x000000c0

#define REG_A6XX_RBBM_CLOCK_CNTL_TP1				0x000000c1

#define REG_A6XX_RBBM_CLOCK_CNTL_TP2				0x000000c2

#define REG_A6XX_RBBM_CLOCK_CNTL_TP3				0x000000c3

#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0				0x000000c4

#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1				0x000000c5

#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2				0x000000c6

#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3				0x000000c7

#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0				0x000000c8

#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1				0x000000c9

#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2				0x000000ca

#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3				0x000000cb

#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0				0x000000cc

#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1				0x000000cd

#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2				0x000000ce

#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3				0x000000cf

#define REG_A6XX_RBBM_CLOCK_DELAY_TP0				0x000000d0

#define REG_A6XX_RBBM_CLOCK_DELAY_TP1				0x000000d1

#define REG_A6XX_RBBM_CLOCK_DELAY_TP2				0x000000d2

#define REG_A6XX_RBBM_CLOCK_DELAY_TP3				0x000000d3

#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0				0x000000d4

#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1				0x000000d5

#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2				0x000000d6

#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3				0x000000d7

#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0				0x000000d8

#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1				0x000000d9

#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2				0x000000da

#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3				0x000000db

#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0				0x000000dc

#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1				0x000000dd

#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2				0x000000de

#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3				0x000000df

#define REG_A6XX_RBBM_CLOCK_HYST_TP0				0x000000e0

#define REG_A6XX_RBBM_CLOCK_HYST_TP1				0x000000e1

#define REG_A6XX_RBBM_CLOCK_HYST_TP2				0x000000e2

#define REG_A6XX_RBBM_CLOCK_HYST_TP3				0x000000e3

#define REG_A6XX_RBBM_CLOCK_HYST2_TP0				0x000000e4

#define REG_A6XX_RBBM_CLOCK_HYST2_TP1				0x000000e5

#define REG_A6XX_RBBM_CLOCK_HYST2_TP2				0x000000e6

#define REG_A6XX_RBBM_CLOCK_HYST2_TP3				0x000000e7

#define REG_A6XX_RBBM_CLOCK_HYST3_TP0				0x000000e8

#define REG_A6XX_RBBM_CLOCK_HYST3_TP1				0x000000e9

#define REG_A6XX_RBBM_CLOCK_HYST3_TP2				0x000000ea

#define REG_A6XX_RBBM_CLOCK_HYST3_TP3				0x000000eb

#define REG_A6XX_RBBM_CLOCK_HYST4_TP0				0x000000ec

#define REG_A6XX_RBBM_CLOCK_HYST4_TP1				0x000000ed

#define REG_A6XX_RBBM_CLOCK_HYST4_TP2				0x000000ee

#define REG_A6XX_RBBM_CLOCK_HYST4_TP3				0x000000ef

#define REG_A6XX_RBBM_CLOCK_CNTL_RB0				0x000000f0

#define REG_A6XX_RBBM_CLOCK_CNTL_RB1				0x000000f1

#define REG_A6XX_RBBM_CLOCK_CNTL_RB2				0x000000f2

#define REG_A6XX_RBBM_CLOCK_CNTL_RB3				0x000000f3

#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0				0x000000f4

#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1				0x000000f5

#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2				0x000000f6

#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3				0x000000f7

#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0				0x000000f8

#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1				0x000000f9

#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2				0x000000fa

#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3				0x000000fb

#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000100

#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000101

#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000102

#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000103

#define REG_A6XX_RBBM_CLOCK_CNTL_RAC				0x00000104

#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC				0x00000105

#define REG_A6XX_RBBM_CLOCK_DELAY_RAC				0x00000106

#define REG_A6XX_RBBM_CLOCK_HYST_RAC				0x00000107

#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000108

#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000109

#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000010a

#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE				0x0000010b

#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE				0x0000010c

#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE				0x0000010d

#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE				0x0000010e

#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE				0x0000010f

#define REG_A6XX_RBBM_CLOCK_HYST_UCHE				0x00000110

#define REG_A6XX_RBBM_CLOCK_MODE_VFD				0x00000111

#define REG_A6XX_RBBM_CLOCK_DELAY_VFD				0x00000112

#define REG_A6XX_RBBM_CLOCK_HYST_VFD				0x00000113

#define REG_A6XX_RBBM_CLOCK_MODE_GPC				0x00000114

#define REG_A6XX_RBBM_CLOCK_DELAY_GPC				0x00000115

#define REG_A6XX_RBBM_CLOCK_HYST_GPC				0x00000116

#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2			0x00000117

#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX				0x00000118

#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX			0x00000119

#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX				0x0000011a

#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ				0x0000011b

#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ				0x0000011c

#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ				0x0000011d

#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE			0x00000120

#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE			0x00000121

#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE			0x00000122

#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A				0x00000600

#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B				0x00000601

#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C				0x00000602

#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D				0x00000603
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK		0x000000ff
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT		0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK		0x0000ff00
#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT		8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
}

#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT				0x00000604
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK			0x00007000
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT			12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK			0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT			28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
}

#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM				0x00000605
#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK			0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT		24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
}

#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0				0x00000608

#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1				0x00000609

#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2				0x0000060a

#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3				0x0000060b

#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0			0x0000060c

#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1			0x0000060d

#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2			0x0000060e

#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3			0x0000060f

#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000610
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT		4
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT		8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT		12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT		16
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT		20
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT		24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT		28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
}

#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000611
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT		4
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT		8
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT		12
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT		16
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT		20
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT		24
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
}
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT		28
static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
{
	return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
}

#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000062f

#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000630

#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0				0x00000cd8

#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1				0x00000cd9

#define REG_A6XX_HLSQ_ADDR_MODE_CNTL				0x0000be05

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x0000be10

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x0000be11

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x0000be12

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x0000be13

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x0000be14

#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x0000be15

#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000c800

#define REG_A6XX_HLSQ_DBG_READ_SEL				0x0000d000

#define REG_A6XX_VFD_ADDR_MODE_CNTL				0x0000a601

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0				0x0000a610

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1				0x0000a611

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2				0x0000a612

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3				0x0000a613

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4				0x0000a614

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5				0x0000a615

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6				0x0000a616

#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7				0x0000a617

#define REG_A6XX_UCHE_ADDR_MODE_CNTL				0x00000e00

#define REG_A6XX_UCHE_MODE_CNTL					0x00000e01

#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO			0x00000e05

#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI			0x00000e06

#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO			0x00000e07

#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI			0x00000e08

#define REG_A6XX_UCHE_TRAP_BASE_LO				0x00000e09

#define REG_A6XX_UCHE_TRAP_BASE_HI				0x00000e0a

#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO				0x00000e0b

#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI				0x00000e0c

#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO				0x00000e0d

#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI				0x00000e0e

#define REG_A6XX_UCHE_CACHE_WAYS				0x00000e17

#define REG_A6XX_UCHE_FILTER_CNTL				0x00000e18

#define REG_A6XX_UCHE_CLIENT_PF					0x00000e19
#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK			0x000000ff
#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT			0
static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
{
	return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
}

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000e1c

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000e1d

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000e1e

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000e1f

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000e20

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000e21

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000e22

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000e23

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8			0x00000e24

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9			0x00000e25

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10			0x00000e26

#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11			0x00000e27

#define REG_A6XX_SP_ADDR_MODE_CNTL				0x0000ae01

#define REG_A6XX_SP_NC_MODE_CNTL				0x0000ae02

#define REG_A6XX_SP_PERFCTR_SP_SEL_0				0x0000ae10

#define REG_A6XX_SP_PERFCTR_SP_SEL_1				0x0000ae11

#define REG_A6XX_SP_PERFCTR_SP_SEL_2				0x0000ae12

#define REG_A6XX_SP_PERFCTR_SP_SEL_3				0x0000ae13

#define REG_A6XX_SP_PERFCTR_SP_SEL_4				0x0000ae14

#define REG_A6XX_SP_PERFCTR_SP_SEL_5				0x0000ae15

#define REG_A6XX_SP_PERFCTR_SP_SEL_6				0x0000ae16

#define REG_A6XX_SP_PERFCTR_SP_SEL_7				0x0000ae17

#define REG_A6XX_SP_PERFCTR_SP_SEL_8				0x0000ae18

#define REG_A6XX_SP_PERFCTR_SP_SEL_9				0x0000ae19

#define REG_A6XX_SP_PERFCTR_SP_SEL_10				0x0000ae1a

#define REG_A6XX_SP_PERFCTR_SP_SEL_11				0x0000ae1b

#define REG_A6XX_SP_PERFCTR_SP_SEL_12				0x0000ae1c

#define REG_A6XX_SP_PERFCTR_SP_SEL_13				0x0000ae1d

#define REG_A6XX_SP_PERFCTR_SP_SEL_14				0x0000ae1e

#define REG_A6XX_SP_PERFCTR_SP_SEL_15				0x0000ae1f

#define REG_A6XX_SP_PERFCTR_SP_SEL_16				0x0000ae20

#define REG_A6XX_SP_PERFCTR_SP_SEL_17				0x0000ae21

#define REG_A6XX_SP_PERFCTR_SP_SEL_18				0x0000ae22

#define REG_A6XX_SP_PERFCTR_SP_SEL_19				0x0000ae23

#define REG_A6XX_SP_PERFCTR_SP_SEL_20				0x0000ae24

#define REG_A6XX_SP_PERFCTR_SP_SEL_21				0x0000ae25

#define REG_A6XX_SP_PERFCTR_SP_SEL_22				0x0000ae26

#define REG_A6XX_SP_PERFCTR_SP_SEL_23				0x0000ae27

#define REG_A6XX_TPL1_ADDR_MODE_CNTL				0x0000b601

#define REG_A6XX_TPL1_NC_MODE_CNTL				0x0000b604

#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0			0x0000b608

#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1			0x0000b609

#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2			0x0000b60a

#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3			0x0000b60b

#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4			0x0000b60c

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0				0x0000b610

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1				0x0000b611

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2				0x0000b612

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3				0x0000b613

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4				0x0000b614

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5				0x0000b615

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6				0x0000b616

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7				0x0000b617

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8				0x0000b618

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9				0x0000b619

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10				0x0000b61a

#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11				0x0000b61b

#define REG_A6XX_VBIF_VERSION					0x00003000

#define REG_A6XX_VBIF_CLKON					0x00003001
#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000002

#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a

#define REG_A6XX_VBIF_XIN_HALT_CTRL0				0x00003080

#define REG_A6XX_VBIF_XIN_HALT_CTRL1				0x00003081

#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084

#define REG_A6XX_VBIF_TEST_BUS1_CTRL0				0x00003085

#define REG_A6XX_VBIF_TEST_BUS1_CTRL1				0x00003086
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK		0x0000000f
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT		0
static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
{
	return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
}

#define REG_A6XX_VBIF_TEST_BUS2_CTRL0				0x00003087

#define REG_A6XX_VBIF_TEST_BUS2_CTRL1				0x00003088
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK		0x000001ff
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT		0
static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
{
	return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
}

#define REG_A6XX_VBIF_TEST_BUS_OUT				0x0000308c

#define REG_A6XX_VBIF_PERF_CNT_SEL0				0x000030d0

#define REG_A6XX_VBIF_PERF_CNT_SEL1				0x000030d1

#define REG_A6XX_VBIF_PERF_CNT_SEL2				0x000030d2

#define REG_A6XX_VBIF_PERF_CNT_SEL3				0x000030d3

#define REG_A6XX_VBIF_PERF_CNT_LOW0				0x000030d8

#define REG_A6XX_VBIF_PERF_CNT_LOW1				0x000030d9

#define REG_A6XX_VBIF_PERF_CNT_LOW2				0x000030da

#define REG_A6XX_VBIF_PERF_CNT_LOW3				0x000030db

#define REG_A6XX_VBIF_PERF_CNT_HIGH0				0x000030e0

#define REG_A6XX_VBIF_PERF_CNT_HIGH1				0x000030e1

#define REG_A6XX_VBIF_PERF_CNT_HIGH2				0x000030e2

#define REG_A6XX_VBIF_PERF_CNT_HIGH3				0x000030e3

#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0				0x00003100

#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1				0x00003101

#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2				0x00003102

#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110

#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111

#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112

#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118

#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119

#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a

#define REG_A6XX_GBIF_SCACHE_CNTL1				0x00003c02

#define REG_A6XX_GBIF_QSB_SIDE0					0x00003c03

#define REG_A6XX_GBIF_QSB_SIDE1					0x00003c04

#define REG_A6XX_GBIF_QSB_SIDE2					0x00003c05

#define REG_A6XX_GBIF_QSB_SIDE3					0x00003c06

#define REG_A6XX_GBIF_HALT					0x00003c45

#define REG_A6XX_GBIF_HALT_ACK					0x00003c46

#define REG_A6XX_GBIF_PERF_PWR_CNT_EN				0x00003cc0

#define REG_A6XX_GBIF_PERF_CNT_SEL				0x00003cc2

#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL				0x00003cc3

#define REG_A6XX_GBIF_PERF_CNT_LOW0				0x00003cc4

#define REG_A6XX_GBIF_PERF_CNT_LOW1				0x00003cc5

#define REG_A6XX_GBIF_PERF_CNT_LOW2				0x00003cc6

#define REG_A6XX_GBIF_PERF_CNT_LOW3				0x00003cc7

#define REG_A6XX_GBIF_PERF_CNT_HIGH0				0x00003cc8

#define REG_A6XX_GBIF_PERF_CNT_HIGH1				0x00003cc9

#define REG_A6XX_GBIF_PERF_CNT_HIGH2				0x00003cca

#define REG_A6XX_GBIF_PERF_CNT_HIGH3				0x00003ccb

#define REG_A6XX_GBIF_PWR_CNT_LOW0				0x00003ccc

#define REG_A6XX_GBIF_PWR_CNT_LOW1				0x00003ccd

#define REG_A6XX_GBIF_PWR_CNT_LOW2				0x00003cce

#define REG_A6XX_GBIF_PWR_CNT_HIGH0				0x00003ccf

#define REG_A6XX_GBIF_PWR_CNT_HIGH1				0x00003cd0

#define REG_A6XX_GBIF_PWR_CNT_HIGH2				0x00003cd1

#define REG_A6XX_SP_WINDOW_OFFSET				0x0000b4d1
#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
#define A6XX_SP_WINDOW_OFFSET_X__MASK				0x00007fff
#define A6XX_SP_WINDOW_OFFSET_X__SHIFT				0
static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
{
	return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
}
#define A6XX_SP_WINDOW_OFFSET_Y__MASK				0x7fff0000
#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT				16
static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
{
	return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
}

#define REG_A6XX_SP_TP_WINDOW_OFFSET				0x0000b307
#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK			0x00007fff
#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT			0
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
{
	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
}
#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK			0x7fff0000
#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT			16
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
{
	return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
}

#define REG_A6XX_VSC_BIN_SIZE					0x00000c02
#define A6XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
	return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001ff00
#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT				8
static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
	return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
}

#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO			0x00000c03

#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI			0x00000c04

#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS			0x00000c03

#define REG_A6XX_VSC_BIN_COUNT					0x00000c06
#define A6XX_VSC_BIN_COUNT_NX__MASK				0x000007fe
#define A6XX_VSC_BIN_COUNT_NX__SHIFT				1
static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
{
	return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
}
#define A6XX_VSC_BIN_COUNT_NY__MASK				0x001ff800
#define A6XX_VSC_BIN_COUNT_NY__SHIFT				11
static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
{
	return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
}

static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
{
	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT			10
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
{
	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK			0x03f00000
#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT			20
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
{
	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
}
#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK			0xfc000000
#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT			26
static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
{
	return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
}

#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO			0x00000c30

#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI			0x00000c31

#define REG_A6XX_VSC_PRIM_STRM_ADDRESS				0x00000c30

#define REG_A6XX_VSC_PRIM_STRM_PITCH				0x00000c32

#define REG_A6XX_VSC_PRIM_STRM_LIMIT				0x00000c33

#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO			0x00000c34

#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI			0x00000c35

#define REG_A6XX_VSC_DRAW_STRM_ADDRESS				0x00000c34

#define REG_A6XX_VSC_DRAW_STRM_PITCH				0x00000c36

#define REG_A6XX_VSC_DRAW_STRM_LIMIT				0x00000c37

static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }

static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }

#define REG_A6XX_UCHE_UNKNOWN_0E12				0x00000e12

#define REG_A6XX_GRAS_CL_CNTL					0x00008000
#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE				0x00000001
#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE			0x00000002
#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE			0x00000004
#define A6XX_GRAS_CL_CNTL_UNK5					0x00000020
#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE			0x00000080
#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE			0x00000100
#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE		0x00000200

#define REG_A6XX_GRAS_VS_CL_CNTL				0x00008001
#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT			8
static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
}

#define REG_A6XX_GRAS_DS_CL_CNTL				0x00008002
#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT			8
static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
}

#define REG_A6XX_GRAS_GS_CL_CNTL				0x00008003
#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
}
#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT			8
static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
}

#define REG_A6XX_GRAS_MAX_LAYER_INDEX				0x00008004

#define REG_A6XX_GRAS_CNTL					0x00008005
#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
#define A6XX_GRAS_CNTL_SIZE					0x00000008
#define A6XX_GRAS_CNTL_UNK4					0x00000010
#define A6XX_GRAS_CNTL_SIZE_PERSAMP				0x00000020
#define A6XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT			6
static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
}

#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x00008006
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000001ff
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
{
	return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
}
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x0007fc00
#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT		10
static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
{
	return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }

static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK				0xffffffff
#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT				0
static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
}

static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK				0xffffffff
#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT				0
static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
{
	return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
}

#define REG_A6XX_GRAS_SU_CNTL					0x00008090
#define A6XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
#define A6XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
#define A6XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT			3
static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
{
	return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
}
#define A6XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
#define A6XX_GRAS_SU_CNTL_UNK12__MASK				0x00001000
#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT				12
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
{
	return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
}
#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE				0x00002000
#define A6XX_GRAS_SU_CNTL_UNK15__MASK				0x007f8000
#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT				15
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
{
	return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
}

#define REG_A6XX_GRAS_SU_POINT_MINMAX				0x00008091
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
{
	return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
}
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT			16
static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
{
	return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
}

#define REG_A6XX_GRAS_SU_POINT_SIZE				0x00008092
#define A6XX_GRAS_SU_POINT_SIZE__MASK				0x0000ffff
#define A6XX_GRAS_SU_POINT_SIZE__SHIFT				0
static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
{
	return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
}

#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK		0x00000003
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT		0
static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
{
	return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
}

#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
{
	return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
}

#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00008096
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
{
	return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
}

#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x00008097
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
{
	return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
}

#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO			0x00008098
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
{
	return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
}
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK		0x00000008
#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT		3
static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
{
	return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
}

#define REG_A6XX_GRAS_UNKNOWN_8099				0x00008099

#define REG_A6XX_GRAS_UNKNOWN_809A				0x0000809a

#define REG_A6XX_GRAS_VS_LAYER_CNTL				0x0000809b
#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER			0x00000001
#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW			0x00000002

#define REG_A6XX_GRAS_GS_LAYER_CNTL				0x0000809c
#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER			0x00000001
#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW			0x00000002

#define REG_A6XX_GRAS_DS_LAYER_CNTL				0x0000809d
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER			0x00000001
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW			0x00000002

#define REG_A6XX_GRAS_UNKNOWN_80A0				0x000080a0

#define REG_A6XX_GRAS_BIN_CONTROL				0x000080a1
#define A6XX_GRAS_BIN_CONTROL_BINW__MASK			0x0000003f
#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT			0
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
{
	return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINH__MASK			0x00007f00
#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT			8
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
{
	return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS			0x00040000
#define A6XX_GRAS_BIN_CONTROL_UNK19__MASK			0x00080000
#define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT			19
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
{
	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_UNK20__MASK			0x00100000
#define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT			20
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
{
	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_USE_VIZ				0x00200000
#define A6XX_GRAS_BIN_CONTROL_UNK22__MASK			0x0fc00000
#define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT			22
static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
{
	return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
}

#define REG_A6XX_GRAS_RAS_MSAA_CNTL				0x000080a2
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT			2
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
{
	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
}
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT			3
static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
{
	return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
}

#define REG_A6XX_GRAS_DEST_MSAA_CNTL				0x000080a3
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004

#define REG_A6XX_GRAS_SAMPLE_CONFIG				0x000080a4
#define A6XX_GRAS_SAMPLE_CONFIG_UNK0				0x00000001
#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002

#define REG_A6XX_GRAS_SAMPLE_LOCATION_0				0x000080a5
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_GRAS_SAMPLE_LOCATION_1				0x000080a6
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_GRAS_UNKNOWN_80AF				0x000080af

static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }

static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x0000ffff
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0xffff0000
#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
}

static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x0000ffff
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0xffff0000
#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
}

static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }

static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK		0x0000ffff
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT		0
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK		0xffff0000
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT		16
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
}

static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK		0x0000ffff
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT		0
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK		0xffff0000
#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT		16
static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
}

#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL			0x000080f0
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00003fff
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
}
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x3fff0000
#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
}

#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR			0x000080f1
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00003fff
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
}
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x3fff0000
#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
}

#define REG_A6XX_GRAS_LRZ_CNTL					0x00008100
#define A6XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
#define A6XX_GRAS_LRZ_CNTL_GREATER				0x00000004
#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE				0x00000008
#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE			0x00000010
#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK				0x000003e0
#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT				5
static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
{
	return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
}

#define REG_A6XX_GRAS_UNKNOWN_8101				0x00008101

#define REG_A6XX_GRAS_2D_BLIT_INFO				0x00008102
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK		0x000000ff
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT		0
static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
}

#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO			0x00008103

#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI			0x00008104

#define REG_A6XX_GRAS_LRZ_BUFFER_BASE				0x00008103
#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK				0xffffffff
#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT			0
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
}

#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH				0x00008105
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000000ff
#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT			0
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
{
	return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffffc00
#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT		10
static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
}

#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO		0x00008106

#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI		0x00008107

#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE		0x00008106
#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK		0xffffffff
#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT		0
static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
}

#define REG_A6XX_GRAS_SAMPLE_CNTL				0x00008109
#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001

#define REG_A6XX_GRAS_UNKNOWN_810A				0x0000810a
#define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK			0x000007ff
#define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT			0
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
{
	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
}
#define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK			0x07ff0000
#define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT			16
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
{
	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
}
#define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK			0xf0000000
#define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT			28
static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
{
	return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
}

#define REG_A6XX_GRAS_UNKNOWN_8110				0x00008110

#define REG_A6XX_GRAS_2D_BLIT_CNTL				0x00008400
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT			0
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK			0x00000078
#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT			3
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK		0x0000ff00
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT		8
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR				0x00010000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK			0x00060000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT			17
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_D24S8				0x00080000
#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK			0x00f00000
#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT			20
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK			0x1f000000
#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT			24
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK			0x20000000
#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT			29
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
}

#define REG_A6XX_GRAS_2D_SRC_TL_X				0x00008401

#define REG_A6XX_GRAS_2D_SRC_BR_X				0x00008402

#define REG_A6XX_GRAS_2D_SRC_TL_Y				0x00008403

#define REG_A6XX_GRAS_2D_SRC_BR_Y				0x00008404

#define REG_A6XX_GRAS_2D_DST_TL					0x00008405
#define A6XX_GRAS_2D_DST_TL_X__MASK				0x00003fff
#define A6XX_GRAS_2D_DST_TL_X__SHIFT				0
static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
}
#define A6XX_GRAS_2D_DST_TL_Y__MASK				0x3fff0000
#define A6XX_GRAS_2D_DST_TL_Y__SHIFT				16
static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
}

#define REG_A6XX_GRAS_2D_DST_BR					0x00008406
#define A6XX_GRAS_2D_DST_BR_X__MASK				0x00003fff
#define A6XX_GRAS_2D_DST_BR_X__SHIFT				0
static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
}
#define A6XX_GRAS_2D_DST_BR_Y__MASK				0x3fff0000
#define A6XX_GRAS_2D_DST_BR_Y__SHIFT				16
static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
}

#define REG_A6XX_GRAS_2D_UNKNOWN_8407				0x00008407

#define REG_A6XX_GRAS_2D_UNKNOWN_8408				0x00008408

#define REG_A6XX_GRAS_2D_UNKNOWN_8409				0x00008409

#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1				0x0000840a
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK			0x00003fff
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT			0
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
}
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK			0x3fff0000
#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
}

#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2				0x0000840b
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK			0x00003fff
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT			0
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
}
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK			0x3fff0000
#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT			16
static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
{
	return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
}

#define REG_A6XX_GRAS_UNKNOWN_8600				0x00008600

#define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601

#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0				0x00008610

#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1				0x00008611

#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2				0x00008612

#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3				0x00008613

#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0				0x00008614

#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1				0x00008615

#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2				0x00008616

#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3				0x00008617

#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0				0x00008618

#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1				0x00008619

#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2				0x0000861a

#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3				0x0000861b

#define REG_A6XX_RB_BIN_CONTROL					0x00008800
#define A6XX_RB_BIN_CONTROL_BINW__MASK				0x0000003f
#define A6XX_RB_BIN_CONTROL_BINW__SHIFT				0
static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
{
	return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINH__MASK				0x00007f00
#define A6XX_RB_BIN_CONTROL_BINH__SHIFT				8
static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
{
	return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINNING_PASS			0x00040000
#define A6XX_RB_BIN_CONTROL_UNK19__MASK				0x00080000
#define A6XX_RB_BIN_CONTROL_UNK19__SHIFT			19
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
{
	return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
}
#define A6XX_RB_BIN_CONTROL_UNK20__MASK				0x00100000
#define A6XX_RB_BIN_CONTROL_UNK20__SHIFT			20
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
{
	return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
}
#define A6XX_RB_BIN_CONTROL_USE_VIZ				0x00200000
#define A6XX_RB_BIN_CONTROL_UNK22__MASK				0x07c00000
#define A6XX_RB_BIN_CONTROL_UNK22__SHIFT			22
static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
{
	return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
}

#define REG_A6XX_RB_RENDER_CNTL					0x00008801
#define A6XX_RB_RENDER_CNTL_UNK3				0x00000008
#define A6XX_RB_RENDER_CNTL_UNK4				0x00000010
#define A6XX_RB_RENDER_CNTL_UNK5__MASK				0x00000060
#define A6XX_RB_RENDER_CNTL_UNK5__SHIFT				5
static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
}
#define A6XX_RB_RENDER_CNTL_BINNING				0x00000080
#define A6XX_RB_RENDER_CNTL_UNK8__MASK				0x00001f00
#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT				8
static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
}
#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT			16
static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
}

#define REG_A6XX_RB_RAS_MSAA_CNTL				0x00008802
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT			2
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
{
	return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
}
#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT			3
static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
{
	return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
}

#define REG_A6XX_RB_DEST_MSAA_CNTL				0x00008803
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004

#define REG_A6XX_RB_SAMPLE_CONFIG				0x00008804
#define A6XX_RB_SAMPLE_CONFIG_UNK0				0x00000001
#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002

#define REG_A6XX_RB_SAMPLE_LOCATION_0				0x00008805
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_RB_SAMPLE_LOCATION_1				0x00008806
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_RB_RENDER_CONTROL0				0x00008809
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
#define A6XX_RB_RENDER_CONTROL0_SIZE				0x00000008
#define A6XX_RB_RENDER_CONTROL0_UNK4				0x00000010
#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP			0x00000020
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT		6
static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
}
#define A6XX_RB_RENDER_CONTROL0_UNK10				0x00000400

#define REG_A6XX_RB_RENDER_CONTROL1				0x0000880a
#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
#define A6XX_RB_RENDER_CONTROL1_UNK1				0x00000002
#define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000004
#define A6XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000008
#define A6XX_RB_RENDER_CONTROL1_UNK4				0x00000010
#define A6XX_RB_RENDER_CONTROL1_UNK5				0x00000020
#define A6XX_RB_RENDER_CONTROL1_SIZE				0x00000040
#define A6XX_RB_RENDER_CONTROL1_UNK7				0x00000080
#define A6XX_RB_RENDER_CONTROL1_UNK8				0x00000100

#define REG_A6XX_RB_FS_OUTPUT_CNTL0				0x0000880b
#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z			0x00000002
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK		0x00000004
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF		0x00000008

#define REG_A6XX_RB_FS_OUTPUT_CNTL1				0x0000880c
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT			0
static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
{
	return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
}

#define REG_A6XX_RB_RENDER_COMPONENTS				0x0000880d
#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT			4
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT			8
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT			12
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT			16
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT			20
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT			24
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
}
#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT			28
static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
{
	return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
}

#define REG_A6XX_RB_DITHER_CNTL					0x0000880e
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK		0x00000003
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT		0
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK		0x0000000c
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT		2
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK		0x00000030
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT		4
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK		0x000000c0
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT		6
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK		0x00000300
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT		8
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK		0x00000c00
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT		10
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK		0x00001000
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT		12
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
}
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK		0x0000c000
#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT		14
static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
{
	return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
}

#define REG_A6XX_RB_SRGB_CNTL					0x0000880f
#define A6XX_RB_SRGB_CNTL_SRGB_MRT0				0x00000001
#define A6XX_RB_SRGB_CNTL_SRGB_MRT1				0x00000002
#define A6XX_RB_SRGB_CNTL_SRGB_MRT2				0x00000004
#define A6XX_RB_SRGB_CNTL_SRGB_MRT3				0x00000008
#define A6XX_RB_SRGB_CNTL_SRGB_MRT4				0x00000010
#define A6XX_RB_SRGB_CNTL_SRGB_MRT5				0x00000020
#define A6XX_RB_SRGB_CNTL_SRGB_MRT6				0x00000040
#define A6XX_RB_SRGB_CNTL_SRGB_MRT7				0x00000080

#define REG_A6XX_RB_SAMPLE_CNTL					0x00008810
#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001

#define REG_A6XX_RB_UNKNOWN_8811				0x00008811

#define REG_A6XX_RB_UNKNOWN_8818				0x00008818

#define REG_A6XX_RB_UNKNOWN_8819				0x00008819

#define REG_A6XX_RB_UNKNOWN_881A				0x0000881a

#define REG_A6XX_RB_UNKNOWN_881B				0x0000881b

#define REG_A6XX_RB_UNKNOWN_881C				0x0000881c

#define REG_A6XX_RB_UNKNOWN_881D				0x0000881d

#define REG_A6XX_RB_UNKNOWN_881E				0x0000881e

static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }

static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
#define A6XX_RB_MRT_CONTROL_BLEND				0x00000001
#define A6XX_RB_MRT_CONTROL_BLEND2				0x00000002
#define A6XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT			3
static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
{
	return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
}
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT		7
static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
{
	return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT	8
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT	16
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
}
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT	24
static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
}
#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT		8
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
}
#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK			0x00000400
#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT			10
static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
{
	return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
}
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT			13
static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
#define A6XX_RB_MRT_PITCH__MASK					0x0000ffff
#define A6XX_RB_MRT_PITCH__SHIFT				0
static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
#define A6XX_RB_MRT_ARRAY_PITCH__MASK				0x1fffffff
#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT				0
static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }

static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }

static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
#define A6XX_RB_MRT_BASE__MASK					0xffffffff
#define A6XX_RB_MRT_BASE__SHIFT					0
static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
{
	return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
#define A6XX_RB_MRT_BASE_GMEM__MASK				0xfffff000
#define A6XX_RB_MRT_BASE_GMEM__SHIFT				12
static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
{
	return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
}

#define REG_A6XX_RB_BLEND_RED_F32				0x00008860
#define A6XX_RB_BLEND_RED_F32__MASK				0xffffffff
#define A6XX_RB_BLEND_RED_F32__SHIFT				0
static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
{
	return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
}

#define REG_A6XX_RB_BLEND_GREEN_F32				0x00008861
#define A6XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
#define A6XX_RB_BLEND_GREEN_F32__SHIFT				0
static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
{
	return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
}

#define REG_A6XX_RB_BLEND_BLUE_F32				0x00008862
#define A6XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
#define A6XX_RB_BLEND_BLUE_F32__SHIFT				0
static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
{
	return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
}

#define REG_A6XX_RB_BLEND_ALPHA_F32				0x00008863
#define A6XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
#define A6XX_RB_BLEND_ALPHA_F32__SHIFT				0
static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
{
	return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
}

#define REG_A6XX_RB_ALPHA_CONTROL				0x00008864
#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
{
	return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
}
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT		9
static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
{
	return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
}

#define REG_A6XX_RB_BLEND_CNTL					0x00008865
#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
{
	return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
}
#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE				0x00000800
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT			16
static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
{
	return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
}

#define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK			0x00000003
#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT			0
static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
{
	return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
}

#define REG_A6XX_RB_DEPTH_CNTL					0x00008871
#define A6XX_RB_DEPTH_CNTL_Z_ENABLE				0x00000001
#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT				2
static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
{
	return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
}
#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE			0x00000020
#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000040
#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE			0x00000080

#define REG_A6XX_RB_DEPTH_BUFFER_INFO				0x00008872
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
{
	return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
}
#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK			0x00000018
#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT			3
static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
{
	return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
}

#define REG_A6XX_RB_DEPTH_BUFFER_PITCH				0x00008873
#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0x00003fff
#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
}

#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x00008874
#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0x0fffffff
#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO			0x00008875

#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI			0x00008876

#define REG_A6XX_RB_DEPTH_BUFFER_BASE				0x00008875
#define A6XX_RB_DEPTH_BUFFER_BASE__MASK				0xffffffff
#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT			0
static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
}

#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM			0x00008877
#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK			0xfffff000
#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT			12
static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
{
	return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
}

#define REG_A6XX_RB_Z_BOUNDS_MIN				0x00008878
#define A6XX_RB_Z_BOUNDS_MIN__MASK				0xffffffff
#define A6XX_RB_Z_BOUNDS_MIN__SHIFT				0
static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
{
	return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
}

#define REG_A6XX_RB_Z_BOUNDS_MAX				0x00008879
#define A6XX_RB_Z_BOUNDS_MAX__MASK				0xffffffff
#define A6XX_RB_Z_BOUNDS_MAX__SHIFT				0
static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
{
	return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
}

#define REG_A6XX_RB_STENCIL_CONTROL				0x00008880
#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT			8
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT			11
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT			14
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT			17
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT			20
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT			23
static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT			26
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
}
#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT			29
static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
}

#define REG_A6XX_RB_STENCIL_INFO				0x00008881
#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
#define A6XX_RB_STENCIL_INFO_UNK1				0x00000002

#define REG_A6XX_RB_STENCIL_BUFFER_PITCH			0x00008882
#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0x00000fff
#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
}

#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH			0x00008883
#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0x00ffffff
#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT		0
static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO			0x00008884

#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI			0x00008885

#define REG_A6XX_RB_STENCIL_BUFFER_BASE				0x00008884
#define A6XX_RB_STENCIL_BUFFER_BASE__MASK			0xffffffff
#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT			0
static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
}

#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM			0x00008886
#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK			0xfffff000
#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT			12
static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
{
	return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
}

#define REG_A6XX_RB_STENCILREF					0x00008887
#define A6XX_RB_STENCILREF_REF__MASK				0x000000ff
#define A6XX_RB_STENCILREF_REF__SHIFT				0
static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
}
#define A6XX_RB_STENCILREF_BFREF__MASK				0x0000ff00
#define A6XX_RB_STENCILREF_BFREF__SHIFT				8
static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
}

#define REG_A6XX_RB_STENCILMASK					0x00008888
#define A6XX_RB_STENCILMASK_MASK__MASK				0x000000ff
#define A6XX_RB_STENCILMASK_MASK__SHIFT				0
static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
}
#define A6XX_RB_STENCILMASK_BFMASK__MASK			0x0000ff00
#define A6XX_RB_STENCILMASK_BFMASK__SHIFT			8
static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
}

#define REG_A6XX_RB_STENCILWRMASK				0x00008889
#define A6XX_RB_STENCILWRMASK_WRMASK__MASK			0x000000ff
#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT			0
static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
}
#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK			0x0000ff00
#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT			8
static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
{
	return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
}

#define REG_A6XX_RB_WINDOW_OFFSET				0x00008890
#define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00003fff
#define A6XX_RB_WINDOW_OFFSET_X__SHIFT				0
static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
{
	return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
}
#define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x3fff0000
#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT				16
static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
{
	return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
}

#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL			0x00008891
#define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0			0x00000001
#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002

#define REG_A6XX_RB_LRZ_CNTL					0x00008898
#define A6XX_RB_LRZ_CNTL_ENABLE					0x00000001

#define REG_A6XX_RB_Z_CLAMP_MIN					0x000088c0
#define A6XX_RB_Z_CLAMP_MIN__MASK				0xffffffff
#define A6XX_RB_Z_CLAMP_MIN__SHIFT				0
static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
{
	return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
}

#define REG_A6XX_RB_Z_CLAMP_MAX					0x000088c1
#define A6XX_RB_Z_CLAMP_MAX__MASK				0xffffffff
#define A6XX_RB_Z_CLAMP_MAX__SHIFT				0
static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
{
	return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
}

#define REG_A6XX_RB_UNKNOWN_88D0				0x000088d0
#define A6XX_RB_UNKNOWN_88D0_UNK0__MASK				0x00001fff
#define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT			0
static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
{
	return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
}
#define A6XX_RB_UNKNOWN_88D0_UNK16__MASK			0x07ff0000
#define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT			16
static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
{
	return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
}

#define REG_A6XX_RB_BLIT_SCISSOR_TL				0x000088d1
#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00003fff
#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
}
#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x3fff0000
#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
}

#define REG_A6XX_RB_BLIT_SCISSOR_BR				0x000088d2
#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00003fff
#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
}
#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x3fff0000
#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
}

#define REG_A6XX_RB_BIN_CONTROL2				0x000088d3
#define A6XX_RB_BIN_CONTROL2_BINW__MASK				0x0000003f
#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT			0
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
{
	return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL2_BINH__MASK				0x00007f00
#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT			8
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
{
	return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
}

#define REG_A6XX_RB_WINDOW_OFFSET2				0x000088d4
#define A6XX_RB_WINDOW_OFFSET2_X__MASK				0x00003fff
#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT				0
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
{
	return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
}
#define A6XX_RB_WINDOW_OFFSET2_Y__MASK				0x3fff0000
#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT				16
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
{
	return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
}

#define REG_A6XX_RB_MSAA_CNTL					0x000088d5
#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK				0x00000018
#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT			3
static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
}

#define REG_A6XX_RB_BLIT_BASE_GMEM				0x000088d6
#define A6XX_RB_BLIT_BASE_GMEM__MASK				0xfffff000
#define A6XX_RB_BLIT_BASE_GMEM__SHIFT				12
static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
{
	return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
}

#define REG_A6XX_RB_BLIT_DST_INFO				0x000088d7
#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK			0x00000003
#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT			0
static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
}
#define A6XX_RB_BLIT_DST_INFO_FLAGS				0x00000004
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK			0x00000018
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT			3
static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
}
#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK			0x00000060
#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT			5
static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
}
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT		7
static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
}
#define A6XX_RB_BLIT_DST_INFO_UNK15				0x00008000

#define REG_A6XX_RB_BLIT_DST					0x000088d8
#define A6XX_RB_BLIT_DST__MASK					0xffffffff
#define A6XX_RB_BLIT_DST__SHIFT					0
static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
}

#define REG_A6XX_RB_BLIT_DST_LO					0x000088d8

#define REG_A6XX_RB_BLIT_DST_HI					0x000088d9

#define REG_A6XX_RB_BLIT_DST_PITCH				0x000088da
#define A6XX_RB_BLIT_DST_PITCH__MASK				0x0000ffff
#define A6XX_RB_BLIT_DST_PITCH__SHIFT				0
static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
}

#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH			0x000088db
#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0x1fffffff
#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_BLIT_FLAG_DST				0x000088dc
#define A6XX_RB_BLIT_FLAG_DST__MASK				0xffffffff
#define A6XX_RB_BLIT_FLAG_DST__SHIFT				0
static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
}

#define REG_A6XX_RB_BLIT_FLAG_DST_LO				0x000088dc

#define REG_A6XX_RB_BLIT_FLAG_DST_HI				0x000088dd

#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH				0x000088de
#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK			0x000007ff
#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT		0
static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
}
#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK		0x0ffff800
#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT		11
static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0			0x000088df

#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1			0x000088e0

#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2			0x000088e1

#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3			0x000088e2

#define REG_A6XX_RB_BLIT_INFO					0x000088e3
#define A6XX_RB_BLIT_INFO_UNK0					0x00000001
#define A6XX_RB_BLIT_INFO_GMEM					0x00000002
#define A6XX_RB_BLIT_INFO_INTEGER				0x00000004
#define A6XX_RB_BLIT_INFO_DEPTH					0x00000008
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK			0x000000f0
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT			4
static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
}
#define A6XX_RB_BLIT_INFO_UNK8__MASK				0x00000300
#define A6XX_RB_BLIT_INFO_UNK8__SHIFT				8
static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
}
#define A6XX_RB_BLIT_INFO_UNK12__MASK				0x0000f000
#define A6XX_RB_BLIT_INFO_UNK12__SHIFT				12
static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
{
	return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
}

#define REG_A6XX_RB_UNKNOWN_88F0				0x000088f0

#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE			0x000088f1
#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK			0xffffffff
#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT			0
static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
}

#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH			0x000088f3
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x00fff800
#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_UNKNOWN_88F4				0x000088f4

#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO			0x00008900

#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI			0x00008901

#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE			0x00008900
#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK			0xffffffff
#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT			0
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
}

#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x00008902
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK		0x0000007f
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK		0x00000700
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT		8
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
{
	return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
}
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK	0x0ffff800
#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }

static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }

static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }

static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK			0xffffffff
#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT			0
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
{
	return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
}

static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
}
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffff800
#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT	11
static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
}

#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO			0x00008927

#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI			0x00008928

#define REG_A6XX_RB_SAMPLE_COUNT_ADDR				0x00008927
#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK				0xffffffff
#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT			0
static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
{
	return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
}

#define REG_A6XX_RB_2D_BLIT_CNTL				0x00008c00
#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT			0
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK				0x00000078
#define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT			3
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK			0x0000ff00
#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT		8
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_SCISSOR				0x00010000
#define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK			0x00060000
#define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT			17
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_D24S8				0x00080000
#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK				0x00f00000
#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT			20
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK				0x1f000000
#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT			24
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK			0x20000000
#define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT			29
static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)
{
	return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK;
}

#define REG_A6XX_RB_2D_UNKNOWN_8C01				0x00008c01

#define REG_A6XX_RB_2D_DST_INFO					0x00008c17
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
}
#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT			8
static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
}
#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT			10
static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
}
#define A6XX_RB_2D_DST_INFO_FLAGS				0x00001000
#define A6XX_RB_2D_DST_INFO_SRGB				0x00002000
#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK			0x0000c000
#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT			14
static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
}
#define A6XX_RB_2D_DST_INFO_FILTER				0x00010000
#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE			0x00040000
#define A6XX_RB_2D_DST_INFO_UNK20				0x00100000
#define A6XX_RB_2D_DST_INFO_UNK22				0x00400000

#define REG_A6XX_RB_2D_DST_LO					0x00008c18

#define REG_A6XX_RB_2D_DST_HI					0x00008c19

#define REG_A6XX_RB_2D_DST					0x00008c18
#define A6XX_RB_2D_DST__MASK					0xffffffff
#define A6XX_RB_2D_DST__SHIFT					0
static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
{
	return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
}

#define REG_A6XX_RB_2D_DST_PITCH				0x00008c1a
#define A6XX_RB_2D_DST_PITCH__MASK				0x0000ffff
#define A6XX_RB_2D_DST_PITCH__SHIFT				0
static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
}

#define REG_A6XX_RB_2D_DST_PLANE1				0x00008c1b
#define A6XX_RB_2D_DST_PLANE1__MASK				0xffffffff
#define A6XX_RB_2D_DST_PLANE1__SHIFT				0
static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
{
	return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
}

#define REG_A6XX_RB_2D_DST_PLANE_PITCH				0x00008c1d
#define A6XX_RB_2D_DST_PLANE_PITCH__MASK			0x0000ffff
#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
}

#define REG_A6XX_RB_2D_DST_PLANE2				0x00008c1e
#define A6XX_RB_2D_DST_PLANE2__MASK				0xffffffff
#define A6XX_RB_2D_DST_PLANE2__SHIFT				0
static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
{
	return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
}

#define REG_A6XX_RB_2D_DST_FLAGS_LO				0x00008c20

#define REG_A6XX_RB_2D_DST_FLAGS_HI				0x00008c21

#define REG_A6XX_RB_2D_DST_FLAGS				0x00008c20
#define A6XX_RB_2D_DST_FLAGS__MASK				0xffffffff
#define A6XX_RB_2D_DST_FLAGS__SHIFT				0
static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
{
	return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
}

#define REG_A6XX_RB_2D_DST_FLAGS_PITCH				0x00008c22
#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK			0x000000ff
#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
}

#define REG_A6XX_RB_2D_DST_FLAGS_PLANE				0x00008c23
#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK			0xffffffff
#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT			0
static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
{
	return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
}

#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH			0x00008c25
#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK			0x000000ff
#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT			0
static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
}

#define REG_A6XX_RB_2D_SRC_SOLID_C0				0x00008c2c

#define REG_A6XX_RB_2D_SRC_SOLID_C1				0x00008c2d

#define REG_A6XX_RB_2D_SRC_SOLID_C2				0x00008c2e

#define REG_A6XX_RB_2D_SRC_SOLID_C3				0x00008c2f

#define REG_A6XX_RB_UNKNOWN_8E01				0x00008e01

#define REG_A6XX_RB_UNKNOWN_8E04				0x00008e04

#define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05

#define REG_A6XX_RB_CCU_CNTL					0x00008e07
#define A6XX_RB_CCU_CNTL_OFFSET__MASK				0xff800000
#define A6XX_RB_CCU_CNTL_OFFSET__SHIFT				23
static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
{
	return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
}
#define A6XX_RB_CCU_CNTL_GMEM					0x00400000
#define A6XX_RB_CCU_CNTL_UNK2					0x00000004

#define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
#define A6XX_RB_NC_MODE_CNTL_MODE				0x00000001
#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT			1
static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
{
	return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
}
#define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH			0x00000008
#define A6XX_RB_NC_MODE_CNTL_AMSBC				0x00000010
#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000400
#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT			10
static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
{
	return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
}
#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR			0x00000800
#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK			0x00003000
#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT			12
static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
{
	return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
}

#define REG_A6XX_RB_PERFCTR_RB_SEL_0				0x00008e10

#define REG_A6XX_RB_PERFCTR_RB_SEL_1				0x00008e11

#define REG_A6XX_RB_PERFCTR_RB_SEL_2				0x00008e12

#define REG_A6XX_RB_PERFCTR_RB_SEL_3				0x00008e13

#define REG_A6XX_RB_PERFCTR_RB_SEL_4				0x00008e14

#define REG_A6XX_RB_PERFCTR_RB_SEL_5				0x00008e15

#define REG_A6XX_RB_PERFCTR_RB_SEL_6				0x00008e16

#define REG_A6XX_RB_PERFCTR_RB_SEL_7				0x00008e17

#define REG_A6XX_RB_PERFCTR_CCU_SEL_0				0x00008e18

#define REG_A6XX_RB_PERFCTR_CCU_SEL_1				0x00008e19

#define REG_A6XX_RB_PERFCTR_CCU_SEL_2				0x00008e1a

#define REG_A6XX_RB_PERFCTR_CCU_SEL_3				0x00008e1b

#define REG_A6XX_RB_PERFCTR_CCU_SEL_4				0x00008e1c

#define REG_A6XX_RB_UNKNOWN_8E28				0x00008e28

#define REG_A6XX_RB_PERFCTR_CMP_SEL_0				0x00008e2c

#define REG_A6XX_RB_PERFCTR_CMP_SEL_1				0x00008e2d

#define REG_A6XX_RB_PERFCTR_CMP_SEL_2				0x00008e2e

#define REG_A6XX_RB_PERFCTR_CMP_SEL_3				0x00008e2f

#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST			0x00008e3b

#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d

#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50

#define REG_A6XX_RB_UNKNOWN_8E51				0x00008e51
#define A6XX_RB_UNKNOWN_8E51__MASK				0xffffffff
#define A6XX_RB_UNKNOWN_8E51__SHIFT				0
static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
{
	return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
}

#define REG_A6XX_VPC_UNKNOWN_9100				0x00009100

#define REG_A6XX_VPC_VS_CLIP_CNTL				0x00009101
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
}
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
}
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
}

#define REG_A6XX_VPC_GS_CLIP_CNTL				0x00009102
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
}
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
}
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
}

#define REG_A6XX_VPC_DS_CLIP_CNTL				0x00009103
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT			0
static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
}
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT		8
static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
}
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT		16
static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
}

#define REG_A6XX_VPC_VS_LAYER_CNTL				0x00009104
#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT			0
static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
}
#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT			8
static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
}

#define REG_A6XX_VPC_GS_LAYER_CNTL				0x00009105
#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT			0
static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
}
#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT			8
static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
}

#define REG_A6XX_VPC_DS_LAYER_CNTL				0x00009106
#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT			0
static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
}
#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT			8
static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
}

#define REG_A6XX_VPC_UNKNOWN_9107				0x00009107

#define REG_A6XX_VPC_POLYGON_MODE				0x00009108
#define A6XX_VPC_POLYGON_MODE_MODE__MASK			0x00000003
#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT			0
static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
{
	return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
}

static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }

static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }

static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }

static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }

#define REG_A6XX_VPC_UNKNOWN_9210				0x00009210

#define REG_A6XX_VPC_UNKNOWN_9211				0x00009211

static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }

static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }

#define REG_A6XX_VPC_SO_CNTL					0x00009216
#define A6XX_VPC_SO_CNTL_UNK0__MASK				0x000000ff
#define A6XX_VPC_SO_CNTL_UNK0__SHIFT				0
static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
}
#define A6XX_VPC_SO_CNTL_ENABLE					0x00010000

#define REG_A6XX_VPC_SO_PROG					0x00009217
#define A6XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
#define A6XX_VPC_SO_PROG_A_BUF__SHIFT				0
static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
}
#define A6XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
#define A6XX_VPC_SO_PROG_A_OFF__SHIFT				2
static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
{
	return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
}
#define A6XX_VPC_SO_PROG_A_EN					0x00000800
#define A6XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
#define A6XX_VPC_SO_PROG_B_BUF__SHIFT				12
static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
}
#define A6XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
#define A6XX_VPC_SO_PROG_B_OFF__SHIFT				14
static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
{
	return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
}
#define A6XX_VPC_SO_PROG_B_EN					0x00800000

#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO			0x00009218

#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI			0x00009219

#define REG_A6XX_VPC_SO_STREAM_COUNTS				0x00009218
#define A6XX_VPC_SO_STREAM_COUNTS__MASK				0xffffffff
#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT			0
static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
}

static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }

static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
#define A6XX_VPC_SO_BUFFER_BASE__MASK				0xffffffff
#define A6XX_VPC_SO_BUFFER_BASE__SHIFT				0
static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
}

static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }

static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }

static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
#define A6XX_VPC_SO_BUFFER_SIZE__MASK				0xfffffffc
#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT				2
static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
{
	return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
}

static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }

static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
#define A6XX_VPC_SO_BUFFER_OFFSET__MASK				0xfffffffc
#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT			2
static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
{
	return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
}

static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
#define A6XX_VPC_SO_FLUSH_BASE__MASK				0xffffffff
#define A6XX_VPC_SO_FLUSH_BASE__SHIFT				0
static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
}

static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }

static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }

#define REG_A6XX_VPC_POINT_COORD_INVERT				0x00009236
#define A6XX_VPC_POINT_COORD_INVERT_INVERT			0x00000001

#define REG_A6XX_VPC_UNKNOWN_9300				0x00009300

#define REG_A6XX_VPC_VS_PACK					0x00009301
#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT			0
static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
}
#define A6XX_VPC_VS_PACK_POSITIONLOC__MASK			0x0000ff00
#define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT			8
static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
}
#define A6XX_VPC_VS_PACK_PSIZELOC__MASK				0x00ff0000
#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT			16
static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
}
#define A6XX_VPC_VS_PACK_UNK24__MASK				0x0f000000
#define A6XX_VPC_VS_PACK_UNK24__SHIFT				24
static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
{
	return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
}

#define REG_A6XX_VPC_GS_PACK					0x00009302
#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT			0
static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
}
#define A6XX_VPC_GS_PACK_POSITIONLOC__MASK			0x0000ff00
#define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT			8
static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
}
#define A6XX_VPC_GS_PACK_PSIZELOC__MASK				0x00ff0000
#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT			16
static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
}
#define A6XX_VPC_GS_PACK_UNK24__MASK				0x0f000000
#define A6XX_VPC_GS_PACK_UNK24__SHIFT				24
static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
{
	return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
}

#define REG_A6XX_VPC_DS_PACK					0x00009303
#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT			0
static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
}
#define A6XX_VPC_DS_PACK_POSITIONLOC__MASK			0x0000ff00
#define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT			8
static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
}
#define A6XX_VPC_DS_PACK_PSIZELOC__MASK				0x00ff0000
#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT			16
static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
}
#define A6XX_VPC_DS_PACK_UNK24__MASK				0x0f000000
#define A6XX_VPC_DS_PACK_UNK24__SHIFT				24
static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
{
	return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
}

#define REG_A6XX_VPC_CNTL_0					0x00009304
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK			0x000000ff
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT			0
static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
{
	return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
}
#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK				0x0000ff00
#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT			8
static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
}
#define A6XX_VPC_CNTL_0_VARYING					0x00010000
#define A6XX_VPC_CNTL_0_UNKLOC__MASK				0xff000000
#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT				24
static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
{
	return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
}

#define REG_A6XX_VPC_SO_BUF_CNTL				0x00009305
#define A6XX_VPC_SO_BUF_CNTL_BUF0				0x00000001
#define A6XX_VPC_SO_BUF_CNTL_BUF1				0x00000008
#define A6XX_VPC_SO_BUF_CNTL_BUF2				0x00000040
#define A6XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
#define A6XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK			0x000f0000
#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT			16
static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
{
	return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
}

#define REG_A6XX_VPC_SO_DISABLE					0x00009306
#define A6XX_VPC_SO_DISABLE_DISABLE				0x00000001

#define REG_A6XX_VPC_UNKNOWN_9600				0x00009600

#define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601

#define REG_A6XX_VPC_UNKNOWN_9602				0x00009602

#define REG_A6XX_VPC_UNKNOWN_9603				0x00009603

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0				0x00009604

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1				0x00009605

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2				0x00009606

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3				0x00009607

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4				0x00009608

#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5				0x00009609

#define REG_A6XX_PC_TESS_NUM_VERTEX				0x00009800

#define REG_A6XX_PC_UNKNOWN_9801				0x00009801
#define A6XX_PC_UNKNOWN_9801_UNK0__MASK				0x000007ff
#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT			0
static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
{
	return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
}
#define A6XX_PC_UNKNOWN_9801_UNK13__MASK			0x00002000
#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT			13
static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
{
	return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
}

#define REG_A6XX_PC_TESS_CNTL					0x00009802
#define A6XX_PC_TESS_CNTL_SPACING__MASK				0x00000003
#define A6XX_PC_TESS_CNTL_SPACING__SHIFT			0
static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
{
	return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
}
#define A6XX_PC_TESS_CNTL_OUTPUT__MASK				0x0000000c
#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT				2
static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
{
	return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
}

#define REG_A6XX_PC_RESTART_INDEX				0x00009803

#define REG_A6XX_PC_MODE_CNTL					0x00009804

#define REG_A6XX_PC_UNKNOWN_9805				0x00009805

#define REG_A6XX_PC_PRIMID_PASSTHRU				0x00009806

#define REG_A6XX_PC_DRAW_CMD					0x00009840
#define A6XX_PC_DRAW_CMD_STATE_ID__MASK				0x000000ff
#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT			0
static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
}

#define REG_A6XX_PC_DISPATCH_CMD				0x00009841
#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT			0
static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
}

#define REG_A6XX_PC_EVENT_CMD					0x00009842
#define A6XX_PC_EVENT_CMD_STATE_ID__MASK			0x00ff0000
#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT			16
static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
}
#define A6XX_PC_EVENT_CMD_EVENT__MASK				0x0000007f
#define A6XX_PC_EVENT_CMD_EVENT__SHIFT				0
static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
{
	return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
}

#define REG_A6XX_PC_POLYGON_MODE				0x00009981
#define A6XX_PC_POLYGON_MODE_MODE__MASK				0x00000003
#define A6XX_PC_POLYGON_MODE_MODE__SHIFT			0
static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
{
	return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
}

#define REG_A6XX_PC_UNKNOWN_9980				0x00009980

#define REG_A6XX_PC_PRIMITIVE_CNTL_0				0x00009b00
#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART		0x00000001
#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST		0x00000002
#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN	0x00000004
#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3				0x00000008

#define REG_A6XX_PC_VS_OUT_CNTL					0x00009b01
#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
}
#define A6XX_PC_VS_OUT_CNTL_PSIZE				0x00000100
#define A6XX_PC_VS_OUT_CNTL_LAYER				0x00000200
#define A6XX_PC_VS_OUT_CNTL_VIEW				0x00000400
#define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID			0x00000800
#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT			16
static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
}

#define REG_A6XX_PC_GS_OUT_CNTL					0x00009b02
#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
}
#define A6XX_PC_GS_OUT_CNTL_PSIZE				0x00000100
#define A6XX_PC_GS_OUT_CNTL_LAYER				0x00000200
#define A6XX_PC_GS_OUT_CNTL_VIEW				0x00000400
#define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID			0x00000800
#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT			16
static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
}

#define REG_A6XX_PC_PRIMITIVE_CNTL_3				0x00009b03

#define REG_A6XX_PC_DS_OUT_CNTL					0x00009b04
#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
}
#define A6XX_PC_DS_OUT_CNTL_PSIZE				0x00000100
#define A6XX_PC_DS_OUT_CNTL_LAYER				0x00000200
#define A6XX_PC_DS_OUT_CNTL_VIEW				0x00000400
#define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID			0x00000800
#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT			16
static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
{
	return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
}

#define REG_A6XX_PC_PRIMITIVE_CNTL_5				0x00009b05
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK		0x000000ff
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT		0
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
{
	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
}
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK		0x00007c00
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT		10
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
{
	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
}
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK		0x00030000
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT		16
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
{
	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
}
#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK			0x00040000
#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT			18
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
{
	return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
}

#define REG_A6XX_PC_PRIMITIVE_CNTL_6				0x00009b06
#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK		0x000007ff
#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT		0
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
}

#define REG_A6XX_PC_UNKNOWN_9B07				0x00009b07

#define REG_A6XX_PC_UNKNOWN_9B08				0x00009b08

#define REG_A6XX_PC_2D_EVENT_CMD				0x00009c00
#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK			0x0000007f
#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT			0
static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
{
	return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
}
#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT			8
static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
}

#define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00

#define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01

#define REG_A6XX_PC_TESSFACTOR_ADDR_LO				0x00009e08

#define REG_A6XX_PC_TESSFACTOR_ADDR_HI				0x00009e09

#define REG_A6XX_PC_TESSFACTOR_ADDR				0x00009e08
#define A6XX_PC_TESSFACTOR_ADDR__MASK				0xffffffff
#define A6XX_PC_TESSFACTOR_ADDR__SHIFT				0
static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
{
	return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
}

#define REG_A6XX_PC_VSTREAM_CONTROL				0x00009e11
#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK			0x0000ffff
#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT			0
static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
{
	return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
}
#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK			0x003f0000
#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT			16
static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
{
	return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
}
#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK			0x07c00000
#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT			22
static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
{
	return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
}

#define REG_A6XX_PC_BIN_PRIM_STRM				0x00009e12
#define A6XX_PC_BIN_PRIM_STRM__MASK				0xffffffff
#define A6XX_PC_BIN_PRIM_STRM__SHIFT				0
static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
{
	return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
}

#define REG_A6XX_PC_BIN_DRAW_STRM				0x00009e14
#define A6XX_PC_BIN_DRAW_STRM__MASK				0xffffffff
#define A6XX_PC_BIN_DRAW_STRM__SHIFT				0
static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
{
	return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
}

#define REG_A6XX_PC_PERFCTR_PC_SEL_0				0x00009e34

#define REG_A6XX_PC_PERFCTR_PC_SEL_1				0x00009e35

#define REG_A6XX_PC_PERFCTR_PC_SEL_2				0x00009e36

#define REG_A6XX_PC_PERFCTR_PC_SEL_3				0x00009e37

#define REG_A6XX_PC_PERFCTR_PC_SEL_4				0x00009e38

#define REG_A6XX_PC_PERFCTR_PC_SEL_5				0x00009e39

#define REG_A6XX_PC_PERFCTR_PC_SEL_6				0x00009e3a

#define REG_A6XX_PC_PERFCTR_PC_SEL_7				0x00009e3b

#define REG_A6XX_PC_UNKNOWN_9E72				0x00009e72

#define REG_A6XX_VFD_CONTROL_0					0x0000a000
#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK			0x0000003f
#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT			0
static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
}
#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK			0x00003f00
#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT			8
static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
}

#define REG_A6XX_VFD_CONTROL_1					0x0000a001
#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
}
#define A6XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT			8
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
}
#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT			16
static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
}

#define REG_A6XX_VFD_CONTROL_2					0x0000a002
#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK		0x000000ff
#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT		0
static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
}
#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK		0x0000ff00
#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT		8
static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
}

#define REG_A6XX_VFD_CONTROL_3					0x0000a003
#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK		0x0000ff00
#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT		8
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
}
#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT			16
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
}
#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT			24
static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
}

#define REG_A6XX_VFD_CONTROL_4					0x0000a004

#define REG_A6XX_VFD_CONTROL_5					0x0000a005
#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK			0x000000ff
#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT		0
static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
{
	return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
}

#define REG_A6XX_VFD_CONTROL_6					0x0000a006
#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU			0x00000001

#define REG_A6XX_VFD_MODE_CNTL					0x0000a007
#define A6XX_VFD_MODE_CNTL_BINNING_PASS				0x00000001

#define REG_A6XX_VFD_UNKNOWN_A008				0x0000a008

#define REG_A6XX_VFD_ADD_OFFSET					0x0000a009
#define A6XX_VFD_ADD_OFFSET_VERTEX				0x00000001
#define A6XX_VFD_ADD_OFFSET_INSTANCE				0x00000002

#define REG_A6XX_VFD_INDEX_OFFSET				0x0000a00e

#define REG_A6XX_VFD_INSTANCE_START_OFFSET			0x0000a00f

static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }

static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }

static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
#define A6XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT			0
static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
{
	return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
}
#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK			0x0001ffe0
#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT			5
static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
{
	return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
}
#define A6XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT			20
static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
}
#define A6XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT			28
static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
}
#define A6XX_VFD_DECODE_INSTR_UNK30				0x40000000
#define A6XX_VFD_DECODE_INSTR_FLOAT				0x80000000

static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }

static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }

static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
{
	return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
}
#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT			4
static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
{
	return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
}

#define REG_A6XX_SP_UNKNOWN_A0F8				0x0000a0f8

#define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_VS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_VS_BRANCH_COND				0x0000a801

#define REG_A6XX_SP_VS_PRIMITIVE_CNTL				0x0000a802
#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT			0
static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
{
	return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
}

static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
#define A6XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
}
#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT			8
static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
}
#define A6XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT			16
static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
}
#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT			24
static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}

static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
{
	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
}
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT			8
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
{
	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
}
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT			16
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
{
	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
}
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT			24
static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
{
	return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
}

#define REG_A6XX_SP_UNKNOWN_A81B				0x0000a81b

#define REG_A6XX_SP_VS_OBJ_START_LO				0x0000a81c

#define REG_A6XX_SP_VS_OBJ_START_HI				0x0000a81d

#define REG_A6XX_SP_VS_TEX_COUNT				0x0000a822

#define REG_A6XX_SP_VS_CONFIG					0x0000a823
#define A6XX_SP_VS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_VS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_VS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_VS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_VS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_VS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_VS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_VS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_VS_INSTRLEN					0x0000a824

#define REG_A6XX_SP_HS_CTRL_REG0				0x0000a830
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_HS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_HS_UNKNOWN_A831				0x0000a831

#define REG_A6XX_SP_HS_UNKNOWN_A833				0x0000a833

#define REG_A6XX_SP_HS_OBJ_START_LO				0x0000a834

#define REG_A6XX_SP_HS_OBJ_START_HI				0x0000a835

#define REG_A6XX_SP_HS_TEX_COUNT				0x0000a83a

#define REG_A6XX_SP_HS_CONFIG					0x0000a83b
#define A6XX_SP_HS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_HS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_HS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_HS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_HS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_HS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_HS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_HS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_HS_INSTRLEN					0x0000a83c

#define REG_A6XX_SP_DS_CTRL_REG0				0x0000a840
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_DS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_DS_PRIMITIVE_CNTL				0x0000a842
#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT			0
static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
{
	return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
}

static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
#define A6XX_SP_DS_OUT_REG_A_REGID__MASK			0x000000ff
#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
}
#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00000f00
#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT			8
static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
}
#define A6XX_SP_DS_OUT_REG_B_REGID__MASK			0x00ff0000
#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT			16
static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
}
#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x0f000000
#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT			24
static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
}

static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
{
	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
}
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT			8
static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
{
	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
}
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT			16
static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
{
	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
}
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT			24
static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
{
	return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
}

#define REG_A6XX_SP_DS_UNKNOWN_A85B				0x0000a85b

#define REG_A6XX_SP_DS_OBJ_START_LO				0x0000a85c

#define REG_A6XX_SP_DS_OBJ_START_HI				0x0000a85d

#define REG_A6XX_SP_DS_TEX_COUNT				0x0000a862

#define REG_A6XX_SP_DS_CONFIG					0x0000a863
#define A6XX_SP_DS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_DS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_DS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_DS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_DS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_DS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_DS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_DS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_DS_INSTRLEN					0x0000a864

#define REG_A6XX_SP_GS_CTRL_REG0				0x0000a870
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_GS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_GS_PRIM_SIZE				0x0000a871

#define REG_A6XX_SP_GS_BRANCH_COND				0x0000a872

#define REG_A6XX_SP_GS_PRIMITIVE_CNTL				0x0000a873
#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT			0
static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
{
	return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
}
#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT		6
static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
}

static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
#define A6XX_SP_GS_OUT_REG_A_REGID__MASK			0x000000ff
#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
}
#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00000f00
#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT			8
static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
}
#define A6XX_SP_GS_OUT_REG_B_REGID__MASK			0x00ff0000
#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT			16
static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
}
#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x0f000000
#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT			24
static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
{
	return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
}

static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
{
	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
}
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT			8
static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
{
	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
}
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT			16
static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
{
	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
}
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT			24
static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
{
	return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
}

#define REG_A6XX_SP_GS_OBJ_START_LO				0x0000a88d

#define REG_A6XX_SP_GS_OBJ_START_HI				0x0000a88e

#define REG_A6XX_SP_GS_TEX_COUNT				0x0000a893

#define REG_A6XX_SP_GS_CONFIG					0x0000a894
#define A6XX_SP_GS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_GS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_GS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_GS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_GS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_GS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_GS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_GS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_GS_INSTRLEN					0x0000a895

#define REG_A6XX_SP_VS_TEX_SAMP_LO				0x0000a8a0

#define REG_A6XX_SP_VS_TEX_SAMP_HI				0x0000a8a1

#define REG_A6XX_SP_HS_TEX_SAMP_LO				0x0000a8a2

#define REG_A6XX_SP_HS_TEX_SAMP_HI				0x0000a8a3

#define REG_A6XX_SP_DS_TEX_SAMP_LO				0x0000a8a4

#define REG_A6XX_SP_DS_TEX_SAMP_HI				0x0000a8a5

#define REG_A6XX_SP_GS_TEX_SAMP_LO				0x0000a8a6

#define REG_A6XX_SP_GS_TEX_SAMP_HI				0x0000a8a7

#define REG_A6XX_SP_VS_TEX_CONST_LO				0x0000a8a8

#define REG_A6XX_SP_VS_TEX_CONST_HI				0x0000a8a9

#define REG_A6XX_SP_HS_TEX_CONST_LO				0x0000a8aa

#define REG_A6XX_SP_HS_TEX_CONST_HI				0x0000a8ab

#define REG_A6XX_SP_DS_TEX_CONST_LO				0x0000a8ac

#define REG_A6XX_SP_DS_TEX_CONST_HI				0x0000a8ad

#define REG_A6XX_SP_GS_TEX_CONST_LO				0x0000a8ae

#define REG_A6XX_SP_GS_TEX_CONST_HI				0x0000a8af

#define REG_A6XX_SP_FS_CTRL_REG0				0x0000a980
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_FS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_FS_BRANCH_COND				0x0000a981

#define REG_A6XX_SP_UNKNOWN_A982				0x0000a982

#define REG_A6XX_SP_FS_OBJ_START_LO				0x0000a983

#define REG_A6XX_SP_FS_OBJ_START_HI				0x0000a984

#define REG_A6XX_SP_BLEND_CNTL					0x0000a989
#define A6XX_SP_BLEND_CNTL_ENABLED				0x00000001
#define A6XX_SP_BLEND_CNTL_UNK8					0x00000100
#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400

#define REG_A6XX_SP_SRGB_CNTL					0x0000a98a
#define A6XX_SP_SRGB_CNTL_SRGB_MRT0				0x00000001
#define A6XX_SP_SRGB_CNTL_SRGB_MRT1				0x00000002
#define A6XX_SP_SRGB_CNTL_SRGB_MRT2				0x00000004
#define A6XX_SP_SRGB_CNTL_SRGB_MRT3				0x00000008
#define A6XX_SP_SRGB_CNTL_SRGB_MRT4				0x00000010
#define A6XX_SP_SRGB_CNTL_SRGB_MRT5				0x00000020
#define A6XX_SP_SRGB_CNTL_SRGB_MRT6				0x00000040
#define A6XX_SP_SRGB_CNTL_SRGB_MRT7				0x00000080

#define REG_A6XX_SP_FS_RENDER_COMPONENTS			0x0000a98b
#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK			0x0000000f
#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT			0
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK			0x000000f0
#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT			4
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK			0x00000f00
#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT			8
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK			0x0000f000
#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT			12
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK			0x000f0000
#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT			16
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK			0x00f00000
#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT			20
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK			0x0f000000
#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT			24
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
}
#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK			0xf0000000
#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT			28
static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
{
	return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
}

#define REG_A6XX_SP_FS_OUTPUT_CNTL0				0x0000a98c
#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK		0x0000ff00
#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT		8
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
}
#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK		0x00ff0000
#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT		16
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
}
#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK		0xff000000
#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT		24
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
}

#define REG_A6XX_SP_FS_OUTPUT_CNTL1				0x0000a98d
#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT			0
static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
{
	return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
}

static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
}
#define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
#define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200

#define REG_A6XX_SP_FS_PREFETCH_CNTL				0x0000a99e
#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK			0x00000007
#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT			0
static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
}
#define A6XX_SP_FS_PREFETCH_CNTL_UNK3				0x00000008
#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK			0x00000ff0
#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT			4
static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
}

static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK			0x0000007f
#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT			0
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
}
#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK			0x00000780
#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT			7
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
}
#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK			0x0000f800
#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT			11
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
}
#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK			0x003f0000
#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT			16
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
}
#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK			0x03c00000
#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT			22
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
}
#define A6XX_SP_FS_PREFETCH_CMD_HALF				0x04000000
#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK			0xf8000000
#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT			27
static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
{
	return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
}

static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK		0x000000ff
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT		0
static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
}
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK		0x00ff0000
#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT		16
static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
}

#define REG_A6XX_SP_FS_TEX_COUNT				0x0000a9a7

#define REG_A6XX_SP_UNKNOWN_A9A8				0x0000a9a8

#define REG_A6XX_SP_CS_UNKNOWN_A9B1				0x0000a9b1
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK		0x00000001
#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT		0
static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
{
	return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
}

#define REG_A6XX_SP_CS_UNKNOWN_A9B3				0x0000a9b3

#define REG_A6XX_SP_CS_TEX_COUNT				0x0000a9ba

#define REG_A6XX_SP_FS_TEX_SAMP_LO				0x0000a9e0

#define REG_A6XX_SP_FS_TEX_SAMP_HI				0x0000a9e1

#define REG_A6XX_SP_CS_TEX_SAMP_LO				0x0000a9e2

#define REG_A6XX_SP_CS_TEX_SAMP_HI				0x0000a9e3

#define REG_A6XX_SP_FS_TEX_CONST_LO				0x0000a9e4

#define REG_A6XX_SP_FS_TEX_CONST_HI				0x0000a9e5

#define REG_A6XX_SP_CS_TEX_CONST_LO				0x0000a9e6

#define REG_A6XX_SP_CS_TEX_CONST_HI				0x0000a9e7

static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }

static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }

static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }

static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
{
	return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
}
#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100

#define REG_A6XX_SP_CS_CTRL_REG0				0x0000a9b0
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		1
static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		7
static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT			14
static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
}
#define A6XX_SP_CS_CTRL_REG0_VARYING				0x00400000
#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE				0x00800000
#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x04000000
#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS				0x80000000

#define REG_A6XX_SP_CS_OBJ_START_LO				0x0000a9b4

#define REG_A6XX_SP_CS_OBJ_START_HI				0x0000a9b5

#define REG_A6XX_SP_CS_CONFIG					0x0000a9bb
#define A6XX_SP_CS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_CS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_CS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_CS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_CS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_CS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_CS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_CS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_CS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_CS_INSTRLEN					0x0000a9bc

#define REG_A6XX_SP_CS_IBO_LO					0x0000a9f2

#define REG_A6XX_SP_CS_IBO_HI					0x0000a9f3

#define REG_A6XX_SP_CS_IBO_COUNT				0x0000aa00

#define REG_A6XX_SP_UNKNOWN_AB00				0x0000ab00

#define REG_A6XX_SP_FS_CONFIG					0x0000ab04
#define A6XX_SP_FS_CONFIG_BINDLESS_TEX				0x00000001
#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP				0x00000002
#define A6XX_SP_FS_CONFIG_BINDLESS_IBO				0x00000004
#define A6XX_SP_FS_CONFIG_BINDLESS_UBO				0x00000008
#define A6XX_SP_FS_CONFIG_ENABLED				0x00000100
#define A6XX_SP_FS_CONFIG_NTEX__MASK				0x0001fe00
#define A6XX_SP_FS_CONFIG_NTEX__SHIFT				9
static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
}
#define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x003e0000
#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT				17
static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
}
#define A6XX_SP_FS_CONFIG_NIBO__MASK				0x3fc00000
#define A6XX_SP_FS_CONFIG_NIBO__SHIFT				22
static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
{
	return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
}

#define REG_A6XX_SP_FS_INSTRLEN					0x0000ab05

static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }

static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }

#define REG_A6XX_SP_IBO_LO					0x0000ab1a

#define REG_A6XX_SP_IBO_HI					0x0000ab1b

#define REG_A6XX_SP_IBO_COUNT					0x0000ab20

#define REG_A6XX_SP_2D_DST_FORMAT				0x0000acc0
#define A6XX_SP_2D_DST_FORMAT_NORM				0x00000001
#define A6XX_SP_2D_DST_FORMAT_SINT				0x00000002
#define A6XX_SP_2D_DST_FORMAT_UINT				0x00000004
#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK		0x000007f8
#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT		3
static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
}
#define A6XX_SP_2D_DST_FORMAT_SRGB				0x00000800
#define A6XX_SP_2D_DST_FORMAT_MASK__MASK			0x0000f000
#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT			12
static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
{
	return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
}

#define REG_A6XX_SP_UNKNOWN_AE00				0x0000ae00

#define REG_A6XX_SP_UNKNOWN_AE03				0x0000ae03

#define REG_A6XX_SP_UNKNOWN_AE04				0x0000ae04

#define REG_A6XX_SP_UNKNOWN_AE0F				0x0000ae0f

#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR		0x0000b180

#define REG_A6XX_SP_UNKNOWN_B182				0x0000b182

#define REG_A6XX_SP_UNKNOWN_B183				0x0000b183

#define REG_A6XX_SP_TP_RAS_MSAA_CNTL				0x0000b300
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
}

#define REG_A6XX_SP_TP_DEST_MSAA_CNTL				0x0000b301
#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
}
#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004

#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR			0x0000b302

#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO		0x0000b302

#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI		0x0000b303

#define REG_A6XX_SP_TP_SAMPLE_CONFIG				0x0000b304
#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0				0x00000001
#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE		0x00000002

#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0			0x0000b305
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1			0x0000b306
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT		4
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT		8
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT		12
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT		16
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT		20
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT		24
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
}
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT		28
static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
{
	return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
}

#define REG_A6XX_SP_TP_UNKNOWN_B309				0x0000b309

#define REG_A6XX_SP_PS_2D_SRC_INFO				0x0000b4c0
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
}
#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT			8
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
}
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT		10
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
}
#define A6XX_SP_PS_2D_SRC_INFO_FLAGS				0x00001000
#define A6XX_SP_PS_2D_SRC_INFO_SRGB				0x00002000
#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK			0x0000c000
#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT			14
static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
}
#define A6XX_SP_PS_2D_SRC_INFO_FILTER				0x00010000
#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE			0x00040000
#define A6XX_SP_PS_2D_SRC_INFO_UNK20				0x00100000
#define A6XX_SP_PS_2D_SRC_INFO_UNK22				0x00400000

#define REG_A6XX_SP_PS_2D_SRC_SIZE				0x0000b4c1
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK			0x00007fff
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT			0
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
}
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK			0x3fff8000
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT			15
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
{
	return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
}

#define REG_A6XX_SP_PS_2D_SRC_LO				0x0000b4c2

#define REG_A6XX_SP_PS_2D_SRC_HI				0x0000b4c3

#define REG_A6XX_SP_PS_2D_SRC					0x0000b4c2

#define REG_A6XX_SP_PS_2D_SRC_PITCH				0x0000b4c4
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK			0x01fffe00
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT			9
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
}

#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO				0x0000b4ca

#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI				0x0000b4cb

#define REG_A6XX_SP_PS_2D_SRC_FLAGS				0x0000b4ca

#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH			0x0000b4cc
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK		0x000007ff
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT		0
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
}
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK		0x003ff800
#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT	11
static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
}

#define REG_A6XX_SP_UNKNOWN_B600				0x0000b600

#define REG_A6XX_SP_UNKNOWN_B605				0x0000b605

#define REG_A6XX_HLSQ_VS_CNTL					0x0000b800
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_VS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_HS_CNTL					0x0000b801
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_HS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_DS_CNTL					0x0000b802
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_DS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_GS_CNTL					0x0000b803
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_GS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD			0x0000b820

#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR		0x0000b821

#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA			0x0000b823

#define REG_A6XX_HLSQ_UNKNOWN_B980				0x0000b980

#define REG_A6XX_HLSQ_CONTROL_1_REG				0x0000b982

#define REG_A6XX_HLSQ_CONTROL_2_REG				0x0000b983
#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
}
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT			8
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
}
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT		16
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
}
#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT			24
static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
}

#define REG_A6XX_HLSQ_CONTROL_3_REG				0x0000b984
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
}
#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT		8
static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
}
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT	16
static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
}
#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT	24
static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
}

#define REG_A6XX_HLSQ_CONTROL_4_REG				0x0000b985
#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
}
#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT		8
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
}
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT		16
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
}
#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT		24
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
}

#define REG_A6XX_HLSQ_CONTROL_5_REG				0x0000b986

#define REG_A6XX_HLSQ_CS_CNTL					0x0000b987
#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_CS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_CS_NDRANGE_0				0x0000b990
#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
}
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT		2
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
}
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT		12
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
}
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT		22
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_1				0x0000b991
#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_2				0x0000b992
#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_3				0x0000b993
#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_4				0x0000b994
#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_5				0x0000b995
#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
}

#define REG_A6XX_HLSQ_CS_NDRANGE_6				0x0000b996
#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
}

#define REG_A6XX_HLSQ_CS_CNTL_0					0x0000b997
#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
}
#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK				0x0000ff00
#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT				8
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
}
#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK				0x00ff0000
#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT				16
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
}
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT			24
static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
}

#define REG_A6XX_HLSQ_CS_UNKNOWN_B998				0x0000b998

#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X				0x0000b999

#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000b99a

#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000b99b

#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD			0x0000b9a0

#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR		0x0000b9a1

#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA			0x0000b9a3

static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }

static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }

#define REG_A6XX_HLSQ_DRAW_CMD					0x0000bb00
#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK			0x000000ff
#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT			0
static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
}

#define REG_A6XX_HLSQ_DISPATCH_CMD				0x0000bb01
#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT			0
static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
}

#define REG_A6XX_HLSQ_EVENT_CMD					0x0000bb02
#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK			0x00ff0000
#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT			16
static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
}
#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK				0x0000007f
#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT			0
static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
{
	return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
}

#define REG_A6XX_HLSQ_INVALIDATE_CMD				0x0000bb08
#define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE			0x00000001
#define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE			0x00000002
#define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE			0x00000004
#define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE			0x00000008
#define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE			0x00000010
#define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE			0x00000020
#define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO				0x00000040
#define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO			0x00000080
#define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST		0x00080000
#define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST		0x00000100
#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK		0x00003e00
#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT		9
static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
{
	return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
}
#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK		0x0007c000
#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT		14
static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
{
	return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
}

#define REG_A6XX_HLSQ_FS_CNTL					0x0000bb10
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK			0x000000ff
#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT			0
static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
{
	return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
}
#define A6XX_HLSQ_FS_CNTL_ENABLED				0x00000100

#define REG_A6XX_HLSQ_SHARED_CONSTS				0x0000bb11
#define A6XX_HLSQ_SHARED_CONSTS_ENABLE				0x00000001

static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }

static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }

#define REG_A6XX_HLSQ_2D_EVENT_CMD				0x0000bd80
#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT			8
static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
}
#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK			0x0000007f
#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT			0
static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
{
	return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
}

#define REG_A6XX_HLSQ_UNKNOWN_BE00				0x0000be00

#define REG_A6XX_HLSQ_UNKNOWN_BE01				0x0000be01

#define REG_A6XX_HLSQ_UNKNOWN_BE04				0x0000be04

#define REG_A6XX_CP_EVENT_START					0x0000d600
#define A6XX_CP_EVENT_START_STATE_ID__MASK			0x000000ff
#define A6XX_CP_EVENT_START_STATE_ID__SHIFT			0
static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
}

#define REG_A6XX_CP_EVENT_END					0x0000d601
#define A6XX_CP_EVENT_END_STATE_ID__MASK			0x000000ff
#define A6XX_CP_EVENT_END_STATE_ID__SHIFT			0
static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
}

#define REG_A6XX_CP_2D_EVENT_START				0x0000d700
#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK			0x000000ff
#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT			0
static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
}

#define REG_A6XX_CP_2D_EVENT_END				0x0000d701
#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK			0x000000ff
#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT			0
static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
{
	return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
}

#define REG_A6XX_TEX_SAMP_0					0x00000000
#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
#define A6XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT				1
static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
{
	return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
}
#define A6XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT				3
static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
{
	return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
}
#define A6XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT				5
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
{
	return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
}
#define A6XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT				8
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
{
	return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
}
#define A6XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT				11
static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
{
	return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
}
#define A6XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
#define A6XX_TEX_SAMP_0_ANISO__SHIFT				14
static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
{
	return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
}
#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT				19
static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
{
	return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
}

#define REG_A6XX_TEX_SAMP_1					0x00000001
#define A6XX_TEX_SAMP_1_UNK0					0x00000001
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT			1
static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
{
	return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
}
#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
#define A6XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
#define A6XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT				8
static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
{
	return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
}
#define A6XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT				20
static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
{
	return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
}

#define REG_A6XX_TEX_SAMP_2					0x00000002
#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK			0x00000003
#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT			0
static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
{
	return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
}
#define A6XX_TEX_SAMP_2_CHROMA_LINEAR				0x00000020
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT			7
static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
{
	return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
}

#define REG_A6XX_TEX_SAMP_3					0x00000003

#define REG_A6XX_TEX_CONST_0					0x00000000
#define A6XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT			0
static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
}
#define A6XX_TEX_CONST_0_SRGB					0x00000004
#define A6XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT				4
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
{
	return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
}
#define A6XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT				7
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
{
	return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
}
#define A6XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT				10
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
{
	return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
}
#define A6XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT				13
static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
{
	return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
}
#define A6XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT				16
static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
}
#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X			0x00010000
#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y			0x00040000
#define A6XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
#define A6XX_TEX_CONST_0_SAMPLES__SHIFT				20
static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
}
#define A6XX_TEX_CONST_0_FMT__MASK				0x3fc00000
#define A6XX_TEX_CONST_0_FMT__SHIFT				22
static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
{
	return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
}
#define A6XX_TEX_CONST_0_SWAP__MASK				0xc0000000
#define A6XX_TEX_CONST_0_SWAP__SHIFT				30
static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
}

#define REG_A6XX_TEX_CONST_1					0x00000001
#define A6XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
#define A6XX_TEX_CONST_1_WIDTH__SHIFT				0
static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
}
#define A6XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
#define A6XX_TEX_CONST_1_HEIGHT__SHIFT				15
static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
}

#define REG_A6XX_TEX_CONST_2					0x00000002
#define A6XX_TEX_CONST_2_UNK4					0x00000010
#define A6XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
}
#define A6XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
#define A6XX_TEX_CONST_2_PITCH__SHIFT				7
static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
}
#define A6XX_TEX_CONST_2_TYPE__MASK				0x60000000
#define A6XX_TEX_CONST_2_TYPE__SHIFT				29
static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
{
	return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
}
#define A6XX_TEX_CONST_2_UNK31					0x80000000

#define REG_A6XX_TEX_CONST_3					0x00000003
#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
}
#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT			23
static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
{
	return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
}
#define A6XX_TEX_CONST_3_TILE_ALL				0x08000000
#define A6XX_TEX_CONST_3_FLAG					0x10000000

#define REG_A6XX_TEX_CONST_4					0x00000004
#define A6XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
#define A6XX_TEX_CONST_4_BASE_LO__SHIFT				5
static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
{
	return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
}

#define REG_A6XX_TEX_CONST_5					0x00000005
#define A6XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
#define A6XX_TEX_CONST_5_BASE_HI__SHIFT				0
static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
}
#define A6XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
#define A6XX_TEX_CONST_5_DEPTH__SHIFT				17
static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
}

#define REG_A6XX_TEX_CONST_6					0x00000006
#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK			0xffffff00
#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT			8
static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
}

#define REG_A6XX_TEX_CONST_7					0x00000007
#define A6XX_TEX_CONST_7_FLAG_LO__MASK				0xffffffe0
#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT				5
static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
{
	return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
}

#define REG_A6XX_TEX_CONST_8					0x00000008
#define A6XX_TEX_CONST_8_FLAG_HI__MASK				0x0001ffff
#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT				0
static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
}

#define REG_A6XX_TEX_CONST_9					0x00000009
#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
}

#define REG_A6XX_TEX_CONST_10					0x0000000a
#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK		0x0000007f
#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT		0
static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
}
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK		0x00000f00
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT		8
static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
}
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK		0x0000f000
#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT		12
static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
{
	return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
}

#define REG_A6XX_TEX_CONST_11					0x0000000b

#define REG_A6XX_TEX_CONST_12					0x0000000c

#define REG_A6XX_TEX_CONST_13					0x0000000d

#define REG_A6XX_TEX_CONST_14					0x0000000e

#define REG_A6XX_TEX_CONST_15					0x0000000f

#define REG_A6XX_IBO_0						0x00000000
#define A6XX_IBO_0_TILE_MODE__MASK				0x00000003
#define A6XX_IBO_0_TILE_MODE__SHIFT				0
static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
{
	return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
}
#define A6XX_IBO_0_FMT__MASK					0x3fc00000
#define A6XX_IBO_0_FMT__SHIFT					22
static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
{
	return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
}

#define REG_A6XX_IBO_1						0x00000001
#define A6XX_IBO_1_WIDTH__MASK					0x00007fff
#define A6XX_IBO_1_WIDTH__SHIFT					0
static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
{
	return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
}
#define A6XX_IBO_1_HEIGHT__MASK					0x3fff8000
#define A6XX_IBO_1_HEIGHT__SHIFT				15
static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
{
	return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
}

#define REG_A6XX_IBO_2						0x00000002
#define A6XX_IBO_2_UNK4						0x00000010
#define A6XX_IBO_2_PITCH__MASK					0x1fffff80
#define A6XX_IBO_2_PITCH__SHIFT					7
static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
{
	return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
}
#define A6XX_IBO_2_TYPE__MASK					0x60000000
#define A6XX_IBO_2_TYPE__SHIFT					29
static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
{
	return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
}
#define A6XX_IBO_2_UNK31					0x80000000

#define REG_A6XX_IBO_3						0x00000003
#define A6XX_IBO_3_ARRAY_PITCH__MASK				0x00003fff
#define A6XX_IBO_3_ARRAY_PITCH__SHIFT				0
static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
}
#define A6XX_IBO_3_UNK27					0x08000000
#define A6XX_IBO_3_FLAG						0x10000000

#define REG_A6XX_IBO_4						0x00000004
#define A6XX_IBO_4_BASE_LO__MASK				0xffffffff
#define A6XX_IBO_4_BASE_LO__SHIFT				0
static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
{
	return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
}

#define REG_A6XX_IBO_5						0x00000005
#define A6XX_IBO_5_BASE_HI__MASK				0x0001ffff
#define A6XX_IBO_5_BASE_HI__SHIFT				0
static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
{
	return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
}
#define A6XX_IBO_5_DEPTH__MASK					0x3ffe0000
#define A6XX_IBO_5_DEPTH__SHIFT					17
static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
{
	return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
}

#define REG_A6XX_IBO_6						0x00000006

#define REG_A6XX_IBO_7						0x00000007

#define REG_A6XX_IBO_8						0x00000008

#define REG_A6XX_IBO_9						0x00000009
#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
{
	return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
}

#define REG_A6XX_IBO_10						0x0000000a
#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK			0x0000007f
#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT			0
static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
{
	return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
}

#define REG_A6XX_UBO_0						0x00000000
#define A6XX_UBO_0_BASE_LO__MASK				0xffffffff
#define A6XX_UBO_0_BASE_LO__SHIFT				0
static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
{
	return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
}

#define REG_A6XX_UBO_1						0x00000001
#define A6XX_UBO_1_BASE_HI__MASK				0x0001ffff
#define A6XX_UBO_1_BASE_HI__SHIFT				0
static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
{
	return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
}
#define A6XX_UBO_1_SIZE__MASK					0xfffe0000
#define A6XX_UBO_1_SIZE__SHIFT					17
static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
{
	return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
}

#define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00001140

#define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00001148

#define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00001540

#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00001541

#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00001542

#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00001543

#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00001544

#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00001545

#define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00001572

#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00001573

#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00001574

#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00001575

#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00001576

#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00001577

#define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000015a4

#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000015a5

#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000015a6

#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000015a7

#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000015a8

#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000015a9

#define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000015d6

#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000015d7

#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000015d8

#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000015d9

#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000015da

#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000015db

#define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x00000000

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00000000
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK		0x000000ff
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT		0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK	0x0000ff00
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT	8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
}

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00000001

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00000002

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00000003

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00000004
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT		12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT		28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
}

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00000005
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT		24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
}

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00000008

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00000009

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0000000a

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0000000b

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0000000c

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0000000d

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0000000e

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0000000f

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000010
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT		4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT		8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT		12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT		16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT		20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT		24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT		28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
}

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000011
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT		4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT		8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT		12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT		16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT		20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT		24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT		28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
{
	return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
}

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000002f

#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000030

#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0			0x00000001

#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1			0x00000002


#endif /* A6XX_XML */