1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
#ifndef __iop_fifo_out_extra_defs_h
#define __iop_fifo_out_extra_defs_h
/*
* This file is autogenerated from
* file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: <not found>
* last modfied: Mon Apr 11 16:10:10 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
* id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope iop_fifo_out_extra */
/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
/* Register r_rd_data, scope iop_fifo_out_extra, type r */
typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
/* Register r_stat, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int avail_bytes : 4;
unsigned int last : 8;
unsigned int dif_in_en : 1;
unsigned int dif_out_en : 1;
unsigned int zero_data_last : 1;
unsigned int dummy1 : 17;
} reg_iop_fifo_out_extra_r_stat;
#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_rw_intr_mask;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_rw_ack_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
/* Register r_intr, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_r_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
typedef struct {
unsigned int urun : 1;
unsigned int last_data : 1;
unsigned int dav : 1;
unsigned int free : 1;
unsigned int orun : 1;
unsigned int dummy1 : 27;
} reg_iop_fifo_out_extra_r_masked_intr;
#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
/* Constants */
enum {
regk_iop_fifo_out_extra_no = 0x00000000,
regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
regk_iop_fifo_out_extra_yes = 0x00000001
};
#endif /* __iop_fifo_out_extra_defs_h */
|
