summaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/rt5640.h
blob: 58ebe96b86dae452165fc679ce424017e9088833 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
/*
 * rt5640.h  --  RT5640 ALSA SoC audio driver
 *
 * Copyright 2011 Realtek Microelectronics
 * Author: Johnny Hsu <johnnyhsu@realtek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _RT5640_H
#define _RT5640_H

#include <sound/rt5640.h>

/* Info */
#define RT5640_RESET				0x00
#define RT5640_VENDOR_ID			0xfd
#define RT5640_VENDOR_ID1			0xfe
#define RT5640_VENDOR_ID2			0xff
/*  I/O - Output */
#define RT5640_SPK_VOL				0x01
#define RT5640_HP_VOL				0x02
#define RT5640_OUTPUT				0x03
#define RT5640_MONO_OUT				0x04
/* I/O - Input */
#define RT5640_IN1_IN2				0x0d
#define RT5640_IN3_IN4				0x0e
#define RT5640_INL_INR_VOL			0x0f
/* I/O - ADC/DAC/DMIC */
#define RT5640_DAC1_DIG_VOL			0x19
#define RT5640_DAC2_DIG_VOL			0x1a
#define RT5640_DAC2_CTRL			0x1b
#define RT5640_ADC_DIG_VOL			0x1c
#define RT5640_ADC_DATA				0x1d
#define RT5640_ADC_BST_VOL			0x1e
/* Mixer - D-D */
#define RT5640_STO_ADC_MIXER			0x27
#define RT5640_MONO_ADC_MIXER			0x28
#define RT5640_AD_DA_MIXER			0x29
#define RT5640_STO_DAC_MIXER			0x2a
#define RT5640_MONO_DAC_MIXER			0x2b
#define RT5640_DIG_MIXER			0x2c
#define RT5640_DSP_PATH1			0x2d
#define RT5640_DSP_PATH2			0x2e
#define RT5640_DIG_INF_DATA			0x2f
/* Mixer - ADC */
#define RT5640_REC_L1_MIXER			0x3b
#define RT5640_REC_L2_MIXER			0x3c
#define RT5640_REC_R1_MIXER			0x3d
#define RT5640_REC_R2_MIXER			0x3e
/* Mixer - DAC */
#define RT5640_HPO_MIXER			0x45
#define RT5640_SPK_L_MIXER			0x46
#define RT5640_SPK_R_MIXER			0x47
#define RT5640_SPO_L_MIXER			0x48
#define RT5640_SPO_R_MIXER			0x49
#define RT5640_SPO_CLSD_RATIO			0x4a
#define RT5640_MONO_MIXER			0x4c
#define RT5640_OUT_L1_MIXER			0x4d
#define RT5640_OUT_L2_MIXER			0x4e
#define RT5640_OUT_L3_MIXER			0x4f
#define RT5640_OUT_R1_MIXER			0x50
#define RT5640_OUT_R2_MIXER			0x51
#define RT5640_OUT_R3_MIXER			0x52
#define RT5640_LOUT_MIXER			0x53
/* Power */
#define RT5640_PWR_DIG1				0x61
#define RT5640_PWR_DIG2				0x62
#define RT5640_PWR_ANLG1			0x63
#define RT5640_PWR_ANLG2			0x64
#define RT5640_PWR_MIXER			0x65
#define RT5640_PWR_VOL				0x66
/* Private Register Control */
#define RT5640_PRIV_INDEX			0x6a
#define RT5640_PRIV_DATA			0x6c
/* Format - ADC/DAC */
#define RT5640_I2S1_SDP				0x70
#define RT5640_I2S2_SDP				0x71
#define RT5640_ADDA_CLK1			0x73
#define RT5640_ADDA_CLK2			0x74
#define RT5640_DMIC				0x75
/* Function - Analog */
#define RT5640_GLB_CLK				0x80
#define RT5640_PLL_CTRL1			0x81
#define RT5640_PLL_CTRL2			0x82
#define RT5640_ASRC_1				0x83
#define RT5640_ASRC_2				0x84
#define RT5640_ASRC_3				0x85
#define RT5640_ASRC_4				0x89
#define RT5640_ASRC_5				0x8a
#define RT5640_HP_OVCD				0x8b
#define RT5640_CLS_D_OVCD			0x8c
#define RT5640_CLS_D_OUT			0x8d
#define RT5640_DEPOP_M1				0x8e
#define RT5640_DEPOP_M2				0x8f
#define RT5640_DEPOP_M3				0x90
#define RT5640_CHARGE_PUMP			0x91
#define RT5640_PV_DET_SPK_G			0x92
#define RT5640_MICBIAS				0x93
/* Function - Digital */
#define RT5640_EQ_CTRL1				0xb0
#define RT5640_EQ_CTRL2				0xb1
#define RT5640_WIND_FILTER			0xb2
#define RT5640_DRC_AGC_1			0xb4
#define RT5640_DRC_AGC_2			0xb5
#define RT5640_DRC_AGC_3			0xb6
#define RT5640_SVOL_ZC				0xb7
#define RT5640_ANC_CTRL1			0xb8
#define RT5640_ANC_CTRL2			0xb9
#define RT5640_ANC_CTRL3			0xba
#define RT5640_JD_CTRL				0xbb
#define RT5640_ANC_JD				0xbc
#define RT5640_IRQ_CTRL1			0xbd
#define RT5640_IRQ_CTRL2			0xbe
#define RT5640_INT_IRQ_ST			0xbf
#define RT5640_GPIO_CTRL1			0xc0
#define RT5640_GPIO_CTRL2			0xc1
#define RT5640_GPIO_CTRL3			0xc2
#define RT5640_DSP_CTRL1			0xc4
#define RT5640_DSP_CTRL2			0xc5
#define RT5640_DSP_CTRL3			0xc6
#define RT5640_DSP_CTRL4			0xc7
#define RT5640_PGM_REG_ARR1			0xc8
#define RT5640_PGM_REG_ARR2			0xc9
#define RT5640_PGM_REG_ARR3			0xca
#define RT5640_PGM_REG_ARR4			0xcb
#define RT5640_PGM_REG_ARR5			0xcc
#define RT5640_SCB_FUNC				0xcd
#define RT5640_SCB_CTRL				0xce
#define RT5640_BASE_BACK			0xcf
#define RT5640_MP3_PLUS1			0xd0
#define RT5640_MP3_PLUS2			0xd1
#define RT5640_3D_HP				0xd2
#define RT5640_ADJ_HPF				0xd3
#define RT5640_HP_CALIB_AMP_DET			0xd6
#define RT5640_HP_CALIB2			0xd7
#define RT5640_SV_ZCD1				0xd9
#define RT5640_SV_ZCD2				0xda
/* Dummy Register */
#define RT5640_DUMMY1				0xfa
#define RT5640_DUMMY2				0xfb
#define RT5640_DUMMY3				0xfc


/* Index of Codec Private Register definition */
#define RT5640_CHPUMP_INT_REG1			0x24
#define RT5640_MAMP_INT_REG2			0x37
#define RT5640_3D_SPK				0x63
#define RT5640_WND_1				0x6c
#define RT5640_WND_2				0x6d
#define RT5640_WND_3				0x6e
#define RT5640_WND_4				0x6f
#define RT5640_WND_5				0x70
#define RT5640_WND_8				0x73
#define RT5640_DIP_SPK_INF			0x75
#define RT5640_HP_DCC_INT1			0x77
#define RT5640_EQ_BW_LOP			0xa0
#define RT5640_EQ_GN_LOP			0xa1
#define RT5640_EQ_FC_BP1			0xa2
#define RT5640_EQ_BW_BP1			0xa3
#define RT5640_EQ_GN_BP1			0xa4
#define RT5640_EQ_FC_BP2			0xa5
#define RT5640_EQ_BW_BP2			0xa6
#define RT5640_EQ_GN_BP2			0xa7
#define RT5640_EQ_FC_BP3			0xa8
#define RT5640_EQ_BW_BP3			0xa9
#define RT5640_EQ_GN_BP3			0xaa
#define RT5640_EQ_FC_BP4			0xab
#define RT5640_EQ_BW_BP4			0xac
#define RT5640_EQ_GN_BP4			0xad
#define RT5640_EQ_FC_HIP1			0xae
#define RT5640_EQ_GN_HIP1			0xaf
#define RT5640_EQ_FC_HIP2			0xb0
#define RT5640_EQ_BW_HIP2			0xb1
#define RT5640_EQ_GN_HIP2			0xb2
#define RT5640_EQ_PRE_VOL			0xb3
#define RT5640_EQ_PST_VOL			0xb4

/* global definition */
#define RT5640_L_MUTE				(0x1 << 15)
#define RT5640_L_MUTE_SFT			15
#define RT5640_VOL_L_MUTE			(0x1 << 14)
#define RT5640_VOL_L_SFT			14
#define RT5640_R_MUTE				(0x1 << 7)
#define RT5640_R_MUTE_SFT			7
#define RT5640_VOL_R_MUTE			(0x1 << 6)
#define RT5640_VOL_R_SFT			6
#define RT5640_L_VOL_MASK			(0x3f << 8)
#define RT5640_L_VOL_SFT			8
#define RT5640_R_VOL_MASK			(0x3f)
#define RT5640_R_VOL_SFT			0

/* SW Reset & Device ID (0x00) */
#define RT5640_ID_MASK				(0x3 << 1)
#define RT5640_ID_5639				(0x0 << 1)
#define RT5640_ID_5640				(0x2 << 1)
#define RT5640_ID_5642				(0x3 << 1)


/* IN1 and IN2 Control (0x0d) */
/* IN3 and IN4 Control (0x0e) */
#define RT5640_BST_SFT1				12
#define RT5640_BST_SFT2				8
#define RT5640_IN_DF1				(0x1 << 7)
#define RT5640_IN_SFT1				7
#define RT5640_IN_DF2				(0x1 << 6)
#define RT5640_IN_SFT2				6

/* INL and INR Volume Control (0x0f) */
#define RT5640_INL_SEL_MASK			(0x1 << 15)
#define RT5640_INL_SEL_SFT			15
#define RT5640_INL_SEL_IN4P			(0x0 << 15)
#define RT5640_INL_SEL_MONOP			(0x1 << 15)
#define RT5640_INL_VOL_MASK			(0x1f << 8)
#define RT5640_INL_VOL_SFT			8
#define RT5640_INR_SEL_MASK			(0x1 << 7)
#define RT5640_INR_SEL_SFT			7
#define RT5640_INR_SEL_IN4N			(0x0 << 7)
#define RT5640_INR_SEL_MONON			(0x1 << 7)
#define RT5640_INR_VOL_MASK			(0x1f)
#define RT5640_INR_VOL_SFT			0

/* DAC1 Digital Volume (0x19) */
#define RT5640_DAC_L1_VOL_MASK			(0xff << 8)
#define RT5640_DAC_L1_VOL_SFT			8
#define RT5640_DAC_R1_VOL_MASK			(0xff)
#define RT5640_DAC_R1_VOL_SFT			0

/* DAC2 Digital Volume (0x1a) */
#define RT5640_DAC_L2_VOL_MASK			(0xff << 8)
#define RT5640_DAC_L2_VOL_SFT			8
#define RT5640_DAC_R2_VOL_MASK			(0xff)
#define RT5640_DAC_R2_VOL_SFT			0

/* DAC2 Control (0x1b) */
#define RT5640_M_DAC_L2_VOL			(0x1 << 13)
#define RT5640_M_DAC_L2_VOL_SFT			13
#define RT5640_M_DAC_R2_VOL			(0x1 << 12)
#define RT5640_M_DAC_R2_VOL_SFT			12

/* ADC Digital Volume Control (0x1c) */
#define RT5640_ADC_L_VOL_MASK			(0x7f << 8)
#define RT5640_ADC_L_VOL_SFT			8
#define RT5640_ADC_R_VOL_MASK			(0x7f)
#define RT5640_ADC_R_VOL_SFT			0

/* Mono ADC Digital Volume Control (0x1d) */
#define RT5640_MONO_ADC_L_VOL_MASK		(0x7f << 8)
#define RT5640_MONO_ADC_L_VOL_SFT		8
#define RT5640_MONO_ADC_R_VOL_MASK		(0x7f)
#define RT5640_MONO_ADC_R_VOL_SFT		0

/* ADC Boost Volume Control (0x1e) */
#define RT5640_ADC_L_BST_MASK			(0x3 << 14)
#define RT5640_ADC_L_BST_SFT			14
#define RT5640_ADC_R_BST_MASK			(0x3 << 12)
#define RT5640_ADC_R_BST_SFT			12
#define RT5640_ADC_COMP_MASK			(0x3 << 10)
#define RT5640_ADC_COMP_SFT			10

/* Stereo ADC Mixer Control (0x27) */
#define RT5640_M_ADC_L1				(0x1 << 14)
#define RT5640_M_ADC_L1_SFT			14
#define RT5640_M_ADC_L2				(0x1 << 13)
#define RT5640_M_ADC_L2_SFT			13
#define RT5640_ADC_1_SRC_MASK			(0x1 << 12)
#define RT5640_ADC_1_SRC_SFT			12
#define RT5640_ADC_1_SRC_ADC			(0x1 << 12)
#define RT5640_ADC_1_SRC_DACMIX			(0x0 << 12)
#define RT5640_ADC_2_SRC_MASK			(0x3 << 10)
#define RT5640_ADC_2_SRC_SFT			10
#define RT5640_ADC_2_SRC_DMIC1			(0x0 << 10)
#define RT5640_ADC_2_SRC_DMIC2			(0x1 << 10)
#define RT5640_ADC_2_SRC_DACMIX			(0x2 << 10)
#define RT5640_M_ADC_R1				(0x1 << 6)
#define RT5640_M_ADC_R1_SFT			6
#define RT5640_M_ADC_R2				(0x1 << 5)
#define RT5640_M_ADC_R2_SFT			5

/* Mono ADC Mixer Control (0x28) */
#define RT5640_M_MONO_ADC_L1			(0x1 << 14)
#define RT5640_M_MONO_ADC_L1_SFT		14
#define RT5640_M_MONO_ADC_L2			(0x1 << 13)
#define RT5640_M_MONO_ADC_L2_SFT		13
#define RT5640_MONO_ADC_L1_SRC_MASK		(0x1 << 12)
#define RT5640_MONO_ADC_L1_SRC_SFT		12
#define RT5640_MONO_ADC_L1_SRC_DACMIXL		(0x0 << 12)
#define RT5640_MONO_ADC_L1_SRC_ADCL		(0x1 << 12)
#define RT5640_MONO_ADC_L2_SRC_MASK		(0x3 << 10)
#define RT5640_MONO_ADC_L2_SRC_SFT		10
#define RT5640_MONO_ADC_L2_SRC_DMIC_L1		(0x0 << 10)
#define RT5640_MONO_ADC_L2_SRC_DMIC_L2		(0x1 << 10)
#define RT5640_MONO_ADC_L2_SRC_DACMIXL		(0x2 << 10)
#define RT5640_M_MONO_ADC_R1			(0x1 << 6)
#define RT5640_M_MONO_ADC_R1_SFT		6
#define RT5640_M_MONO_ADC_R2			(0x1 << 5)
#define RT5640_M_MONO_ADC_R2_SFT		5
#define RT5640_MONO_ADC_R1_SRC_MASK		(0x1 << 4)
#define RT5640_MONO_ADC_R1_SRC_SFT		4
#define RT5640_MONO_ADC_R1_SRC_ADCR		(0x1 << 4)
#define RT5640_MONO_ADC_R1_SRC_DACMIXR		(0x0 << 4)
#define RT5640_MONO_ADC_R2_SRC_MASK		(0x3 << 2)
#define RT5640_MONO_ADC_R2_SRC_SFT		2
#define RT5640_MONO_ADC_R2_SRC_DMIC_R1		(0x0 << 2)
#define RT5640_MONO_ADC_R2_SRC_DMIC_R2		(0x1 << 2)
#define RT5640_MONO_ADC_R2_SRC_DACMIXR		(0x2 << 2)

/* ADC Mixer to DAC Mixer Control (0x29) */
#define RT5640_M_ADCMIX_L			(0x1 << 15)
#define RT5640_M_ADCMIX_L_SFT			15
#define RT5640_M_IF1_DAC_L			(0x1 << 14)
#define RT5640_M_IF1_DAC_L_SFT			14
#define RT5640_M_ADCMIX_R			(0x1 << 7)
#define RT5640_M_ADCMIX_R_SFT			7
#define RT5640_M_IF1_DAC_R			(0x1 << 6)
#define RT5640_M_IF1_DAC_R_SFT			6

/* Stereo DAC Mixer Control (0x2a) */
#define RT5640_M_DAC_L1				(0x1 << 14)
#define RT5640_M_DAC_L1_SFT			14
#define RT5640_DAC_L1_STO_L_VOL_MASK		(0x1 << 13)
#define RT5640_DAC_L1_STO_L_VOL_SFT		13
#define RT5640_M_DAC_L2				(0x1 << 12)
#define RT5640_M_DAC_L2_SFT			12
#define RT5640_DAC_L2_STO_L_VOL_MASK		(0x1 << 11)
#define RT5640_DAC_L2_STO_L_VOL_SFT		11
#define RT5640_M_ANC_DAC_L			(0x1 << 10)
#define RT5640_M_ANC_DAC_L_SFT			10
#define RT5640_M_DAC_R1				(0x1 << 6)
#define RT5640_M_DAC_R1_SFT			6
#define RT5640_DAC_R1_STO_R_VOL_MASK		(0x1 << 5)
#define RT5640_DAC_R1_STO_R_VOL_SFT		5
#define RT5640_M_DAC_R2				(0x1 << 4)
#define RT5640_M_DAC_R2_SFT			4
#define RT5640_DAC_R2_STO_R_VOL_MASK		(0x1 << 3)
#define RT5640_DAC_R2_STO_R_VOL_SFT		3
#define RT5640_M_ANC_DAC_R			(0x1 << 2)
#define RT5640_M_ANC_DAC_R_SFT		2

/* Mono DAC Mixer Control (0x2b) */
#define RT5640_M_DAC_L1_MONO_L			(0x1 << 14)
#define RT5640_M_DAC_L1_MONO_L_SFT		14
#define RT5640_DAC_L1_MONO_L_VOL_MASK		(0x1 << 13)
#define RT5640_DAC_L1_MONO_L_VOL_SFT		13
#define RT5640_M_DAC_L2_MONO_L			(0x1 << 12)
#define RT5640_M_DAC_L2_MONO_L_SFT		12
#define RT5640_DAC_L2_MONO_L_VOL_MASK		(0x1 << 11)
#define RT5640_DAC_L2_MONO_L_VOL_SFT		11
#define RT5640_M_DAC_R2_MONO_L			(0x1 << 10)
#define RT5640_M_DAC_R2_MONO_L_SFT		10
#define RT5640_DAC_R2_MONO_L_VOL_MASK		(0x1 << 9)
#define RT5640_DAC_R2_MONO_L_VOL_SFT		9
#define RT5640_M_DAC_R1_MONO_R			(0x1 << 6)
#define RT5640_M_DAC_R1_MONO_R_SFT		6
#define RT5640_DAC_R1_MONO_R_VOL_MASK		(0x1 << 5)
#define RT5640_DAC_R1_MONO_R_VOL_SFT		5
#define RT5640_M_DAC_R2_MONO_R			(0x1 << 4)
#define RT5640_M_DAC_R2_MONO_R_SFT		4
#define RT5640_DAC_R2_MONO_R_VOL_MASK		(0x1 << 3)
#define RT5640_DAC_R2_MONO_R_VOL_SFT		3
#define RT5640_M_DAC_L2_MONO_R			(0x1 << 2)
#define RT5640_M_DAC_L2_MONO_R_SFT		2
#define RT5640_DAC_L2_MONO_R_VOL_MASK		(0x1 << 1)
#define RT5640_DAC_L2_MONO_R_VOL_SFT		1

/* Digital Mixer Control (0x2c) */
#define RT5640_M_STO_L_DAC_L			(0x1 << 15)
#define RT5640_M_STO_L_DAC_L_SFT		15
#define RT5640_STO_L_DAC_L_VOL_MASK		(0x1 << 14)
#define RT5640_STO_L_DAC_L_VOL_SFT		14
#define RT5640_M_DAC_L2_DAC_L			(0x1 << 13)
#define RT5640_M_DAC_L2_DAC_L_SFT		13
#define RT5640_DAC_L2_DAC_L_VOL_MASK		(0x1 << 12)
#define RT5640_DAC_L2_DAC_L_VOL_SFT		12
#define RT5640_M_STO_R_DAC_R			(0x1 << 11)
#define RT5640_M_STO_R_DAC_R_SFT		11
#define RT5640_STO_R_DAC_R_VOL_MASK		(0x1 << 10)
#define RT5640_STO_R_DAC_R_VOL_SFT		10
#define RT5640_M_DAC_R2_DAC_R			(0x1 << 9)
#define RT5640_M_DAC_R2_DAC_R_SFT		9
#define RT5640_DAC_R2_DAC_R_VOL_MASK		(0x1 << 8)
#define RT5640_DAC_R2_DAC_R_VOL_SFT		8

/* DSP Path Control 1 (0x2d) */
#define RT5640_RXDP_SRC_MASK			(0x1 << 15)
#define RT5640_RXDP_SRC_SFT			15
#define RT5640_RXDP_SRC_NOR			(0x0 << 15)
#define RT5640_RXDP_SRC_DIV3			(0x1 << 15)
#define RT5640_TXDP_SRC_MASK			(0x1 << 14)
#define RT5640_TXDP_SRC_SFT			14
#define RT5640_TXDP_SRC_NOR			(0x0 << 14)
#define RT5640_TXDP_SRC_DIV3			(0x1 << 14)

/* DSP Path Control 2 (0x2e) */
#define RT5640_DAC_L2_SEL_MASK			(0x3 << 14)
#define RT5640_DAC_L2_SEL_SFT			14
#define RT5640_DAC_L2_SEL_IF2			(0x0 << 14)
#define RT5640_DAC_L2_SEL_IF3			(0x1 << 14)
#define RT5640_DAC_L2_SEL_TXDC			(0x2 << 14)
#define RT5640_DAC_L2_SEL_BASS			(0x3 << 14)
#define RT5640_DAC_R2_SEL_MASK			(0x3 << 12)
#define RT5640_DAC_R2_SEL_SFT			12
#define RT5640_DAC_R2_SEL_IF2			(0x0 << 12)
#define RT5640_DAC_R2_SEL_IF3			(0x1 << 12)
#define RT5640_DAC_R2_SEL_TXDC			(0x2 << 12)
#define RT5640_IF2_ADC_L_SEL_MASK		(0x1 << 11)
#define RT5640_IF2_ADC_L_SEL_SFT		11
#define RT5640_IF2_ADC_L_SEL_TXDP		(0x0 << 11)
#define RT5640_IF2_ADC_L_SEL_PASS		(0x1 << 11)
#define RT5640_IF2_ADC_R_SEL_MASK		(0x1 << 10)
#define RT5640_IF2_ADC_R_SEL_SFT		10
#define RT5640_IF2_ADC_R_SEL_TXDP		(0x0 << 10)
#define RT5640_IF2_ADC_R_SEL_PASS		(0x1 << 10)
#define RT5640_RXDC_SEL_MASK			(0x3 << 8)
#define RT5640_RXDC_SEL_SFT			8
#define RT5640_RXDC_SEL_NOR			(0x0 << 8)
#define RT5640_RXDC_SEL_L2R			(0x1 << 8)
#define RT5640_RXDC_SEL_R2L			(0x2 << 8)
#define RT5640_RXDC_SEL_SWAP			(0x3 << 8)
#define RT5640_RXDP_SEL_MASK			(0x3 << 6)
#define RT5640_RXDP_SEL_SFT			6
#define RT5640_RXDP_SEL_NOR			(0x0 << 6)
#define RT5640_RXDP_SEL_L2R			(0x1 << 6)
#define RT5640_RXDP_SEL_R2L			(0x2 << 6)
#define RT5640_RXDP_SEL_SWAP			(0x3 << 6)
#define RT5640_TXDC_SEL_MASK			(0x3 << 4)
#define RT5640_TXDC_SEL_SFT			4
#define RT5640_TXDC_SEL_NOR			(0x0 << 4)
#define RT5640_TXDC_SEL_L2R			(0x1 << 4)
#define RT5640_TXDC_SEL_R2L			(0x2 << 4)
#define RT5640_TXDC_SEL_SWAP			(0x3 << 4)
#define RT5640_TXDP_SEL_MASK			(0x3 << 2)
#define RT5640_TXDP_SEL_SFT			2
#define RT5640_TXDP_SEL_NOR			(0x0 << 2)
#define RT5640_TXDP_SEL_L2R			(0x1 << 2)
#define RT5640_TXDP_SEL_R2L			(0x2 << 2)
#define RT5640_TRXDP_SEL_SWAP			(0x3 << 2)

/* Digital Interface Data Control (0x2f) */
#define RT5640_IF1_DAC_SEL_MASK			(0x3 << 14)
#define RT5640_IF1_DAC_SEL_SFT			14
#define RT5640_IF1_DAC_SEL_NOR			(0x0 << 14)
#define RT5640_IF1_DAC_SEL_L2R			(0x1 << 14)
#define RT5640_IF1_DAC_SEL_R2L			(0x2 << 14)
#define RT5640_IF1_DAC_SEL_SWAP			(0x3 << 14)
#define RT5640_IF1_ADC_SEL_MASK			(0x3 << 12)
#define RT5640_IF1_ADC_SEL_SFT			12
#define RT5640_IF1_ADC_SEL_NOR			(0x0 << 12)
#define RT5640_IF1_ADC_SEL_L2R			(0x1 << 12)
#define RT5640_IF1_ADC_SEL_R2L			(0x2 << 12)
#define RT5640_IF1_ADC_SEL_SWAP			(0x3 << 12)
#define RT5640_IF2_DAC_SEL_MASK			(0x3 << 10)
#define RT5640_IF2_DAC_SEL_SFT			10
#define RT5640_IF2_DAC_SEL_NOR			(0x0 << 10)
#define RT5640_IF2_DAC_SEL_L2R			(0x1 << 10)
#define RT5640_IF2_DAC_SEL_R2L			(0x2 << 10)
#define RT5640_IF2_DAC_SEL_SWAP			(0x3 << 10)
#define RT5640_IF2_ADC_SEL_MASK			(0x3 << 8)
#define RT5640_IF2_ADC_SEL_SFT			8
#define RT5640_IF2_ADC_SEL_NOR			(0x0 << 8)
#define RT5640_IF2_ADC_SEL_L2R			(0x1 << 8)
#define RT5640_IF2_ADC_SEL_R2L			(0x2 << 8)
#define RT5640_IF2_ADC_SEL_SWAP			(0x3 << 8)
#define RT5640_IF3_DAC_SEL_MASK			(0x3 << 6)
#define RT5640_IF3_DAC_SEL_SFT			6
#define RT5640_IF3_DAC_SEL_NOR			(0x0 << 6)
#define RT5640_IF3_DAC_SEL_L2R			(0x1 << 6)
#define RT5640_IF3_DAC_SEL_R2L			(0x2 << 6)
#define RT5640_IF3_DAC_SEL_SWAP			(0x3 << 6)
#define RT5640_IF3_ADC_SEL_MASK			(0x3 << 4)
#define RT5640_IF3_ADC_SEL_SFT			4
#define RT5640_IF3_ADC_SEL_NOR			(0x0 << 4)
#define RT5640_IF3_ADC_SEL_L2R			(0x1 << 4)
#define RT5640_IF3_ADC_SEL_R2L			(0x2 << 4)
#define RT5640_IF3_ADC_SEL_SWAP			(0x3 << 4)

/* REC Left Mixer Control 1 (0x3b) */
#define RT5640_G_HP_L_RM_L_MASK			(0x7 << 13)
#define RT5640_G_HP_L_RM_L_SFT			13
#define RT5640_G_IN_L_RM_L_MASK			(0x7 << 10)
#define RT5640_G_IN_L_RM_L_SFT			10
#define RT5640_G_BST4_RM_L_MASK			(0x7 << 7)
#define RT5640_G_BST4_RM_L_SFT			7
#define RT5640_G_BST3_RM_L_MASK			(0x7 << 4)
#define RT5640_G_BST3_RM_L_SFT			4
#define RT5640_G_BST2_RM_L_MASK			(0x7 << 1)
#define RT5640_G_BST2_RM_L_SFT			1

/* REC Left Mixer Control 2 (0x3c) */
#define RT5640_G_BST1_RM_L_MASK			(0x7 << 13)
#define RT5640_G_BST1_RM_L_SFT			13
#define RT5640_G_OM_L_RM_L_MASK			(0x7 << 10)
#define RT5640_G_OM_L_RM_L_SFT			10
#define RT5640_M_HP_L_RM_L			(0x1 << 6)
#define RT5640_M_HP_L_RM_L_SFT			6
#define RT5640_M_IN_L_RM_L			(0x1 << 5)
#define RT5640_M_IN_L_RM_L_SFT			5
#define RT5640_M_BST4_RM_L			(0x1 << 4)
#define RT5640_M_BST4_RM_L_SFT			4
#define RT5640_M_BST3_RM_L			(0x1 << 3)
#define RT5640_M_BST3_RM_L_SFT			3
#define RT5640_M_BST2_RM_L			(0x1 << 2)
#define RT5640_M_BST2_RM_L_SFT			2
#define RT5640_M_BST1_RM_L			(0x1 << 1)
#define RT5640_M_BST1_RM_L_SFT			1
#define RT5640_M_OM_L_RM_L			(0x1)
#define RT5640_M_OM_L_RM_L_SFT			0

/* REC Right Mixer Control 1 (0x3d) */
#define RT5640_G_HP_R_RM_R_MASK			(0x7 << 13)
#define RT5640_G_HP_R_RM_R_SFT			13
#define RT5640_G_IN_R_RM_R_MASK			(0x7 << 10)
#define RT5640_G_IN_R_RM_R_SFT			10
#define RT5640_G_BST4_RM_R_MASK			(0x7 << 7)
#define RT5640_G_BST4_RM_R_SFT			7
#define RT5640_G_BST3_RM_R_MASK			(0x7 << 4)
#define RT5640_G_BST3_RM_R_SFT			4
#define RT5640_G_BST2_RM_R_MASK			(0x7 << 1)
#define RT5640_G_BST2_RM_R_SFT			1

/* REC Right Mixer Control 2 (0x3e) */
#define RT5640_G_BST1_RM_R_MASK			(0x7 << 13)
#define RT5640_G_BST1_RM_R_SFT			13
#define RT5640_G_OM_R_RM_R_MASK			(0x7 << 10)
#define RT5640_G_OM_R_RM_R_SFT			10
#define RT5640_M_HP_R_RM_R			(0x1 << 6)
#define RT5640_M_HP_R_RM_R_SFT			6
#define RT5640_M_IN_R_RM_R			(0x1 << 5)
#define RT5640_M_IN_R_RM_R_SFT			5
#define RT5640_M_BST4_RM_R			(0x1 << 4)
#define RT5640_M_BST4_RM_R_SFT			4
#define RT5640_M_BST3_RM_R			(0x1 << 3)
#define RT5640_M_BST3_RM_R_SFT			3
#define RT5640_M_BST2_RM_R			(0x1 << 2)
#define RT5640_M_BST2_RM_R_SFT			2
#define RT5640_M_BST1_RM_R			(0x1 << 1)
#define RT5640_M_BST1_RM_R_SFT			1
#define RT5640_M_OM_R_RM_R			(0x1)
#define RT5640_M_OM_R_RM_R_SFT			0

/* HPMIX Control (0x45) */
#define RT5640_M_DAC2_HM			(0x1 << 15)
#define RT5640_M_DAC2_HM_SFT			15
#define RT5640_M_DAC1_HM			(0x1 << 14)
#define RT5640_M_DAC1_HM_SFT			14
#define RT5640_M_HPVOL_HM			(0x1 << 13)
#define RT5640_M_HPVOL_HM_SFT			13
#define RT5640_G_HPOMIX_MASK			(0x1 << 12)
#define RT5640_G_HPOMIX_SFT			12

/* SPK Left Mixer Control (0x46) */
#define RT5640_G_RM_L_SM_L_MASK			(0x3 << 14)
#define RT5640_G_RM_L_SM_L_SFT			14
#define RT5640_G_IN_L_SM_L_MASK			(0x3 << 12)
#define RT5640_G_IN_L_SM_L_SFT			12
#define RT5640_G_DAC_L1_SM_L_MASK		(0x3 << 10)
#define RT5640_G_DAC_L1_SM_L_SFT		10
#define RT5640_G_DAC_L2_SM_L_MASK		(0x3 << 8)
#define RT5640_G_DAC_L2_SM_L_SFT		8
#define RT5640_G_OM_L_SM_L_MASK			(0x3 << 6)
#define RT5640_G_OM_L_SM_L_SFT			6
#define RT5640_M_RM_L_SM_L			(0x1 << 5)
#define RT5640_M_RM_L_SM_L_SFT			5
#define RT5640_M_IN_L_SM_L			(0x1 << 4)
#define RT5640_M_IN_L_SM_L_SFT			4
#define RT5640_M_DAC_L1_SM_L			(0x1 << 3)
#define RT5640_M_DAC_L1_SM_L_SFT		3
#define RT5640_M_DAC_L2_SM_L			(0x1 << 2)
#define RT5640_M_DAC_L2_SM_L_SFT		2
#define RT5640_M_OM_L_SM_L			(0x1 << 1)
#define RT5640_M_OM_L_SM_L_SFT		1

/* SPK Right Mixer Control (0x47) */
#define RT5640_G_RM_R_SM_R_MASK			(0x3 << 14)
#define RT5640_G_RM_R_SM_R_SFT			14
#define RT5640_G_IN_R_SM_R_MASK			(0x3 << 12)
#define RT5640_G_IN_R_SM_R_SFT			12
#define RT5640_G_DAC_R1_SM_R_MASK		(0x3 << 10)
#define RT5640_G_DAC_R1_SM_R_SFT		10
#define RT5640_G_DAC_R2_SM_R_MASK		(0x3 << 8)
#define RT5640_G_DAC_R2_SM_R_SFT		8
#define RT5640_G_OM_R_SM_R_MASK			(0x3 << 6)
#define RT5640_G_OM_R_SM_R_SFT			6
#define RT5640_M_RM_R_SM_R			(0x1 << 5)
#define RT5640_M_RM_R_SM_R_SFT			5
#define RT5640_M_IN_R_SM_R			(0x1 << 4)
#define RT5640_M_IN_R_SM_R_SFT			4
#define RT5640_M_DAC_R1_SM_R			(0x1 << 3)
#define RT5640_M_DAC_R1_SM_R_SFT		3
#define RT5640_M_DAC_R2_SM_R			(0x1 << 2)
#define RT5640_M_DAC_R2_SM_R_SFT		2
#define RT5640_M_OM_R_SM_R			(0x1 << 1)
#define RT5640_M_OM_R_SM_R_SFT			1

/* SPOLMIX Control (0x48) */
#define RT5640_M_DAC_R1_SPM_L			(0x1 << 15)
#define RT5640_M_DAC_R1_SPM_L_SFT		15
#define RT5640_M_DAC_L1_SPM_L			(0x1 << 14)
#define RT5640_M_DAC_L1_SPM_L_SFT		14
#define RT5640_M_SV_R_SPM_L			(0x1 << 13)
#define RT5640_M_SV_R_SPM_L_SFT			13
#define RT5640_M_SV_L_SPM_L			(0x1 << 12)
#define RT5640_M_SV_L_SPM_L_SFT			12
#define RT5640_M_BST1_SPM_L			(0x1 << 11)
#define RT5640_M_BST1_SPM_L_SFT			11

/* SPORMIX Control (0x49) */
#define RT5640_M_DAC_R1_SPM_R			(0x1 << 13)
#define RT5640_M_DAC_R1_SPM_R_SFT		13
#define RT5640_M_SV_R_SPM_R			(0x1 << 12)
#define RT5640_M_SV_R_SPM_R_SFT			12
#define RT5640_M_BST1_SPM_R			(0x1 << 11)
#define RT5640_M_BST1_SPM_R_SFT			11

/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
#define RT5640_SPO_CLSD_RATIO_MASK		(0x7)
#define RT5640_SPO_CLSD_RATIO_SFT		0

/* Mono Output Mixer Control (0x4c) */
#define RT5640_M_DAC_R2_MM			(0x1 << 15)
#define RT5640_M_DAC_R2_MM_SFT			15
#define RT5640_M_DAC_L2_MM			(0x1 << 14)
#define RT5640_M_DAC_L2_MM_SFT			14
#define RT5640_M_OV_R_MM			(0x1 << 13)
#define RT5640_M_OV_R_MM_SFT			13
#define RT5640_M_OV_L_MM			(0x1 << 12)
#define RT5640_M_OV_L_MM_SFT			12
#define RT5640_M_BST1_MM			(0x1 << 11)
#define RT5640_M_BST1_MM_SFT			11
#define RT5640_G_MONOMIX_MASK			(0x1 << 10)
#define RT5640_G_MONOMIX_SFT			10

/* Output Left Mixer Control 1 (0x4d) */
#define RT5640_G_BST3_OM_L_MASK			(0x7 << 13)
#define RT5640_G_BST3_OM_L_SFT			13
#define RT5640_G_BST2_OM_L_MASK			(0x7 << 10)
#define RT5640_G_BST2_OM_L_SFT			10
#define RT5640_G_BST1_OM_L_MASK			(0x7 << 7)
#define RT5640_G_BST1_OM_L_SFT			7
#define RT5640_G_IN_L_OM_L_MASK			(0x7 << 4)
#define RT5640_G_IN_L_OM_L_SFT			4
#define RT5640_G_RM_L_OM_L_MASK			(0x7 << 1)
#define RT5640_G_RM_L_OM_L_SFT			1

/* Output Left Mixer Control 2 (0x4e) */
#define RT5640_G_DAC_R2_OM_L_MASK		(0x7 << 13)
#define RT5640_G_DAC_R2_OM_L_SFT		13
#define RT5640_G_DAC_L2_OM_L_MASK		(0x7 << 10)
#define RT5640_G_DAC_L2_OM_L_SFT		10
#define RT5640_G_DAC_L1_OM_L_MASK		(0x7 << 7)
#define RT5640_G_DAC_L1_OM_L_SFT		7

/* Output Left Mixer Control 3 (0x4f) */
#define RT5640_M_SM_L_OM_L			(0x1 << 8)
#define RT5640_M_SM_L_OM_L_SFT			8
#define RT5640_M_BST3_OM_L			(0x1 << 7)
#define RT5640_M_BST3_OM_L_SFT			7
#define RT5640_M_BST2_OM_L			(0x1 << 6)
#define RT5640_M_BST2_OM_L_SFT			6
#define RT5640_M_BST1_OM_L			(0x1 << 5)
#define RT5640_M_BST1_OM_L_SFT			5
#define RT5640_M_IN_L_OM_L			(0x1 << 4)
#define RT5640_M_IN_L_OM_L_SFT			4
#define RT5640_M_RM_L_OM_L			(0x1 << 3)
#define RT5640_M_RM_L_OM_L_SFT			3
#define RT5640_M_DAC_R2_OM_L			(0x1 << 2)
#define RT5640_M_DAC_R2_OM_L_SFT		2
#define RT5640_M_DAC_L2_OM_L			(0x1 << 1)
#define RT5640_M_DAC_L2_OM_L_SFT		1
#define RT5640_M_DAC_L1_OM_L			(0x1)
#define RT5640_M_DAC_L1_OM_L_SFT		0

/* Output Right Mixer Control 1 (0x50) */
#define RT5640_G_BST4_OM_R_MASK			(0x7 << 13)
#define RT5640_G_BST4_OM_R_SFT			13
#define RT5640_G_BST2_OM_R_MASK			(0x7 << 10)
#define RT5640_G_BST2_OM_R_SFT			10
#define RT5640_G_BST1_OM_R_MASK			(0x7 << 7)
#define RT5640_G_BST1_OM_R_SFT			7
#define RT5640_G_IN_R_OM_R_MASK			(0x7 << 4)
#define RT5640_G_IN_R_OM_R_SFT			4
#define RT5640_G_RM_R_OM_R_MASK			(0x7 << 1)
#define RT5640_G_RM_R_OM_R_SFT			1

/* Output Right Mixer Control 2 (0x51) */
#define RT5640_G_DAC_L2_OM_R_MASK		(0x7 << 13)
#define RT5640_G_DAC_L2_OM_R_SFT		13
#define RT5640_G_DAC_R2_OM_R_MASK		(0x7 << 10)
#define RT5640_G_DAC_R2_OM_R_SFT		10
#define RT5640_G_DAC_R1_OM_R_MASK		(0x7 << 7)
#define RT5640_G_DAC_R1_OM_R_SFT		7

/* Output Right Mixer Control 3 (0x52) */
#define RT5640_M_SM_L_OM_R			(0x1 << 8)
#define RT5640_M_SM_L_OM_R_SFT			8
#define RT5640_M_BST4_OM_R			(0x1 << 7)
#define RT5640_M_BST4_OM_R_SFT			7
#define RT5640_M_BST2_OM_R			(0x1 << 6)
#define RT5640_M_BST2_OM_R_SFT			6
#define RT5640_M_BST1_OM_R			(0x1 << 5)
#define RT5640_M_BST1_OM_R_SFT			5
#define RT5640_M_IN_R_OM_R			(0x1 << 4)
#define RT5640_M_IN_R_OM_R_SFT			4
#define RT5640_M_RM_R_OM_R			(0x1 << 3)
#define RT5640_M_RM_R_OM_R_SFT			3
#define RT5640_M_DAC_L2_OM_R			(0x1 << 2)
#define RT5640_M_DAC_L2_OM_R_SFT		2
#define RT5640_M_DAC_R2_OM_R			(0x1 << 1)
#define RT5640_M_DAC_R2_OM_R_SFT		1
#define RT5640_M_DAC_R1_OM_R			(0x1)
#define RT5640_M_DAC_R1_OM_R_SFT		0

/* LOUT Mixer Control (0x53) */
#define RT5640_M_DAC_L1_LM			(0x1 << 15)
#define RT5640_M_DAC_L1_LM_SFT			15
#define RT5640_M_DAC_R1_LM			(0x1 << 14)
#define RT5640_M_DAC_R1_LM_SFT			14
#define RT5640_M_OV_L_LM			(0x1 << 13)
#define RT5640_M_OV_L_LM_SFT			13
#define RT5640_M_OV_R_LM			(0x1 << 12)
#define RT5640_M_OV_R_LM_SFT			12
#define RT5640_G_LOUTMIX_MASK			(0x1 << 11)
#define RT5640_G_LOUTMIX_SFT			11

/* Power Management for Digital 1 (0x61) */
#define RT5640_PWR_I2S1				(0x1 << 15)
#define RT5640_PWR_I2S1_BIT			15
#define RT5640_PWR_I2S2				(0x1 << 14)
#define RT5640_PWR_I2S2_BIT			14
#define RT5640_PWR_DAC_L1			(0x1 << 12)
#define RT5640_PWR_DAC_L1_BIT			12
#define RT5640_PWR_DAC_R1			(0x1 << 11)
#define RT5640_PWR_DAC_R1_BIT			11
#define RT5640_PWR_DAC_L2			(0x1 << 7)
#define RT5640_PWR_DAC_L2_BIT			7
#define RT5640_PWR_DAC_R2			(0x1 << 6)
#define RT5640_PWR_DAC_R2_BIT			6
#define RT5640_PWR_ADC_L			(0x1 << 2)
#define RT5640_PWR_ADC_L_BIT			2
#define RT5640_PWR_ADC_R			(0x1 << 1)
#define RT5640_PWR_ADC_R_BIT			1
#define RT5640_PWR_CLS_D			(0x1)
#define RT5640_PWR_CLS_D_BIT			0

/* Power Management for Digital 2 (0x62) */
#define RT5640_PWR_ADC_SF			(0x1 << 15)
#define RT5640_PWR_ADC_SF_BIT			15
#define RT5640_PWR_ADC_MF_L			(0x1 << 14)
#define RT5640_PWR_ADC_MF_L_BIT			14
#define RT5640_PWR_ADC_MF_R			(0x1 << 13)
#define RT5640_PWR_ADC_MF_R_BIT			13
#define RT5640_PWR_I2S_DSP			(0x1 << 12)
#define RT5640_PWR_I2S_DSP_BIT			12

/* Power Management for Analog 1 (0x63) */
#define RT5640_PWR_VREF1			(0x1 << 15)
#define RT5640_PWR_VREF1_BIT			15
#define RT5640_PWR_FV1				(0x1 << 14)
#define RT5640_PWR_FV1_BIT			14
#define RT5640_PWR_MB				(0x1 << 13)
#define RT5640_PWR_MB_BIT			13
#define RT5640_PWR_LM				(0x1 << 12)
#define RT5640_PWR_LM_BIT			12
#define RT5640_PWR_BG				(0x1 << 11)
#define RT5640_PWR_BG_BIT			11
#define RT5640_PWR_MM				(0x1 << 10)
#define RT5640_PWR_MM_BIT			10
#define RT5640_PWR_MA				(0x1 << 8)
#define RT5640_PWR_MA_BIT			8
#define RT5640_PWR_HP_L				(0x1 << 7)
#define RT5640_PWR_HP_L_BIT			7
#define RT5640_PWR_HP_R				(0x1 << 6)
#define RT5640_PWR_HP_R_BIT			6
#define RT5640_PWR_HA				(0x1 << 5)
#define RT5640_PWR_HA_BIT			5
#define RT5640_PWR_VREF2			(0x1 << 4)
#define RT5640_PWR_VREF2_BIT			4
#define RT5640_PWR_FV2				(0x1 << 3)
#define RT5640_PWR_FV2_BIT			3
#define RT5640_PWR_LDO2				(0x1 << 2)
#define RT5640_PWR_LDO2_BIT			2

/* Power Management for Analog 2 (0x64) */
#define RT5640_PWR_BST1				(0x1 << 15)
#define RT5640_PWR_BST1_BIT			15
#define RT5640_PWR_BST2				(0x1 << 14)
#define RT5640_PWR_BST2_BIT			14
#define RT5640_PWR_BST3				(0x1 << 13)
#define RT5640_PWR_BST3_BIT			13
#define RT5640_PWR_BST4				(0x1 << 12)
#define RT5640_PWR_BST4_BIT			12
#define RT5640_PWR_MB1				(0x1 << 11)
#define RT5640_PWR_MB1_BIT			11
#define RT5640_PWR_PLL				(0x1 << 9)
#define RT5640_PWR_PLL_BIT			9

/* Power Management for Mixer (0x65) */
#define RT5640_PWR_OM_L				(0x1 << 15)
#define RT5640_PWR_OM_L_BIT			15
#define RT5640_PWR_OM_R				(0x1 << 14)
#define RT5640_PWR_OM_R_BIT			14
#define RT5640_PWR_SM_L				(0x1 << 13)
#define RT5640_PWR_SM_L_BIT			13
#define RT5640_PWR_SM_R				(0x1 << 12)
#define RT5640_PWR_SM_R_BIT			12
#define RT5640_PWR_RM_L				(0x1 << 11)
#define RT5640_PWR_RM_L_BIT			11
#define RT5640_PWR_RM_R				(0x1 << 10)
#define RT5640_PWR_RM_R_BIT			10

/* Power Management for Volume (0x66) */
#define RT5640_PWR_SV_L				(0x1 << 15)
#define RT5640_PWR_SV_L_BIT			15
#define RT5640_PWR_SV_R				(0x1 << 14)
#define RT5640_PWR_SV_R_BIT			14
#define RT5640_PWR_OV_L				(0x1 << 13)
#define RT5640_PWR_OV_L_BIT			13
#define RT5640_PWR_OV_R				(0x1 << 12)
#define RT5640_PWR_OV_R_BIT			12
#define RT5640_PWR_HV_L				(0x1 << 11)
#define RT5640_PWR_HV_L_BIT			11
#define RT5640_PWR_HV_R				(0x1 << 10)
#define RT5640_PWR_HV_R_BIT			10
#define RT5640_PWR_IN_L				(0x1 << 9)
#define RT5640_PWR_IN_L_BIT			9
#define RT5640_PWR_IN_R				(0x1 << 8)
#define RT5640_PWR_IN_R_BIT			8

/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
#define RT5640_I2S_MS_MASK			(0x1 << 15)
#define RT5640_I2S_MS_SFT			15
#define RT5640_I2S_MS_M				(0x0 << 15)
#define RT5640_I2S_MS_S				(0x1 << 15)
#define RT5640_I2S_IF_MASK			(0x7 << 12)
#define RT5640_I2S_IF_SFT			12
#define RT5640_I2S_O_CP_MASK			(0x3 << 10)
#define RT5640_I2S_O_CP_SFT			10
#define RT5640_I2S_O_CP_OFF			(0x0 << 10)
#define RT5640_I2S_O_CP_U_LAW			(0x1 << 10)
#define RT5640_I2S_O_CP_A_LAW			(0x2 << 10)
#define RT5640_I2S_I_CP_MASK			(0x3 << 8)
#define RT5640_I2S_I_CP_SFT			8
#define RT5640_I2S_I_CP_OFF			(0x0 << 8)
#define RT5640_I2S_I_CP_U_LAW			(0x1 << 8)
#define RT5640_I2S_I_CP_A_LAW			(0x2 << 8)
#define RT5640_I2S_BP_MASK			(0x1 << 7)
#define RT5640_I2S_BP_SFT			7
#define RT5640_I2S_BP_NOR			(0x0 << 7)
#define RT5640_I2S_BP_INV			(0x1 << 7)
#define RT5640_I2S_DL_MASK			(0x3 << 2)
#define RT5640_I2S_DL_SFT			2
#define RT5640_I2S_DL_16			(0x0 << 2)
#define RT5640_I2S_DL_20			(0x1 << 2)
#define RT5640_I2S_DL_24			(0x2 << 2)
#define RT5640_I2S_DL_8				(0x3 << 2)
#define RT5640_I2S_DF_MASK			(0x3)
#define RT5640_I2S_DF_SFT			0
#define RT5640_I2S_DF_I2S			(0x0)
#define RT5640_I2S_DF_LEFT			(0x1)
#define RT5640_I2S_DF_PCM_A			(0x2)
#define RT5640_I2S_DF_PCM_B			(0x3)

/* I2S2 Audio Serial Data Port Control (0x71) */
#define RT5640_I2S2_SDI_MASK			(0x1 << 6)
#define RT5640_I2S2_SDI_SFT			6
#define RT5640_I2S2_SDI_I2S1			(0x0 << 6)
#define RT5640_I2S2_SDI_I2S2			(0x1 << 6)

/* ADC/DAC Clock Control 1 (0x73) */
#define RT5640_I2S_BCLK_MS1_MASK		(0x1 << 15)
#define RT5640_I2S_BCLK_MS1_SFT			15
#define RT5640_I2S_BCLK_MS1_32			(0x0 << 15)
#define RT5640_I2S_BCLK_MS1_64			(0x1 << 15)
#define RT5640_I2S_PD1_MASK			(0x7 << 12)
#define RT5640_I2S_PD1_SFT			12
#define RT5640_I2S_PD1_1			(0x0 << 12)
#define RT5640_I2S_PD1_2			(0x1 << 12)
#define RT5640_I2S_PD1_3			(0x2 << 12)
#define RT5640_I2S_PD1_4			(0x3 << 12)
#define RT5640_I2S_PD1_6			(0x4 << 12)
#define RT5640_I2S_PD1_8			(0x5 << 12)
#define RT5640_I2S_PD1_12			(0x6 << 12)
#define RT5640_I2S_PD1_16			(0x7 << 12)
#define RT5640_I2S_BCLK_MS2_MASK		(0x1 << 11)
#define RT5640_I2S_BCLK_MS2_SFT			11
#define RT5640_I2S_BCLK_MS2_32			(0x0 << 11)
#define RT5640_I2S_BCLK_MS2_64			(0x1 << 11)
#define RT5640_I2S_PD2_MASK			(0x7 << 8)
#define RT5640_I2S_PD2_SFT			8
#define RT5640_I2S_PD2_1			(0x0 << 8)
#define RT5640_I2S_PD2_2			(0x1 << 8)
#define RT5640_I2S_PD2_3			(0x2 << 8)
#define RT5640_I2S_PD2_4			(0x3 << 8)
#define RT5640_I2S_PD2_6			(0x4 << 8)
#define RT5640_I2S_PD2_8			(0x5 << 8)
#define RT5640_I2S_PD2_12			(0x6 << 8)
#define RT5640_I2S_PD2_16			(0x7 << 8)
#define RT5640_I2S_BCLK_MS3_MASK		(0x1 << 7)
#define RT5640_I2S_BCLK_MS3_SFT			7
#define RT5640_I2S_BCLK_MS3_32			(0x0 << 7)
#define RT5640_I2S_BCLK_MS3_64			(0x1 << 7)
#define RT5640_I2S_PD3_MASK			(0x7 << 4)
#define RT5640_I2S_PD3_SFT			4
#define RT5640_I2S_PD3_1			(0x0 << 4)
#define RT5640_I2S_PD3_2			(0x1 << 4)
#define RT5640_I2S_PD3_3			(0x2 << 4)
#define RT5640_I2S_PD3_4			(0x3 << 4)
#define RT5640_I2S_PD3_6			(0x4 << 4)
#define RT5640_I2S_PD3_8			(0x5 << 4)
#define RT5640_I2S_PD3_12			(0x6 << 4)
#define RT5640_I2S_PD3_16			(0x7 << 4)
#define RT5640_DAC_OSR_MASK			(0x3 << 2)
#define RT5640_DAC_OSR_SFT			2
#define RT5640_DAC_OSR_128			(0x0 << 2)
#define RT5640_DAC_OSR_64			(0x1 << 2)
#define RT5640_DAC_OSR_32			(0x2 << 2)
#define RT5640_DAC_OSR_16			(0x3 << 2)
#define RT5640_ADC_OSR_MASK			(0x3)
#define RT5640_ADC_OSR_SFT			0
#define RT5640_ADC_OSR_128			(0x0)
#define RT5640_ADC_OSR_64			(0x1)
#define RT5640_ADC_OSR_32			(0x2)
#define RT5640_ADC_OSR_16			(0x3)

/* ADC/DAC Clock Control 2 (0x74) */
#define RT5640_DAC_L_OSR_MASK			(0x3 << 14)
#define RT5640_DAC_L_OSR_SFT			14
#define RT5640_DAC_L_OSR_128			(0x0 << 14)
#define RT5640_DAC_L_OSR_64			(0x1 << 14)
#define RT5640_DAC_L_OSR_32			(0x2 << 14)
#define RT5640_DAC_L_OSR_16			(0x3 << 14)
#define RT5640_ADC_R_OSR_MASK			(0x3 << 12)
#define RT5640_ADC_R_OSR_SFT			12
#define RT5640_ADC_R_OSR_128			(0x0 << 12)
#define RT5640_ADC_R_OSR_64			(0x1 << 12)
#define RT5640_ADC_R_OSR_32			(0x2 << 12)
#define RT5640_ADC_R_OSR_16			(0x3 << 12)
#define RT5640_DAHPF_EN				(0x1 << 11)
#define RT5640_DAHPF_EN_SFT			11
#define RT5640_ADHPF_EN				(0x1 << 10)
#define RT5640_ADHPF_EN_SFT			10

/* Digital Microphone Control (0x75) */
#define RT5640_DMIC_1_EN_MASK			(0x1 << 15)
#define RT5640_DMIC_1_EN_SFT			15
#define RT5640_DMIC_1_DIS			(0x0 << 15)
#define RT5640_DMIC_1_EN			(0x1 << 15)
#define RT5640_DMIC_2_EN_MASK			(0x1 << 14)
#define RT5640_DMIC_2_EN_SFT			14
#define RT5640_DMIC_2_DIS			(0x0 << 14)
#define RT5640_DMIC_2_EN			(0x1 << 14)
#define RT5640_DMIC_1L_LH_MASK			(0x1 << 13)
#define RT5640_DMIC_1L_LH_SFT			13
#define RT5640_DMIC_1L_LH_FALLING		(0x0 << 13)
#define RT5640_DMIC_1L_LH_RISING		(0x1 << 13)
#define RT5640_DMIC_1R_LH_MASK			(0x1 << 12)
#define RT5640_DMIC_1R_LH_SFT			12
#define RT5640_DMIC_1R_LH_FALLING		(0x0 << 12)
#define RT5640_DMIC_1R_LH_RISING		(0x1 << 12)
#define RT5640_DMIC_1_DP_MASK			(0x1 << 11)
#define RT5640_DMIC_1_DP_SFT			11
#define RT5640_DMIC_1_DP_GPIO3			(0x0 << 11)
#define RT5640_DMIC_1_DP_IN1P			(0x1 << 11)
#define RT5640_DMIC_2_DP_MASK			(0x1 << 10)
#define RT5640_DMIC_2_DP_SFT			10
#define RT5640_DMIC_2_DP_GPIO4			(0x0 << 10)
#define RT5640_DMIC_2_DP_IN1N			(0x1 << 10)
#define RT5640_DMIC_2L_LH_MASK			(0x1 << 9)
#define RT5640_DMIC_2L_LH_SFT			9
#define RT5640_DMIC_2L_LH_FALLING		(0x0 << 9)
#define RT5640_DMIC_2L_LH_RISING		(0x1 << 9)
#define RT5640_DMIC_2R_LH_MASK			(0x1 << 8)
#define RT5640_DMIC_2R_LH_SFT			8
#define RT5640_DMIC_2R_LH_FALLING		(0x0 << 8)
#define RT5640_DMIC_2R_LH_RISING		(0x1 << 8)
#define RT5640_DMIC_CLK_MASK			(0x7 << 5)
#define RT5640_DMIC_CLK_SFT			5

/* Global Clock Control (0x80) */
#define RT5640_SCLK_SRC_MASK			(0x3 << 14)
#define RT5640_SCLK_SRC_SFT			14
#define RT5640_SCLK_SRC_MCLK			(0x0 << 14)
#define RT5640_SCLK_SRC_PLL1			(0x1 << 14)
#define RT5640_PLL1_SRC_MASK			(0x3 << 12)
#define RT5640_PLL1_SRC_SFT			12
#define RT5640_PLL1_SRC_MCLK			(0x0 << 12)
#define RT5640_PLL1_SRC_BCLK1			(0x1 << 12)
#define RT5640_PLL1_SRC_BCLK2			(0x2 << 12)
#define RT5640_PLL1_SRC_BCLK3			(0x3 << 12)
#define RT5640_PLL1_PD_MASK			(0x1 << 3)
#define RT5640_PLL1_PD_SFT			3
#define RT5640_PLL1_PD_1			(0x0 << 3)
#define RT5640_PLL1_PD_2			(0x1 << 3)

#define RT5640_PLL_INP_MAX			40000000
#define RT5640_PLL_INP_MIN			256000
/* PLL M/N/K Code Control 1 (0x81) */
#define RT5640_PLL_N_MAX			0x1ff
#define RT5640_PLL_N_MASK			(RT5640_PLL_N_MAX << 7)
#define RT5640_PLL_N_SFT			7
#define RT5640_PLL_K_MAX			0x1f
#define RT5640_PLL_K_MASK			(RT5640_PLL_K_MAX)
#define RT5640_PLL_K_SFT			0

/* PLL M/N/K Code Control 2 (0x82) */
#define RT5640_PLL_M_MAX			0xf
#define RT5640_PLL_M_MASK			(RT5640_PLL_M_MAX << 12)
#define RT5640_PLL_M_SFT			12
#define RT5640_PLL_M_BP				(0x1 << 11)
#define RT5640_PLL_M_BP_SFT			11

/* ASRC Control 1 (0x83) */
#define RT5640_STO_T_MASK			(0x1 << 15)
#define RT5640_STO_T_SFT			15
#define RT5640_STO_T_SCLK			(0x0 << 15)
#define RT5640_STO_T_LRCK1			(0x1 << 15)
#define RT5640_M1_T_MASK			(0x1 << 14)
#define RT5640_M1_T_SFT				14
#define RT5640_M1_T_I2S2			(0x0 << 14)
#define RT5640_M1_T_I2S2_D3			(0x1 << 14)
#define RT5640_I2S2_F_MASK			(0x1 << 12)
#define RT5640_I2S2_F_SFT			12
#define RT5640_I2S2_F_I2S2_D2			(0x0 << 12)
#define RT5640_I2S2_F_I2S1_TCLK			(0x1 << 12)
#define RT5640_DMIC_1_M_MASK			(0x1 << 9)
#define RT5640_DMIC_1_M_SFT			9
#define RT5640_DMIC_1_M_NOR			(0x0 << 9)
#define RT5640_DMIC_1_M_ASYN			(0x1 << 9)
#define RT5640_DMIC_2_M_MASK			(0x1 << 8)
#define RT5640_DMIC_2_M_SFT			8
#define RT5640_DMIC_2_M_NOR			(0x0 << 8)
#define RT5640_DMIC_2_M_ASYN			(0x1 << 8)

/* ASRC Control 2 (0x84) */
#define RT5640_MDA_L_M_MASK			(0x1 << 15)
#define RT5640_MDA_L_M_SFT			15
#define RT5640_MDA_L_M_NOR			(0x0 << 15)
#define RT5640_MDA_L_M_ASYN			(0x1 << 15)
#define RT5640_MDA_R_M_MASK			(0x1 << 14)
#define RT5640_MDA_R_M_SFT			14
#define RT5640_MDA_R_M_NOR			(0x0 << 14)
#define RT5640_MDA_R_M_ASYN			(0x1 << 14)
#define RT5640_MAD_L_M_MASK			(0x1 << 13)
#define RT5640_MAD_L_M_SFT			13
#define RT5640_MAD_L_M_NOR			(0x0 << 13)
#define RT5640_MAD_L_M_ASYN			(0x1 << 13)
#define RT5640_MAD_R_M_MASK			(0x1 << 12)
#define RT5640_MAD_R_M_SFT			12
#define RT5640_MAD_R_M_NOR			(0x0 << 12)
#define RT5640_MAD_R_M_ASYN			(0x1 << 12)
#define RT5640_ADC_M_MASK			(0x1 << 11)
#define RT5640_ADC_M_SFT			11
#define RT5640_ADC_M_NOR			(0x0 << 11)
#define RT5640_ADC_M_ASYN			(0x1 << 11)
#define RT5640_STO_DAC_M_MASK			(0x1 << 5)
#define RT5640_STO_DAC_M_SFT			5
#define RT5640_STO_DAC_M_NOR			(0x0 << 5)
#define RT5640_STO_DAC_M_ASYN			(0x1 << 5)
#define RT5640_I2S1_R_D_MASK			(0x1 << 4)
#define RT5640_I2S1_R_D_SFT			4
#define RT5640_I2S1_R_D_DIS			(0x0 << 4)
#define RT5640_I2S1_R_D_EN			(0x1 << 4)
#define RT5640_I2S2_R_D_MASK			(0x1 << 3)
#define RT5640_I2S2_R_D_SFT			3
#define RT5640_I2S2_R_D_DIS			(0x0 << 3)
#define RT5640_I2S2_R_D_EN			(0x1 << 3)
#define RT5640_PRE_SCLK_MASK			(0x3)
#define RT5640_PRE_SCLK_SFT			0
#define RT5640_PRE_SCLK_512			(0x0)
#define RT5640_PRE_SCLK_1024			(0x1)
#define RT5640_PRE_SCLK_2048			(0x2)

/* ASRC Control 3 (0x85) */
#define RT5640_I2S1_RATE_MASK			(0xf << 12)
#define RT5640_I2S1_RATE_SFT			12
#define RT5640_I2S2_RATE_MASK			(0xf << 8)
#define RT5640_I2S2_RATE_SFT			8

/* ASRC Control 4 (0x89) */
#define RT5640_I2S1_PD_MASK			(0x7 << 12)
#define RT5640_I2S1_PD_SFT			12
#define RT5640_I2S2_PD_MASK			(0x7 << 8)
#define RT5640_I2S2_PD_SFT			8

/* HPOUT Over Current Detection (0x8b) */
#define RT5640_HP_OVCD_MASK			(0x1 << 10)
#define RT5640_HP_OVCD_SFT			10
#define RT5640_HP_OVCD_DIS			(0x0 << 10)
#define RT5640_HP_OVCD_EN			(0x1 << 10)
#define RT5640_HP_OC_TH_MASK			(0x3 << 8)
#define RT5640_HP_OC_TH_SFT			8
#define RT5640_HP_OC_TH_90			(0x0 << 8)
#define RT5640_HP_OC_TH_105			(0x1 << 8)
#define RT5640_HP_OC_TH_120			(0x2 << 8)
#define RT5640_HP_OC_TH_135			(0x3 << 8)

/* Class D Over Current Control (0x8c) */
#define RT5640_CLSD_OC_MASK			(0x1 << 9)
#define RT5640_CLSD_OC_SFT			9
#define RT5640_CLSD_OC_PU			(0x0 << 9)
#define RT5640_CLSD_OC_PD			(0x1 << 9)
#define RT5640_AUTO_PD_MASK			(0x1 << 8)
#define RT5640_AUTO_PD_SFT			8
#define RT5640_AUTO_PD_DIS			(0x0 << 8)
#define RT5640_AUTO_PD_EN			(0x1 << 8)
#define RT5640_CLSD_OC_TH_MASK			(0x3f)
#define RT5640_CLSD_OC_TH_SFT			0

/* Class D Output Control (0x8d) */
#define RT5640_CLSD_RATIO_MASK			(0xf << 12)
#define RT5640_CLSD_RATIO_SFT			12
#define RT5640_CLSD_OM_MASK			(0x1 << 11)
#define RT5640_CLSD_OM_SFT			11
#define RT5640_CLSD_OM_MONO			(0x0 << 11)
#define RT5640_CLSD_OM_STO			(0x1 << 11)
#define RT5640_CLSD_SCH_MASK			(0x1 << 10)
#define RT5640_CLSD_SCH_SFT			10
#define RT5640_CLSD_SCH_L			(0x0 << 10)
#define RT5640_CLSD_SCH_S			(0x1 << 10)

/* Depop Mode Control 1 (0x8e) */
#define RT5640_SMT_TRIG_MASK			(0x1 << 15)
#define RT5640_SMT_TRIG_SFT			15
#define RT5640_SMT_TRIG_DIS			(0x0 << 15)
#define RT5640_SMT_TRIG_EN			(0x1 << 15)
#define RT5640_HP_L_SMT_MASK			(0x1 << 9)
#define RT5640_HP_L_SMT_SFT			9
#define RT5640_HP_L_SMT_DIS			(0x0 << 9)
#define RT5640_HP_L_SMT_EN			(0x1 << 9)
#define RT5640_HP_R_SMT_MASK			(0x1 << 8)
#define RT5640_HP_R_SMT_SFT			8
#define RT5640_HP_R_SMT_DIS			(0x0 << 8)
#define RT5640_HP_R_SMT_EN			(0x1 << 8)
#define RT5640_HP_CD_PD_MASK			(0x1 << 7)
#define RT5640_HP_CD_PD_SFT			7
#define RT5640_HP_CD_PD_DIS			(0x0 << 7)
#define RT5640_HP_CD_PD_EN			(0x1 << 7)
#define RT5640_RSTN_MASK			(0x1 << 6)
#define RT5640_RSTN_SFT				6
#define RT5640_RSTN_DIS				(0x0 << 6)
#define RT5640_RSTN_EN				(0x1 << 6)
#define RT5640_RSTP_MASK			(0x1 << 5)
#define RT5640_RSTP_SFT				5
#define RT5640_RSTP_DIS				(0x0 << 5)
#define RT5640_RSTP_EN				(0x1 << 5)
#define RT5640_HP_CO_MASK			(0x1 << 4)
#define RT5640_HP_CO_SFT			4
#define RT5640_HP_CO_DIS			(0x0 << 4)
#define RT5640_HP_CO_EN				(0x1 << 4)
#define RT5640_HP_CP_MASK			(0x1 << 3)
#define RT5640_HP_CP_SFT			3
#define RT5640_HP_CP_PD				(0x0 << 3)
#define RT5640_HP_CP_PU				(0x1 << 3)
#define RT5640_HP_SG_MASK			(0x1 << 2)
#define RT5640_HP_SG_SFT			2
#define RT5640_HP_SG_DIS			(0x0 << 2)
#define RT5640_HP_SG_EN				(0x1 << 2)
#define RT5640_HP_DP_MASK			(0x1 << 1)
#define RT5640_HP_DP_SFT			1
#define RT5640_HP_DP_PD				(0x0 << 1)
#define RT5640_HP_DP_PU				(0x1 << 1)
#define RT5640_HP_CB_MASK			(0x1)
#define RT5640_HP_CB_SFT			0
#define RT5640_HP_CB_PD				(0x0)
#define RT5640_HP_CB_PU				(0x1)

/* Depop Mode Control 2 (0x8f) */
#define RT5640_DEPOP_MASK			(0x1 << 13)
#define RT5640_DEPOP_SFT			13
#define RT5640_DEPOP_AUTO			(0x0 << 13)
#define RT5640_DEPOP_MAN			(0x1 << 13)
#define RT5640_RAMP_MASK			(0x1 << 12)
#define RT5640_RAMP_SFT				12
#define RT5640_RAMP_DIS				(0x0 << 12)
#define RT5640_RAMP_EN				(0x1 << 12)
#define RT5640_BPS_MASK				(0x1 << 11)
#define RT5640_BPS_SFT				11
#define RT5640_BPS_DIS				(0x0 << 11)
#define RT5640_BPS_EN				(0x1 << 11)
#define RT5640_FAST_UPDN_MASK			(0x1 << 10)
#define RT5640_FAST_UPDN_SFT			10
#define RT5640_FAST_UPDN_DIS			(0x0 << 10)
#define RT5640_FAST_UPDN_EN			(0x1 << 10)
#define RT5640_MRES_MASK			(0x3 << 8)
#define RT5640_MRES_SFT				8
#define RT5640_MRES_15MO			(0x0 << 8)
#define RT5640_MRES_25MO			(0x1 << 8)
#define RT5640_MRES_35MO			(0x2 << 8)
#define RT5640_MRES_45MO			(0x3 << 8)
#define RT5640_VLO_MASK				(0x1 << 7)
#define RT5640_VLO_SFT				7
#define RT5640_VLO_3V				(0x0 << 7)
#define RT5640_VLO_32V				(0x1 << 7)
#define RT5640_DIG_DP_MASK			(0x1 << 6)
#define RT5640_DIG_DP_SFT			6
#define RT5640_DIG_DP_DIS			(0x0 << 6)
#define RT5640_DIG_DP_EN			(0x1 << 6)
#define RT5640_DP_TH_MASK			(0x3 << 4)
#define RT5640_DP_TH_SFT			4

/* Depop Mode Control 3 (0x90) */
#define RT5640_CP_SYS_MASK			(0x7 << 12)
#define RT5640_CP_SYS_SFT			12
#define RT5640_CP_FQ1_MASK			(0x7 << 8)
#define RT5640_CP_FQ1_SFT			8
#define RT5640_CP_FQ2_MASK			(0x7 << 4)
#define RT5640_CP_FQ2_SFT			4
#define RT5640_CP_FQ3_MASK			(0x7)
#define RT5640_CP_FQ3_SFT			0
#define RT5640_CP_FQ_1_5_KHZ			0
#define RT5640_CP_FQ_3_KHZ			1
#define RT5640_CP_FQ_6_KHZ			2
#define RT5640_CP_FQ_12_KHZ			3
#define RT5640_CP_FQ_24_KHZ			4
#define RT5640_CP_FQ_48_KHZ			5
#define RT5640_CP_FQ_96_KHZ			6
#define RT5640_CP_FQ_192_KHZ			7

/* HPOUT charge pump (0x91) */
#define RT5640_OSW_L_MASK			(0x1 << 11)
#define RT5640_OSW_L_SFT			11
#define RT5640_OSW_L_DIS			(0x0 << 11)
#define RT5640_OSW_L_EN				(0x1 << 11)
#define RT5640_OSW_R_MASK			(0x1 << 10)
#define RT5640_OSW_R_SFT			10
#define RT5640_OSW_R_DIS			(0x0 << 10)
#define RT5640_OSW_R_EN				(0x1 << 10)
#define RT5640_PM_HP_MASK			(0x3 << 8)
#define RT5640_PM_HP_SFT			8
#define RT5640_PM_HP_LV				(0x0 << 8)
#define RT5640_PM_HP_MV				(0x1 << 8)
#define RT5640_PM_HP_HV				(0x2 << 8)
#define RT5640_IB_HP_MASK			(0x3 << 6)
#define RT5640_IB_HP_SFT			6
#define RT5640_IB_HP_125IL			(0x0 << 6)
#define RT5640_IB_HP_25IL			(0x1 << 6)
#define RT5640_IB_HP_5IL			(0x2 << 6)
#define RT5640_IB_HP_1IL			(0x3 << 6)

/* PV detection and SPK gain control (0x92) */
#define RT5640_PVDD_DET_MASK			(0x1 << 15)
#define RT5640_PVDD_DET_SFT			15
#define RT5640_PVDD_DET_DIS			(0x0 << 15)
#define RT5640_PVDD_DET_EN			(0x1 << 15)
#define RT5640_SPK_AG_MASK			(0x1 << 14)
#define RT5640_SPK_AG_SFT			14
#define RT5640_SPK_AG_DIS			(0x0 << 14)
#define RT5640_SPK_AG_EN			(0x1 << 14)

/* Micbias Control (0x93) */
#define RT5640_MIC1_BS_MASK			(0x1 << 15)
#define RT5640_MIC1_BS_SFT			15
#define RT5640_MIC1_BS_9AV			(0x0 << 15)
#define RT5640_MIC1_BS_75AV			(0x1 << 15)
#define RT5640_MIC2_BS_MASK			(0x1 << 14)
#define RT5640_MIC2_BS_SFT			14
#define RT5640_MIC2_BS_9AV			(0x0 << 14)
#define RT5640_MIC2_BS_75AV			(0x1 << 14)
#define RT5640_MIC1_CLK_MASK			(0x1 << 13)
#define RT5640_MIC1_CLK_SFT			13
#define RT5640_MIC1_CLK_DIS			(0x0 << 13)
#define RT5640_MIC1_CLK_EN			(0x1 << 13)
#define RT5640_MIC2_CLK_MASK			(0x1 << 12)
#define RT5640_MIC2_CLK_SFT			12
#define RT5640_MIC2_CLK_DIS			(0x0 << 12)
#define RT5640_MIC2_CLK_EN			(0x1 << 12)
#define RT5640_MIC1_OVCD_MASK			(0x1 << 11)
#define RT5640_MIC1_OVCD_SFT			11
#define RT5640_MIC1_OVCD_DIS			(0x0 << 11)
#define RT5640_MIC1_OVCD_EN			(0x1 << 11)
#define RT5640_MIC1_OVTH_MASK			(0x3 << 9)
#define RT5640_MIC1_OVTH_SFT			9
#define RT5640_MIC1_OVTH_600UA			(0x0 << 9)
#define RT5640_MIC1_OVTH_1500UA			(0x1 << 9)
#define RT5640_MIC1_OVTH_2000UA			(0x2 << 9)
#define RT5640_MIC2_OVCD_MASK			(0x1 << 8)
#define RT5640_MIC2_OVCD_SFT			8
#define RT5640_MIC2_OVCD_DIS			(0x0 << 8)
#define RT5640_MIC2_OVCD_EN			(0x1 << 8)
#define RT5640_MIC2_OVTH_MASK			(0x3 << 6)
#define RT5640_MIC2_OVTH_SFT			6
#define RT5640_MIC2_OVTH_600UA			(0x0 << 6)
#define RT5640_MIC2_OVTH_1500UA			(0x1 << 6)
#define RT5640_MIC2_OVTH_2000UA			(0x2 << 6)
#define RT5640_PWR_MB_MASK			(0x1 << 5)
#define RT5640_PWR_MB_SFT			5
#define RT5640_PWR_MB_PD			(0x0 << 5)
#define RT5640_PWR_MB_PU			(0x1 << 5)
#define RT5640_PWR_CLK25M_MASK			(0x1 << 4)
#define RT5640_PWR_CLK25M_SFT			4
#define RT5640_PWR_CLK25M_PD			(0x0 << 4)
#define RT5640_PWR_CLK25M_PU			(0x1 << 4)

/* EQ Control 1 (0xb0) */
#define RT5640_EQ_SRC_MASK			(0x1 << 15)
#define RT5640_EQ_SRC_SFT			15
#define RT5640_EQ_SRC_DAC			(0x0 << 15)
#define RT5640_EQ_SRC_ADC			(0x1 << 15)
#define RT5640_EQ_UPD				(0x1 << 14)
#define RT5640_EQ_UPD_BIT			14
#define RT5640_EQ_CD_MASK			(0x1 << 13)
#define RT5640_EQ_CD_SFT			13
#define RT5640_EQ_CD_DIS			(0x0 << 13)
#define RT5640_EQ_CD_EN				(0x1 << 13)
#define RT5640_EQ_DITH_MASK			(0x3 << 8)
#define RT5640_EQ_DITH_SFT			8
#define RT5640_EQ_DITH_NOR			(0x0 << 8)
#define RT5640_EQ_DITH_LSB			(0x1 << 8)
#define RT5640_EQ_DITH_LSB_1			(0x2 << 8)
#define RT5640_EQ_DITH_LSB_2			(0x3 << 8)

/* EQ Control 2 (0xb1) */
#define RT5640_EQ_HPF1_M_MASK			(0x1 << 8)
#define RT5640_EQ_HPF1_M_SFT			8
#define RT5640_EQ_HPF1_M_HI			(0x0 << 8)
#define RT5640_EQ_HPF1_M_1ST			(0x1 << 8)
#define RT5640_EQ_LPF1_M_MASK			(0x1 << 7)
#define RT5640_EQ_LPF1_M_SFT			7
#define RT5640_EQ_LPF1_M_LO			(0x0 << 7)
#define RT5640_EQ_LPF1_M_1ST			(0x1 << 7)
#define RT5640_EQ_HPF2_MASK			(0x1 << 6)
#define RT5640_EQ_HPF2_SFT			6
#define RT5640_EQ_HPF2_DIS			(0x0 << 6)
#define RT5640_EQ_HPF2_EN			(0x1 << 6)
#define RT5640_EQ_HPF1_MASK			(0x1 << 5)
#define RT5640_EQ_HPF1_SFT			5
#define RT5640_EQ_HPF1_DIS			(0x0 << 5)
#define RT5640_EQ_HPF1_EN			(0x1 << 5)
#define RT5640_EQ_BPF4_MASK			(0x1 << 4)
#define RT5640_EQ_BPF4_SFT			4
#define RT5640_EQ_BPF4_DIS			(0x0 << 4)
#define RT5640_EQ_BPF4_EN			(0x1 << 4)
#define RT5640_EQ_BPF3_MASK			(0x1 << 3)
#define RT5640_EQ_BPF3_SFT			3
#define RT5640_EQ_BPF3_DIS			(0x0 << 3)
#define RT5640_EQ_BPF3_EN			(0x1 << 3)
#define RT5640_EQ_BPF2_MASK			(0x1 << 2)
#define RT5640_EQ_BPF2_SFT			2
#define RT5640_EQ_BPF2_DIS			(0x0 << 2)
#define RT5640_EQ_BPF2_EN			(0x1 << 2)
#define RT5640_EQ_BPF1_MASK			(0x1 << 1)
#define RT5640_EQ_BPF1_SFT			1
#define RT5640_EQ_BPF1_DIS			(0x0 << 1)
#define RT5640_EQ_BPF1_EN			(0x1 << 1)
#define RT5640_EQ_LPF_MASK			(0x1)
#define RT5640_EQ_LPF_SFT			0
#define RT5640_EQ_LPF_DIS			(0x0)
#define RT5640_EQ_LPF_EN			(0x1)

/* Memory Test (0xb2) */
#define RT5640_MT_MASK				(0x1 << 15)
#define RT5640_MT_SFT				15
#define RT5640_MT_DIS				(0x0 << 15)
#define RT5640_MT_EN				(0x1 << 15)

/* DRC/AGC Control 1 (0xb4) */
#define RT5640_DRC_AGC_P_MASK			(0x1 << 15)
#define RT5640_DRC_AGC_P_SFT			15
#define RT5640_DRC_AGC_P_DAC			(0x0 << 15)
#define RT5640_DRC_AGC_P_ADC			(0x1 << 15)
#define RT5640_DRC_AGC_MASK			(0x1 << 14)
#define RT5640_DRC_AGC_SFT			14
#define RT5640_DRC_AGC_DIS			(0x0 << 14)
#define RT5640_DRC_AGC_EN			(0x1 << 14)
#define RT5640_DRC_AGC_UPD			(0x1 << 13)
#define RT5640_DRC_AGC_UPD_BIT			13
#define RT5640_DRC_AGC_AR_MASK			(0x1f << 8)
#define RT5640_DRC_AGC_AR_SFT			8
#define RT5640_DRC_AGC_R_MASK			(0x7 << 5)
#define RT5640_DRC_AGC_R_SFT			5
#define RT5640_DRC_AGC_R_48K			(0x1 << 5)
#define RT5640_DRC_AGC_R_96K			(0x2 << 5)
#define RT5640_DRC_AGC_R_192K			(0x3 << 5)
#define RT5640_DRC_AGC_R_441K			(0x5 << 5)
#define RT5640_DRC_AGC_R_882K			(0x6 << 5)
#define RT5640_DRC_AGC_R_1764K			(0x7 << 5)
#define RT5640_DRC_AGC_RC_MASK			(0x1f)
#define RT5640_DRC_AGC_RC_SFT			0

/* DRC/AGC Control 2 (0xb5) */
#define RT5640_DRC_AGC_POB_MASK			(0x3f << 8)
#define RT5640_DRC_AGC_POB_SFT			8
#define RT5640_DRC_AGC_CP_MASK			(0x1 << 7)
#define RT5640_DRC_AGC_CP_SFT			7
#define RT5640_DRC_AGC_CP_DIS			(0x0 << 7)
#define RT5640_DRC_AGC_CP_EN			(0x1 << 7)
#define RT5640_DRC_AGC_CPR_MASK			(0x3 << 5)
#define RT5640_DRC_AGC_CPR_SFT			5
#define RT5640_DRC_AGC_CPR_1_1			(0x0 << 5)
#define RT5640_DRC_AGC_CPR_1_2			(0x1 << 5)
#define RT5640_DRC_AGC_CPR_1_3			(0x2 << 5)
#define RT5640_DRC_AGC_CPR_1_4			(0x3 << 5)
#define RT5640_DRC_AGC_PRB_MASK			(0x1f)
#define RT5640_DRC_AGC_PRB_SFT			0

/* DRC/AGC Control 3 (0xb6) */
#define RT5640_DRC_AGC_NGB_MASK			(0xf << 12)
#define RT5640_DRC_AGC_NGB_SFT			12
#define RT5640_DRC_AGC_TAR_MASK			(0x1f << 7)
#define RT5640_DRC_AGC_TAR_SFT			7
#define RT5640_DRC_AGC_NG_MASK			(0x1 << 6)
#define RT5640_DRC_AGC_NG_SFT			6
#define RT5640_DRC_AGC_NG_DIS			(0x0 << 6)
#define RT5640_DRC_AGC_NG_EN			(0x1 << 6)
#define RT5640_DRC_AGC_NGH_MASK			(0x1 << 5)
#define RT5640_DRC_AGC_NGH_SFT			5
#define RT5640_DRC_AGC_NGH_DIS			(0x0 << 5)
#define RT5640_DRC_AGC_NGH_EN			(0x1 << 5)
#define RT5640_DRC_AGC_NGT_MASK			(0x1f)
#define RT5640_DRC_AGC_NGT_SFT			0

/* ANC Control 1 (0xb8) */
#define RT5640_ANC_M_MASK			(0x1 << 15)
#define RT5640_ANC_M_SFT			15
#define RT5640_ANC_M_NOR			(0x0 << 15)
#define RT5640_ANC_M_REV			(0x1 << 15)
#define RT5640_ANC_MASK				(0x1 << 14)
#define RT5640_ANC_SFT				14
#define RT5640_ANC_DIS				(0x0 << 14)
#define RT5640_ANC_EN				(0x1 << 14)
#define RT5640_ANC_MD_MASK			(0x3 << 12)
#define RT5640_ANC_MD_SFT			12
#define RT5640_ANC_MD_DIS			(0x0 << 12)
#define RT5640_ANC_MD_67MS			(0x1 << 12)
#define RT5640_ANC_MD_267MS			(0x2 << 12)
#define RT5640_ANC_MD_1067MS			(0x3 << 12)
#define RT5640_ANC_SN_MASK			(0x1 << 11)
#define RT5640_ANC_SN_SFT			11
#define RT5640_ANC_SN_DIS			(0x0 << 11)
#define RT5640_ANC_SN_EN			(0x1 << 11)
#define RT5640_ANC_CLK_MASK			(0x1 << 10)
#define RT5640_ANC_CLK_SFT			10
#define RT5640_ANC_CLK_ANC			(0x0 << 10)
#define RT5640_ANC_CLK_REG			(0x1 << 10)
#define RT5640_ANC_ZCD_MASK			(0x3 << 8)
#define RT5640_ANC_ZCD_SFT			8
#define RT5640_ANC_ZCD_DIS			(0x0 << 8)
#define RT5640_ANC_ZCD_T1			(0x1 << 8)
#define RT5640_ANC_ZCD_T2			(0x2 << 8)
#define RT5640_ANC_ZCD_WT			(0x3 << 8)
#define RT5640_ANC_CS_MASK			(0x1 << 7)
#define RT5640_ANC_CS_SFT			7
#define RT5640_ANC_CS_DIS			(0x0 << 7)
#define RT5640_ANC_CS_EN			(0x1 << 7)
#define RT5640_ANC_SW_MASK			(0x1 << 6)
#define RT5640_ANC_SW_SFT			6
#define RT5640_ANC_SW_NOR			(0x0 << 6)
#define RT5640_ANC_SW_AUTO			(0x1 << 6)
#define RT5640_ANC_CO_L_MASK			(0x3f)
#define RT5640_ANC_CO_L_SFT			0

/* ANC Control 2 (0xb6) */
#define RT5640_ANC_FG_R_MASK			(0xf << 12)
#define RT5640_ANC_FG_R_SFT			12
#define RT5640_ANC_FG_L_MASK			(0xf << 8)
#define RT5640_ANC_FG_L_SFT			8
#define RT5640_ANC_CG_R_MASK			(0xf << 4)
#define RT5640_ANC_CG_R_SFT			4
#define RT5640_ANC_CG_L_MASK			(0xf)
#define RT5640_ANC_CG_L_SFT			0

/* ANC Control 3 (0xb6) */
#define RT5640_ANC_CD_MASK			(0x1 << 6)
#define RT5640_ANC_CD_SFT			6
#define RT5640_ANC_CD_BOTH			(0x0 << 6)
#define RT5640_ANC_CD_IND			(0x1 << 6)
#define RT5640_ANC_CO_R_MASK			(0x3f)
#define RT5640_ANC_CO_R_SFT			0

/* Jack Detect Control (0xbb) */
#define RT5640_JD_MASK				(0x7 << 13)
#define RT5640_JD_SFT				13
#define RT5640_JD_DIS				(0x0 << 13)
#define RT5640_JD_GPIO1				(0x1 << 13)
#define RT5640_JD_JD1_IN4P			(0x2 << 13)
#define RT5640_JD_JD2_IN4N			(0x3 << 13)
#define RT5640_JD_GPIO2				(0x4 << 13)
#define RT5640_JD_GPIO3				(0x5 << 13)
#define RT5640_JD_GPIO4				(0x6 << 13)
#define RT5640_JD_HP_MASK			(0x1 << 11)
#define RT5640_JD_HP_SFT			11
#define RT5640_JD_HP_DIS			(0x0 << 11)
#define RT5640_JD_HP_EN				(0x1 << 11)
#define RT5640_JD_HP_TRG_MASK			(0x1 << 10)
#define RT5640_JD_HP_TRG_SFT			10
#define RT5640_JD_HP_TRG_LO			(0x0 << 10)
#define RT5640_JD_HP_TRG_HI			(0x1 << 10)
#define RT5640_JD_SPL_MASK			(0x1 << 9)
#define RT5640_JD_SPL_SFT			9
#define RT5640_JD_SPL_DIS			(0x0 << 9)
#define RT5640_JD_SPL_EN			(0x1 << 9)
#define RT5640_JD_SPL_TRG_MASK			(0x1 << 8)
#define RT5640_JD_SPL_TRG_SFT			8
#define RT5640_JD_SPL_TRG_LO			(0x0 << 8)
#define RT5640_JD_SPL_TRG_HI			(0x1 << 8)
#define RT5640_JD_SPR_MASK			(0x1 << 7)
#define RT5640_JD_SPR_SFT			7
#define RT5640_JD_SPR_DIS			(0x0 << 7)
#define RT5640_JD_SPR_EN			(0x1 << 7)
#define RT5640_JD_SPR_TRG_MASK			(0x1 << 6)
#define RT5640_JD_SPR_TRG_SFT			6
#define RT5640_JD_SPR_TRG_LO			(0x0 << 6)
#define RT5640_JD_SPR_TRG_HI			(0x1 << 6)
#define RT5640_JD_MO_MASK			(0x1 << 5)
#define RT5640_JD_MO_SFT			5
#define RT5640_JD_MO_DIS			(0x0 << 5)
#define RT5640_JD_MO_EN				(0x1 << 5)
#define RT5640_JD_MO_TRG_MASK			(0x1 << 4)
#define RT5640_JD_MO_TRG_SFT			4
#define RT5640_JD_MO_TRG_LO			(0x0 << 4)
#define RT5640_JD_MO_TRG_HI			(0x1 << 4)
#define RT5640_JD_LO_MASK			(0x1 << 3)
#define RT5640_JD_LO_SFT			3
#define RT5640_JD_LO_DIS			(0x0 << 3)
#define RT5640_JD_LO_EN				(0x1 << 3)
#define RT5640_JD_LO_TRG_MASK			(0x1 << 2)
#define RT5640_JD_LO_TRG_SFT			2
#define RT5640_JD_LO_TRG_LO			(0x0 << 2)
#define RT5640_JD_LO_TRG_HI			(0x1 << 2)
#define RT5640_JD1_IN4P_MASK			(0x1 << 1)
#define RT5640_JD1_IN4P_SFT			1
#define RT5640_JD1_IN4P_DIS			(0x0 << 1)
#define RT5640_JD1_IN4P_EN			(0x1 << 1)
#define RT5640_JD2_IN4N_MASK			(0x1)
#define RT5640_JD2_IN4N_SFT			0
#define RT5640_JD2_IN4N_DIS			(0x0)
#define RT5640_JD2_IN4N_EN			(0x1)

/* Jack detect for ANC (0xbc) */
#define RT5640_ANC_DET_MASK			(0x3 << 4)
#define RT5640_ANC_DET_SFT			4
#define RT5640_ANC_DET_DIS			(0x0 << 4)
#define RT5640_ANC_DET_MB1			(0x1 << 4)
#define RT5640_ANC_DET_MB2			(0x2 << 4)
#define RT5640_ANC_DET_JD			(0x3 << 4)
#define RT5640_AD_TRG_MASK			(0x1 << 3)
#define RT5640_AD_TRG_SFT			3
#define RT5640_AD_TRG_LO			(0x0 << 3)
#define RT5640_AD_TRG_HI			(0x1 << 3)
#define RT5640_ANCM_DET_MASK			(0x3 << 4)
#define RT5640_ANCM_DET_SFT			4
#define RT5640_ANCM_DET_DIS			(0x0 << 4)
#define RT5640_ANCM_DET_MB1			(0x1 << 4)
#define RT5640_ANCM_DET_MB2			(0x2 << 4)
#define RT5640_ANCM_DET_JD			(0x3 << 4)
#define RT5640_AMD_TRG_MASK			(0x1 << 3)
#define RT5640_AMD_TRG_SFT			3
#define RT5640_AMD_TRG_LO			(0x0 << 3)
#define RT5640_AMD_TRG_HI			(0x1 << 3)

/* IRQ Control 1 (0xbd) */
#define RT5640_IRQ_JD_MASK			(0x1 << 15)
#define RT5640_IRQ_JD_SFT			15
#define RT5640_IRQ_JD_BP			(0x0 << 15)
#define RT5640_IRQ_JD_NOR			(0x1 << 15)
#define RT5640_IRQ_OT_MASK			(0x1 << 14)
#define RT5640_IRQ_OT_SFT			14
#define RT5640_IRQ_OT_BP			(0x0 << 14)
#define RT5640_IRQ_OT_NOR			(0x1 << 14)
#define RT5640_JD_STKY_MASK			(0x1 << 13)
#define RT5640_JD_STKY_SFT			13
#define RT5640_JD_STKY_DIS			(0x0 << 13)
#define RT5640_JD_STKY_EN			(0x1 << 13)
#define RT5640_OT_STKY_MASK			(0x1 << 12)
#define RT5640_OT_STKY_SFT			12
#define RT5640_OT_STKY_DIS			(0x0 << 12)
#define RT5640_OT_STKY_EN			(0x1 << 12)
#define RT5640_JD_P_MASK			(0x1 << 11)
#define RT5640_JD_P_SFT				11
#define RT5640_JD_P_NOR				(0x0 << 11)
#define RT5640_JD_P_INV				(0x1 << 11)
#define RT5640_OT_P_MASK			(0x1 << 10)
#define RT5640_OT_P_SFT				10
#define RT5640_OT_P_NOR				(0x0 << 10)
#define RT5640_OT_P_INV				(0x1 << 10)

/* IRQ Control 2 (0xbe) */
#define RT5640_IRQ_MB1_OC_MASK			(0x1 << 15)
#define RT5640_IRQ_MB1_OC_SFT			15
#define RT5640_IRQ_MB1_OC_BP			(0x0 << 15)
#define RT5640_IRQ_MB1_OC_NOR			(0x1 << 15)
#define RT5640_IRQ_MB2_OC_MASK			(0x1 << 14)
#define RT5640_IRQ_MB2_OC_SFT			14
#define RT5640_IRQ_MB2_OC_BP			(0x0 << 14)
#define RT5640_IRQ_MB2_OC_NOR			(0x1 << 14)
#define RT5640_MB1_OC_STKY_MASK			(0x1 << 11)
#define RT5640_MB1_OC_STKY_SFT			11
#define RT5640_MB1_OC_STKY_DIS			(0x0 << 11)
#define RT5640_MB1_OC_STKY_EN			(0x1 << 11)
#define RT5640_MB2_OC_STKY_MASK			(0x1 << 10)
#define RT5640_MB2_OC_STKY_SFT			10
#define RT5640_MB2_OC_STKY_DIS			(0x0 << 10)
#define RT5640_MB2_OC_STKY_EN			(0x1 << 10)
#define RT5640_MB1_OC_P_MASK			(0x1 << 7)
#define RT5640_MB1_OC_P_SFT			7
#define RT5640_MB1_OC_P_NOR			(0x0 << 7)
#define RT5640_MB1_OC_P_INV			(0x1 << 7)
#define RT5640_MB2_OC_P_MASK			(0x1 << 6)
#define RT5640_MB2_OC_P_SFT			6
#define RT5640_MB2_OC_P_NOR			(0x0 << 6)
#define RT5640_MB2_OC_P_INV			(0x1 << 6)
#define RT5640_MB1_OC_CLR			(0x1 << 3)
#define RT5640_MB1_OC_CLR_SFT			3
#define RT5640_MB2_OC_CLR			(0x1 << 2)
#define RT5640_MB2_OC_CLR_SFT			2

/* GPIO Control 1 (0xc0) */
#define RT5640_GP1_PIN_MASK			(0x1 << 15)
#define RT5640_GP1_PIN_SFT			15
#define RT5640_GP1_PIN_GPIO1			(0x0 << 15)
#define RT5640_GP1_PIN_IRQ			(0x1 << 15)
#define RT5640_GP2_PIN_MASK			(0x1 << 14)
#define RT5640_GP2_PIN_SFT			14
#define RT5640_GP2_PIN_GPIO2			(0x0 << 14)
#define RT5640_GP2_PIN_DMIC1_SCL		(0x1 << 14)
#define RT5640_GP3_PIN_MASK			(0x3 << 12)
#define RT5640_GP3_PIN_SFT			12
#define RT5640_GP3_PIN_GPIO3			(0x0 << 12)
#define RT5640_GP3_PIN_DMIC1_SDA		(0x1 << 12)
#define RT5640_GP3_PIN_IRQ			(0x2 << 12)
#define RT5640_GP4_PIN_MASK			(0x1 << 11)
#define RT5640_GP4_PIN_SFT			11
#define RT5640_GP4_PIN_GPIO4			(0x0 << 11)
#define RT5640_GP4_PIN_DMIC2_SDA		(0x1 << 11)
#define RT5640_DP_SIG_MASK			(0x1 << 10)
#define RT5640_DP_SIG_SFT			10
#define RT5640_DP_SIG_TEST			(0x0 << 10)
#define RT5640_DP_SIG_AP			(0x1 << 10)
#define RT5640_GPIO_M_MASK			(0x1 << 9)
#define RT5640_GPIO_M_SFT			9
#define RT5640_GPIO_M_FLT			(0x0 << 9)
#define RT5640_GPIO_M_PH			(0x1 << 9)

/* GPIO Control 3 (0xc2) */
#define RT5640_GP4_PF_MASK			(0x1 << 11)
#define RT5640_GP4_PF_SFT			11
#define RT5640_GP4_PF_IN			(0x0 << 11)
#define RT5640_GP4_PF_OUT			(0x1 << 11)
#define RT5640_GP4_OUT_MASK			(0x1 << 10)
#define RT5640_GP4_OUT_SFT			10
#define RT5640_GP4_OUT_LO			(0x0 << 10)
#define RT5640_GP4_OUT_HI			(0x1 << 10)
#define RT5640_GP4_P_MASK			(0x1 << 9)
#define RT5640_GP4_P_SFT			9
#define RT5640_GP4_P_NOR			(0x0 << 9)
#define RT5640_GP4_P_INV			(0x1 << 9)
#define RT5640_GP3_PF_MASK			(0x1 << 8)
#define RT5640_GP3_PF_SFT			8
#define RT5640_GP3_PF_IN			(0x0 << 8)
#define RT5640_GP3_PF_OUT			(0x1 << 8)
#define RT5640_GP3_OUT_MASK			(0x1 << 7)
#define RT5640_GP3_OUT_SFT			7
#define RT5640_GP3_OUT_LO			(0x0 << 7)
#define RT5640_GP3_OUT_HI			(0x1 << 7)
#define RT5640_GP3_P_MASK			(0x1 << 6)
#define RT5640_GP3_P_SFT			6
#define RT5640_GP3_P_NOR			(0x0 << 6)
#define RT5640_GP3_P_INV			(0x1 << 6)
#define RT5640_GP2_PF_MASK			(0x1 << 5)
#define RT5640_GP2_PF_SFT			5
#define RT5640_GP2_PF_IN			(0x0 << 5)
#define RT5640_GP2_PF_OUT			(0x1 << 5)
#define RT5640_GP2_OUT_MASK			(0x1 << 4)
#define RT5640_GP2_OUT_SFT			4
#define RT5640_GP2_OUT_LO			(0x0 << 4)
#define RT5640_GP2_OUT_HI			(0x1 << 4)
#define RT5640_GP2_P_MASK			(0x1 << 3)
#define RT5640_GP2_P_SFT			3
#define RT5640_GP2_P_NOR			(0x0 << 3)
#define RT5640_GP2_P_INV			(0x1 << 3)
#define RT5640_GP1_PF_MASK			(0x1 << 2)
#define RT5640_GP1_PF_SFT			2
#define RT5640_GP1_PF_IN			(0x0 << 2)
#define RT5640_GP1_PF_OUT			(0x1 << 2)
#define RT5640_GP1_OUT_MASK			(0x1 << 1)
#define RT5640_GP1_OUT_SFT			1
#define RT5640_GP1_OUT_LO			(0x0 << 1)
#define RT5640_GP1_OUT_HI			(0x1 << 1)
#define RT5640_GP1_P_MASK			(0x1)
#define RT5640_GP1_P_SFT			0
#define RT5640_GP1_P_NOR			(0x0)
#define RT5640_GP1_P_INV			(0x1)

/* FM34-500 Register Control 1 (0xc4) */
#define RT5640_DSP_ADD_SFT			0

/* FM34-500 Register Control 2 (0xc5) */
#define RT5640_DSP_DAT_SFT			0

/* FM34-500 Register Control 3 (0xc6) */
#define RT5640_DSP_BUSY_MASK			(0x1 << 15)
#define RT5640_DSP_BUSY_BIT			15
#define RT5640_DSP_DS_MASK			(0x1 << 14)
#define RT5640_DSP_DS_SFT			14
#define RT5640_DSP_DS_FM3010			(0x1 << 14)
#define RT5640_DSP_DS_TEMP			(0x1 << 14)
#define RT5640_DSP_CLK_MASK			(0x3 << 12)
#define RT5640_DSP_CLK_SFT			12
#define RT5640_DSP_CLK_384K			(0x0 << 12)
#define RT5640_DSP_CLK_192K			(0x1 << 12)
#define RT5640_DSP_CLK_96K			(0x2 << 12)
#define RT5640_DSP_CLK_64K			(0x3 << 12)
#define RT5640_DSP_PD_PIN_MASK			(0x1 << 11)
#define RT5640_DSP_PD_PIN_SFT			11
#define RT5640_DSP_PD_PIN_LO			(0x0 << 11)
#define RT5640_DSP_PD_PIN_HI			(0x1 << 11)
#define RT5640_DSP_RST_PIN_MASK			(0x1 << 10)
#define RT5640_DSP_RST_PIN_SFT			10
#define RT5640_DSP_RST_PIN_LO			(0x0 << 10)
#define RT5640_DSP_RST_PIN_HI			(0x1 << 10)
#define RT5640_DSP_R_EN				(0x1 << 9)
#define RT5640_DSP_R_EN_BIT			9
#define RT5640_DSP_W_EN				(0x1 << 8)
#define RT5640_DSP_W_EN_BIT			8
#define RT5640_DSP_CMD_MASK			(0xff)
#define RT5640_DSP_CMD_SFT			0
#define RT5640_DSP_CMD_MW			(0x3B)	/* Memory Write */
#define RT5640_DSP_CMD_MR			(0x37)	/* Memory Read */
#define RT5640_DSP_CMD_RR			(0x60)	/* Register Read */
#define RT5640_DSP_CMD_RW			(0x68)	/* Register Write */

/* Programmable Register Array Control 1 (0xc8) */
#define RT5640_REG_SEQ_MASK			(0xf << 12)
#define RT5640_REG_SEQ_SFT			12
#define RT5640_SEQ1_ST_MASK			(0x1 << 11) /*RO*/
#define RT5640_SEQ1_ST_SFT			11
#define RT5640_SEQ1_ST_RUN			(0x0 << 11)
#define RT5640_SEQ1_ST_FIN			(0x1 << 11)
#define RT5640_SEQ2_ST_MASK			(0x1 << 10) /*RO*/
#define RT5640_SEQ2_ST_SFT			10
#define RT5640_SEQ2_ST_RUN			(0x0 << 10)
#define RT5640_SEQ2_ST_FIN			(0x1 << 10)
#define RT5640_REG_LV_MASK			(0x1 << 9)
#define RT5640_REG_LV_SFT			9
#define RT5640_REG_LV_MX			(0x0 << 9)
#define RT5640_REG_LV_PR			(0x1 << 9)
#define RT5640_SEQ_2_PT_MASK			(0x1 << 8)
#define RT5640_SEQ_2_PT_BIT			8
#define RT5640_REG_IDX_MASK			(0xff)
#define RT5640_REG_IDX_SFT			0

/* Programmable Register Array Control 2 (0xc9) */
#define RT5640_REG_DAT_MASK			(0xffff)
#define RT5640_REG_DAT_SFT			0

/* Programmable Register Array Control 3 (0xca) */
#define RT5640_SEQ_DLY_MASK			(0xff << 8)
#define RT5640_SEQ_DLY_SFT			8
#define RT5640_PROG_MASK			(0x1 << 7)
#define RT5640_PROG_SFT				7
#define RT5640_PROG_DIS				(0x0 << 7)
#define RT5640_PROG_EN				(0x1 << 7)
#define RT5640_SEQ1_PT_RUN			(0x1 << 6)
#define RT5640_SEQ1_PT_RUN_BIT			6
#define RT5640_SEQ2_PT_RUN			(0x1 << 5)
#define RT5640_SEQ2_PT_RUN_BIT			5

/* Programmable Register Array Control 4 (0xcb) */
#define RT5640_SEQ1_START_MASK			(0xf << 8)
#define RT5640_SEQ1_START_SFT			8
#define RT5640_SEQ1_END_MASK			(0xf)
#define RT5640_SEQ1_END_SFT			0

/* Programmable Register Array Control 5 (0xcc) */
#define RT5640_SEQ2_START_MASK			(0xf << 8)
#define RT5640_SEQ2_START_SFT			8
#define RT5640_SEQ2_END_MASK			(0xf)
#define RT5640_SEQ2_END_SFT			0

/* Scramble Function (0xcd) */
#define RT5640_SCB_KEY_MASK			(0xff)
#define RT5640_SCB_KEY_SFT			0

/* Scramble Control (0xce) */
#define RT5640_SCB_SWAP_MASK			(0x1 << 15)
#define RT5640_SCB_SWAP_SFT			15
#define RT5640_SCB_SWAP_DIS			(0x0 << 15)
#define RT5640_SCB_SWAP_EN			(0x1 << 15)
#define RT5640_SCB_MASK				(0x1 << 14)
#define RT5640_SCB_SFT				14
#define RT5640_SCB_DIS				(0x0 << 14)
#define RT5640_SCB_EN				(0x1 << 14)

/* Baseback Control (0xcf) */
#define RT5640_BB_MASK				(0x1 << 15)
#define RT5640_BB_SFT				15
#define RT5640_BB_DIS				(0x0 << 15)
#define RT5640_BB_EN				(0x1 << 15)
#define RT5640_BB_CT_MASK			(0x7 << 12)
#define RT5640_BB_CT_SFT			12
#define RT5640_BB_CT_A				(0x0 << 12)
#define RT5640_BB_CT_B				(0x1 << 12)
#define RT5640_BB_CT_C				(0x2 << 12)
#define RT5640_BB_CT_D				(0x3 << 12)
#define RT5640_M_BB_L_MASK			(0x1 << 9)
#define RT5640_M_BB_L_SFT			9
#define RT5640_M_BB_R_MASK			(0x1 << 8)
#define RT5640_M_BB_R_SFT			8
#define RT5640_M_BB_HPF_L_MASK			(0x1 << 7)
#define RT5640_M_BB_HPF_L_SFT			7
#define RT5640_M_BB_HPF_R_MASK			(0x1 << 6)
#define RT5640_M_BB_HPF_R_SFT			6
#define RT5640_G_BB_BST_MASK			(0x3f)
#define RT5640_G_BB_BST_SFT			0

/* MP3 Plus Control 1 (0xd0) */
#define RT5640_M_MP3_L_MASK			(0x1 << 15)
#define RT5640_M_MP3_L_SFT			15
#define RT5640_M_MP3_R_MASK			(0x1 << 14)
#define RT5640_M_MP3_R_SFT			14
#define RT5640_M_MP3_MASK			(0x1 << 13)
#define RT5640_M_MP3_SFT			13
#define RT5640_M_MP3_DIS			(0x0 << 13)
#define RT5640_M_MP3_EN				(0x1 << 13)
#define RT5640_EG_MP3_MASK			(0x1f << 8)
#define RT5640_EG_MP3_SFT			8
#define RT5640_MP3_HLP_MASK			(0x1 << 7)
#define RT5640_MP3_HLP_SFT			7
#define RT5640_MP3_HLP_DIS			(0x0 << 7)
#define RT5640_MP3_HLP_EN			(0x1 << 7)
#define RT5640_M_MP3_ORG_L_MASK			(0x1 << 6)
#define RT5640_M_MP3_ORG_L_SFT			6
#define RT5640_M_MP3_ORG_R_MASK			(0x1 << 5)
#define RT5640_M_MP3_ORG_R_SFT			5

/* MP3 Plus Control 2 (0xd1) */
#define RT5640_MP3_WT_MASK			(0x1 << 13)
#define RT5640_MP3_WT_SFT			13
#define RT5640_MP3_WT_1_4			(0x0 << 13)
#define RT5640_MP3_WT_1_2			(0x1 << 13)
#define RT5640_OG_MP3_MASK			(0x1f << 8)
#define RT5640_OG_MP3_SFT			8
#define RT5640_HG_MP3_MASK			(0x3f)
#define RT5640_HG_MP3_SFT			0

/* 3D HP Control 1 (0xd2) */
#define RT5640_3D_CF_MASK			(0x1 << 15)
#define RT5640_3D_CF_SFT			15
#define RT5640_3D_CF_DIS			(0x0 << 15)
#define RT5640_3D_CF_EN				(0x1 << 15)
#define RT5640_3D_HP_MASK			(0x1 << 14)
#define RT5640_3D_HP_SFT			14
#define RT5640_3D_HP_DIS			(0x0 << 14)
#define RT5640_3D_HP_EN				(0x1 << 14)
#define RT5640_3D_BT_MASK			(0x1 << 13)
#define RT5640_3D_BT_SFT			13
#define RT5640_3D_BT_DIS			(0x0 << 13)
#define RT5640_3D_BT_EN				(0x1 << 13)
#define RT5640_3D_1F_MIX_MASK			(0x3 << 11)
#define RT5640_3D_1F_MIX_SFT			11
#define RT5640_3D_HP_M_MASK			(0x1 << 10)
#define RT5640_3D_HP_M_SFT			10
#define RT5640_3D_HP_M_SUR			(0x0 << 10)
#define RT5640_3D_HP_M_FRO			(0x1 << 10)
#define RT5640_M_3D_HRTF_MASK			(0x1 << 9)
#define RT5640_M_3D_HRTF_SFT			9
#define RT5640_M_3D_D2H_MASK			(0x1 << 8)
#define RT5640_M_3D_D2H_SFT			8
#define RT5640_M_3D_D2R_MASK			(0x1 << 7)
#define RT5640_M_3D_D2R_SFT			7
#define RT5640_M_3D_REVB_MASK			(0x1 << 6)
#define RT5640_M_3D_REVB_SFT			6

/* Adjustable high pass filter control 1 (0xd3) */
#define RT5640_2ND_HPF_MASK			(0x1 << 15)
#define RT5640_2ND_HPF_SFT			15
#define RT5640_2ND_HPF_DIS			(0x0 << 15)
#define RT5640_2ND_HPF_EN			(0x1 << 15)
#define RT5640_HPF_CF_L_MASK			(0x7 << 12)
#define RT5640_HPF_CF_L_SFT			12
#define RT5640_1ST_HPF_MASK			(0x1 << 11)
#define RT5640_1ST_HPF_SFT			11
#define RT5640_1ST_HPF_DIS			(0x0 << 11)
#define RT5640_1ST_HPF_EN			(0x1 << 11)
#define RT5640_HPF_CF_R_MASK			(0x7 << 8)
#define RT5640_HPF_CF_R_SFT			8
#define RT5640_ZD_T_MASK			(0x3 << 6)
#define RT5640_ZD_T_SFT				6
#define RT5640_ZD_F_MASK			(0x3 << 4)
#define RT5640_ZD_F_SFT				4
#define RT5640_ZD_F_IM				(0x0 << 4)
#define RT5640_ZD_F_ZC_IM			(0x1 << 4)
#define RT5640_ZD_F_ZC_IOD			(0x2 << 4)
#define RT5640_ZD_F_UN				(0x3 << 4)

/* HP calibration control and Amp detection (0xd6) */
#define RT5640_SI_DAC_MASK			(0x1 << 11)
#define RT5640_SI_DAC_SFT			11
#define RT5640_SI_DAC_AUTO			(0x0 << 11)
#define RT5640_SI_DAC_TEST			(0x1 << 11)
#define RT5640_DC_CAL_M_MASK			(0x1 << 10)
#define RT5640_DC_CAL_M_SFT			10
#define RT5640_DC_CAL_M_CAL			(0x0 << 10)
#define RT5640_DC_CAL_M_NOR			(0x1 << 10)
#define RT5640_DC_CAL_MASK			(0x1 << 9)
#define RT5640_DC_CAL_SFT			9
#define RT5640_DC_CAL_DIS			(0x0 << 9)
#define RT5640_DC_CAL_EN			(0x1 << 9)
#define RT5640_HPD_RCV_MASK			(0x7 << 6)
#define RT5640_HPD_RCV_SFT			6
#define RT5640_HPD_PS_MASK			(0x1 << 5)
#define RT5640_HPD_PS_SFT			5
#define RT5640_HPD_PS_DIS			(0x0 << 5)
#define RT5640_HPD_PS_EN			(0x1 << 5)
#define RT5640_CAL_M_MASK			(0x1 << 4)
#define RT5640_CAL_M_SFT			4
#define RT5640_CAL_M_DEP			(0x0 << 4)
#define RT5640_CAL_M_CAL			(0x1 << 4)
#define RT5640_CAL_MASK				(0x1 << 3)
#define RT5640_CAL_SFT				3
#define RT5640_CAL_DIS				(0x0 << 3)
#define RT5640_CAL_EN				(0x1 << 3)
#define RT5640_CAL_TEST_MASK			(0x1 << 2)
#define RT5640_CAL_TEST_SFT			2
#define RT5640_CAL_TEST_DIS			(0x0 << 2)
#define RT5640_CAL_TEST_EN			(0x1 << 2)
#define RT5640_CAL_P_MASK			(0x3)
#define RT5640_CAL_P_SFT			0
#define RT5640_CAL_P_NONE			(0x0)
#define RT5640_CAL_P_CAL			(0x1)
#define RT5640_CAL_P_DAC_CAL			(0x2)

/* Soft volume and zero cross control 1 (0xd9) */
#define RT5640_SV_MASK				(0x1 << 15)
#define RT5640_SV_SFT				15
#define RT5640_SV_DIS				(0x0 << 15)
#define RT5640_SV_EN				(0x1 << 15)
#define RT5640_SPO_SV_MASK			(0x1 << 14)
#define RT5640_SPO_SV_SFT			14
#define RT5640_SPO_SV_DIS			(0x0 << 14)
#define RT5640_SPO_SV_EN			(0x1 << 14)
#define RT5640_OUT_SV_MASK			(0x1 << 13)
#define RT5640_OUT_SV_SFT			13
#define RT5640_OUT_SV_DIS			(0x0 << 13)
#define RT5640_OUT_SV_EN			(0x1 << 13)
#define RT5640_HP_SV_MASK			(0x1 << 12)
#define RT5640_HP_SV_SFT			12
#define RT5640_HP_SV_DIS			(0x0 << 12)
#define RT5640_HP_SV_EN				(0x1 << 12)
#define RT5640_ZCD_DIG_MASK			(0x1 << 11)
#define RT5640_ZCD_DIG_SFT			11
#define RT5640_ZCD_DIG_DIS			(0x0 << 11)
#define RT5640_ZCD_DIG_EN			(0x1 << 11)
#define RT5640_ZCD_MASK				(0x1 << 10)
#define RT5640_ZCD_SFT				10
#define RT5640_ZCD_PD				(0x0 << 10)
#define RT5640_ZCD_PU				(0x1 << 10)
#define RT5640_M_ZCD_MASK			(0x3f << 4)
#define RT5640_M_ZCD_SFT			4
#define RT5640_M_ZCD_RM_L			(0x1 << 9)
#define RT5640_M_ZCD_RM_R			(0x1 << 8)
#define RT5640_M_ZCD_SM_L			(0x1 << 7)
#define RT5640_M_ZCD_SM_R			(0x1 << 6)
#define RT5640_M_ZCD_OM_L			(0x1 << 5)
#define RT5640_M_ZCD_OM_R			(0x1 << 4)
#define RT5640_SV_DLY_MASK			(0xf)
#define RT5640_SV_DLY_SFT			0

/* Soft volume and zero cross control 2 (0xda) */
#define RT5640_ZCD_HP_MASK			(0x1 << 15)
#define RT5640_ZCD_HP_SFT			15
#define RT5640_ZCD_HP_DIS			(0x0 << 15)
#define RT5640_ZCD_HP_EN			(0x1 << 15)


/* Codec Private Register definition */
/* 3D Speaker Control (0x63) */
#define RT5640_3D_SPK_MASK			(0x1 << 15)
#define RT5640_3D_SPK_SFT			15
#define RT5640_3D_SPK_DIS			(0x0 << 15)
#define RT5640_3D_SPK_EN			(0x1 << 15)
#define RT5640_3D_SPK_M_MASK			(0x3 << 13)
#define RT5640_3D_SPK_M_SFT			13
#define RT5640_3D_SPK_CG_MASK			(0x1f << 8)
#define RT5640_3D_SPK_CG_SFT			8
#define RT5640_3D_SPK_SG_MASK			(0x1f)
#define RT5640_3D_SPK_SG_SFT			0

/* Wind Noise Detection Control 1 (0x6c) */
#define RT5640_WND_MASK				(0x1 << 15)
#define RT5640_WND_SFT				15
#define RT5640_WND_DIS				(0x0 << 15)
#define RT5640_WND_EN				(0x1 << 15)

/* Wind Noise Detection Control 2 (0x6d) */
#define RT5640_WND_FC_NW_MASK			(0x3f << 10)
#define RT5640_WND_FC_NW_SFT			10
#define RT5640_WND_FC_WK_MASK			(0x3f << 4)
#define RT5640_WND_FC_WK_SFT			4

/* Wind Noise Detection Control 3 (0x6e) */
#define RT5640_HPF_FC_MASK			(0x3f << 6)
#define RT5640_HPF_FC_SFT			6
#define RT5640_WND_FC_ST_MASK			(0x3f)
#define RT5640_WND_FC_ST_SFT			0

/* Wind Noise Detection Control 4 (0x6f) */
#define RT5640_WND_TH_LO_MASK			(0x3ff)
#define RT5640_WND_TH_LO_SFT			0

/* Wind Noise Detection Control 5 (0x70) */
#define RT5640_WND_TH_HI_MASK			(0x3ff)
#define RT5640_WND_TH_HI_SFT			0

/* Wind Noise Detection Control 8 (0x73) */
#define RT5640_WND_WIND_MASK			(0x1 << 13) /* Read-Only */
#define RT5640_WND_WIND_SFT			13
#define RT5640_WND_STRONG_MASK			(0x1 << 12) /* Read-Only */
#define RT5640_WND_STRONG_SFT			12
enum {
	RT5640_NO_WIND,
	RT5640_BREEZE,
	RT5640_STORM,
};

/* Dipole Speaker Interface (0x75) */
#define RT5640_DP_ATT_MASK			(0x3 << 14)
#define RT5640_DP_ATT_SFT			14
#define RT5640_DP_SPK_MASK			(0x1 << 10)
#define RT5640_DP_SPK_SFT			10
#define RT5640_DP_SPK_DIS			(0x0 << 10)
#define RT5640_DP_SPK_EN			(0x1 << 10)

/* EQ Pre Volume Control (0xb3) */
#define RT5640_EQ_PRE_VOL_MASK			(0xffff)
#define RT5640_EQ_PRE_VOL_SFT			0

/* EQ Post Volume Control (0xb4) */
#define RT5640_EQ_PST_VOL_MASK			(0xffff)
#define RT5640_EQ_PST_VOL_SFT			0

#define RT5640_NO_JACK		BIT(0)
#define RT5640_HEADSET_DET	BIT(1)
#define RT5640_HEADPHO_DET	BIT(2)

/* System Clock Source */
#define RT5640_SCLK_S_MCLK	0
#define RT5640_SCLK_S_PLL1	1
#define RT5640_SCLK_S_PLL1_TK	2
#define RT5640_SCLK_S_RCCLK	3

/* PLL1 Source */
#define RT5640_PLL1_S_MCLK	0
#define RT5640_PLL1_S_BCLK1	1
#define RT5640_PLL1_S_BCLK2	2
#define RT5640_PLL1_S_BCLK3	3


enum {
	RT5640_AIF1,
	RT5640_AIF2,
	RT5640_AIF3,
	RT5640_AIFS,
};

enum {
	RT5640_U_IF1 = 0x1,
	RT5640_U_IF2 = 0x2,
	RT5640_U_IF3 = 0x4,
};

enum {
	RT5640_IF_123,
	RT5640_IF_132,
	RT5640_IF_312,
	RT5640_IF_321,
	RT5640_IF_231,
	RT5640_IF_213,
	RT5640_IF_113,
	RT5640_IF_223,
	RT5640_IF_ALL,
};

enum {
	RT5640_DMIC_DIS,
	RT5640_DMIC1,
	RT5640_DMIC2,
};

struct rt5640_priv {
	struct snd_soc_codec *codec;
	struct rt5640_platform_data pdata;
	struct regmap *regmap;

	int sysclk;
	int sysclk_src;
	int lrck[RT5640_AIFS];
	int bclk[RT5640_AIFS];
	int master[RT5640_AIFS];

	int pll_src;
	int pll_in;
	int pll_out;

	bool hp_mute;
};

#endif