summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/mmu.json
blob: 66d83b680651eb823877d831f51955044f60a38a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
[
    {
        "PublicDescription": "Level 2 data translation buffer allocation",
        "EventCode": "0xD800",
        "EventName": "MMU_D_OTB_ALLOC",
        "BriefDescription": "Level 2 data translation buffer allocation"
    },
    {
        "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
        "EventCode": "0xd801",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
        "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
    },
    {
        "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
        "EventCode": "0xd802",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
        "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
    },
    {
        "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
        "EventCode": "0xd803",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
        "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
    },
    {
        "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
        "EventCode": "0xd804",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
        "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
    },
    {
        "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
        "EventCode": "0xd805",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
        "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
    },
    {
        "PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
        "EventCode": "0xd806",
        "EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
        "BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
    },
    {
        "PublicDescrition": "Data-side S1 page walk cache lookup",
        "EventCode": "0xd807",
        "EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
        "BriefDescription": "Data-side S1 page walk cache lookup"
    },
    {
        "PublicDescrition": "Data-side S1 page walk cache refill",
        "EventCode": "0xd808",
        "EventName": "MMU_D_S1_WALK_CACHE_REFILL",
        "BriefDescription": "Data-side S1 page walk cache refill"
    },
    {
        "PublicDescrition": "Data-side S2 page walk cache lookup",
        "EventCode": "0xd809",
        "EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
        "BriefDescription": "Data-side S2 page walk cache lookup"
    },
    {
        "PublicDescrition": "Data-side S2 page walk cache refill",
        "EventCode": "0xd80a",
        "EventName": "MMU_D_S2_WALK_CACHE_REFILL",
        "BriefDescription": "Data-side S2 page walk cache refill"
    },
    {
        "PublicDescription": "Data-side S1 table walk fault",
        "EventCode": "0xD80B",
        "EventName": "MMU_D_S1_WALK_FAULT",
        "BriefDescription": "Data-side S1 table walk fault"
    },
    {
        "PublicDescription": "Data-side S2 table walk fault",
        "EventCode": "0xD80C",
        "EventName": "MMU_D_S2_WALK_FAULT",
        "BriefDescription": "Data-side S2 table walk fault"
    },
    {
        "PublicDescription": "Data-side table walk steps or descriptor fetches",
        "EventCode": "0xD80D",
        "EventName": "MMU_D_WALK_STEPS",
        "BriefDescription": "Data-side table walk steps or descriptor fetches"
    },
    {
        "PublicDescription": "Level 2 instruction translation buffer allocation",
        "EventCode": "0xD900",
        "EventName": "MMU_I_OTB_ALLOC",
        "BriefDescription": "Level 2 instruction translation buffer allocation"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
        "EventCode": "0xd901",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
        "EventCode": "0xd902",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
        "EventCode": "0xd903",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
        "EventCode": "0xd904",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
        "EventCode": "0xd905",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
        "EventCode": "0xd906",
        "EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
        "BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
    },
    {
        "PublicDescrition": "Instruction-side S1 page walk cache lookup",
        "EventCode": "0xd907",
        "EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
        "BriefDescription": "Instruction-side S1 page walk cache lookup"
    },
    {
        "PublicDescrition": "Instruction-side S1 page walk cache refill",
        "EventCode": "0xd908",
        "EventName": "MMU_I_S1_WALK_CACHE_REFILL",
        "BriefDescription": "Instruction-side S1 page walk cache refill"
    },
    {
        "PublicDescrition": "Instruction-side S2 page walk cache lookup",
        "EventCode": "0xd909",
        "EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
        "BriefDescription": "Instruction-side S2 page walk cache lookup"
    },
    {
        "PublicDescrition": "Instruction-side S2 page walk cache refill",
        "EventCode": "0xd90a",
        "EventName": "MMU_I_S2_WALK_CACHE_REFILL",
        "BriefDescription": "Instruction-side S2 page walk cache refill"
    },
    {
        "PublicDescription": "Instruction-side S1 table walk fault",
        "EventCode": "0xD90B",
        "EventName": "MMU_I_S1_WALK_FAULT",
        "BriefDescription": "Instruction-side S1 table walk fault"
    },
    {
        "PublicDescription": "Instruction-side S2 table walk fault",
        "EventCode": "0xD90C",
        "EventName": "MMU_I_S2_WALK_FAULT",
        "BriefDescription": "Instruction-side S2 table walk fault"
    },
    {
        "PublicDescription": "Instruction-side table walk steps or descriptor fetches",
        "EventCode": "0xD90D",
        "EventName": "MMU_I_WALK_STEPS",
        "BriefDescription": "Instruction-side table walk steps or descriptor fetches"
    }
]