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| author | Daniel Golle <daniel@makrotopia.org> | 2023-12-13 05:37:20 +0000 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2024-02-15 19:06:37 +0000 |
| commit | 74a8f416f449be897e763e7f8d94c22c848d8cb9 (patch) | |
| tree | 7e7869f89907432fcbaa0f9d01d885a4d97407af | |
| parent | 54f99ebe5cceccafcc85bc0486a4b06c78bc9dd0 (diff) | |
| download | openwrt-74a8f416f449be897e763e7f8d94c22c848d8cb9.tar.gz openwrt-74a8f416f449be897e763e7f8d94c22c848d8cb9.tar.bz2 openwrt-74a8f416f449be897e763e7f8d94c22c848d8cb9.zip | |
uboot-mediatek: update to U-Boot 2024.01 release
Rebase local patches on top of quarterly timed release, allowing to
drop numerous patches which have been accepted upstream since the
release of U-Boot 2023.07.02.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
69 files changed, 171 insertions, 10550 deletions
diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 9b421d2999..2a4d5481b8 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,8 +1,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.07.02 -PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5 +PKG_VERSION:=2024.01 +PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host UBOOT_USE_INTREE_DTC:=1 diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch index 60eda91124..dcbf8b953f 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch +++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch @@ -18,9 +18,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x280000 - CONFIG_SYS_PROMPT="MT7622> " CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 + CONFIG_SYS_LOAD_ADDR=0x4007ff28 @@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y diff --git a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch b/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch deleted file mode 100644 index d5f6f73762..0000000000 --- a/package/boot/uboot-mediatek/patches/100-00-clk-remove-log_ret-from-clk_get_rate.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 19f2aa053d5531a9ca0ece04dca172a522d58b90 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Fri, 29 Jul 2022 11:32:28 +0800 -Subject: [PATCH 32/71] clk: remove log_ret from clk_get_rate - -The return value of clk_get_rate is ulong, an unsigned type. The size of -ulong depends on the cpu architecture, i.e. 4 bytes on 32-bit CPUs and -8 bytes on 64-bit CPUs. - -However log_ret only accepts and returns value in int type, a fixed 4-byte -type. This may truncate the real clock value and cause unexpected error on -64-bit platforms. - -This patch removes log_ret to solve this issue. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/clk/clk-uclass.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/drivers/clk/clk-uclass.c -+++ b/drivers/clk/clk-uclass.c -@@ -471,7 +471,6 @@ void clk_free(struct clk *clk) - ulong clk_get_rate(struct clk *clk) - { - const struct clk_ops *ops; -- int ret; - - debug("%s(clk=%p)\n", __func__, clk); - if (!clk_valid(clk)) -@@ -481,11 +480,7 @@ ulong clk_get_rate(struct clk *clk) - if (!ops->get_rate) - return -ENOSYS; - -- ret = ops->get_rate(clk); -- if (ret) -- return log_ret(ret); -- -- return 0; -+ return ops->get_rate(clk); - } - - struct clk *clk_get_parent(struct clk *clk) diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch index da87978aef..9b02b4dc63 100644 --- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch +++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch @@ -17,37 +17,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 7 files changed, 299 insertions(+), 3 deletions(-) create mode 100644 env/mtd.c ---- a/cmd/nvedit.c -+++ b/cmd/nvedit.c -@@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; - defined(CONFIG_ENV_IS_IN_MMC) || \ - defined(CONFIG_ENV_IS_IN_FAT) || \ - defined(CONFIG_ENV_IS_IN_EXT4) || \ -+ defined(CONFIG_ENV_IS_IN_MTD) || \ - defined(CONFIG_ENV_IS_IN_NAND) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) || \ - defined(CONFIG_ENV_IS_IN_ONENAND) || \ -@@ -61,7 +62,7 @@ DECLARE_GLOBAL_DATA_PTR; - - #if !defined(ENV_IS_IN_DEVICE) && \ - !defined(CONFIG_ENV_IS_NOWHERE) --# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\ -+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\ - NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE - #endif - --- a/env/Kconfig +++ b/env/Kconfig -@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE +@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ - !ENV_IS_IN_UBI + !ENV_IS_IN_UBI && !ENV_IS_IN_MTD - help - Define this if you don't want to or can't have an environment stored - on a storage medium. In this case the environment will still exist -@@ -251,6 +251,27 @@ config ENV_IS_IN_MMC + select ENV_IS_NOWHERE + + config ENV_IS_NOWHERE +@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant". CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used. @@ -75,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config ENV_IS_IN_NAND bool "Environment in a NAND device" depends on !CHAIN_OF_TRUST -@@ -558,10 +579,16 @@ config ENV_ADDR_REDUND +@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND Offset from the start of the device (or partition) of the redundant environment location. @@ -93,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0xF0000 if ARCH_SUNXI -@@ -609,6 +636,12 @@ config ENV_SECT_SIZE +@@ -622,6 +649,12 @@ config ENV_SECT_SIZE help Size of the sector containing the environment. @@ -118,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o --- a/env/env.c +++ b/env/env.c -@@ -69,6 +69,9 @@ static enum env_location env_locations[] +@@ -46,6 +46,9 @@ static enum env_location env_locations[] #ifdef CONFIG_ENV_IS_IN_MMC ENVL_MMC, #endif diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch index 93fc32cf9e..da4dce917b 100644 --- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/common/board_r.c +++ b/common/board_r.c -@@ -388,6 +388,20 @@ static int initr_nand(void) +@@ -373,6 +373,20 @@ static int initr_nand(void) } #endif @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ static int initr_onenand(void) -@@ -696,6 +710,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch index 35d8f115f6..4eb2bc9ccf 100644 --- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1353,6 +1353,12 @@ config CMD_NAND_TORTURE +@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> depends on NVME --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o +@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch index 6336fb33f5..c6358f3287 100644 --- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch +++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch @@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> #ifdef CONFIG_AUTO_COMPLETE static int mtd_name_complete(int argc, char *const argv[], char last_char, int maxv, char *cmdv[]) -@@ -552,6 +588,7 @@ static char mtd_help_text[] = +@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd, "\n" "Specific functions:\n" "mtd bad <name>\n" @@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> "\n" "With:\n" "\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n" -@@ -577,4 +614,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" +@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase, mtd_name_complete), U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad, diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch index 0b4ee32b62..dbb1e2e59d 100644 --- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch +++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch @@ -17,37 +17,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 7 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 env/nmbm.c ---- a/cmd/nvedit.c -+++ b/cmd/nvedit.c -@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; - defined(CONFIG_ENV_IS_IN_EXT4) || \ - defined(CONFIG_ENV_IS_IN_MTD) || \ - defined(CONFIG_ENV_IS_IN_NAND) || \ -+ defined(CONFIG_ENV_IS_IN_NMBM) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) || \ - defined(CONFIG_ENV_IS_IN_ONENAND) || \ - defined(CONFIG_ENV_IS_IN_SPI_FLASH) || \ -@@ -63,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR; - #if !defined(ENV_IS_IN_DEVICE) && \ - !defined(CONFIG_ENV_IS_NOWHERE) - # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\ --NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE -+NAND|NMBM|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE - #endif - - /* --- a/env/Kconfig +++ b/env/Kconfig -@@ -62,7 +62,7 @@ config ENV_IS_NOWHERE +@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT + def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ + !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \ !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ ++ !ENV_IS_IN_NMBM && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ -- !ENV_IS_IN_UBI && !ENV_IS_IN_MTD -+ !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD - help - Define this if you don't want to or can't have an environment stored - on a storage medium. In this case the environment will still exist -@@ -312,6 +312,21 @@ config ENV_RANGE + !ENV_IS_IN_UBI && !ENV_IS_IN_MTD +@@ -315,6 +316,21 @@ config ENV_RANGE Specifying a range with more erase blocks than are needed to hold CONFIG_ENV_SIZE allows bad blocks within the range to be avoided. @@ -69,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config ENV_IS_IN_NVRAM bool "Environment in a non-volatile RAM" depends on !CHAIN_OF_TRUST -@@ -588,7 +603,7 @@ config ENV_MTD_NAME +@@ -591,7 +607,7 @@ config ENV_MTD_NAME config ENV_OFFSET hex "Environment offset" depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ @@ -90,7 +70,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/env/env.c +++ b/env/env.c -@@ -75,6 +75,9 @@ static enum env_location env_locations[] +@@ -52,6 +52,9 @@ static enum env_location env_locations[] #ifdef CONFIG_ENV_IS_IN_NAND ENVL_NAND, #endif diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch index f3831e07f7..e6e12ae24c 100644 --- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1353,6 +1353,14 @@ config CMD_NAND_TORTURE +@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> bool "nmbm" --- a/cmd/Makefile +++ b/cmd/Makefile -@@ -125,6 +125,7 @@ obj-y += legacy-mtd-utils.o +@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o endif obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch index d9a645d20e..da09cd9c08 100644 --- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -2848,6 +2848,100 @@ static int spi_nor_init_params(struct sp +@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp return 0; } @@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) { size_t i; -@@ -4045,6 +4139,7 @@ int spi_nor_scan(struct spi_nor *nor) +@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->write = spi_nor_write_data; nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg; diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch index ce59cc73ae..f7cbd8d052 100644 --- a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch @@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/sf.c +++ b/cmd/sf.c -@@ -407,6 +407,14 @@ static int do_spi_protect(int argc, char +@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char return ret == 0 ? 0 : 1; } @@ -27,22 +27,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> enum { STAGE_ERASE, STAGE_CHECK, -@@ -601,6 +609,8 @@ static int do_spi_flash(struct cmd_tbl * +@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl * ret = do_spi_flash_erase(argc, argv); - else if (strcmp(cmd, "protect") == 0) + else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0) ret = do_spi_protect(argc, argv); + else if (strcmp(cmd, "uuid") == 0) + ret = do_spi_flash_read_uuid(); else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); else -@@ -626,7 +636,8 @@ static const char long_help[] = - " at `addr' to flash at `offset'\n" - " or to start of mtd `partition'\n" - "sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n" -- " at address 'sector'" -+ " at address 'sector'\n" -+ "sf uuid - read uuid from flash" +@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf, #ifdef CONFIG_CMD_SF_TEST "\nsf test offset len - run a very basic destructive test" #endif ++ "sf uuid - read uuid from flash" + ); + + U_BOOT_CMD( diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch index 315f7f92a3..0438895fdb 100644 --- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch @@ -255,15 +255,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> }; /** enum bootmenu_key - keys that can be returned by the bootmenu */ -@@ -54,6 +59,7 @@ enum bootmenu_key { - BKEY_MINUS, - BKEY_SPACE, +@@ -51,6 +56,7 @@ enum bootmenu_key { + BKEY_SELECT, + BKEY_QUIT, BKEY_SAVE, + BKEY_CHOICE, - BKEY_COUNT, - }; -@@ -76,7 +82,7 @@ enum bootmenu_key { + /* 'extra' keys, which are used by menus but not cedit */ + BKEY_PLUS, +@@ -81,7 +87,7 @@ enum bootmenu_key { * anything else: KEY_NONE */ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, @@ -272,7 +272,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> /** * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled -@@ -102,7 +108,7 @@ enum bootmenu_key bootmenu_autoboot_loop +@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop * Space: BKEY_SPACE */ enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, @@ -281,7 +281,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> /** * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key -@@ -110,6 +116,7 @@ enum bootmenu_key bootmenu_loop(struct b +@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b * @ichar: Keypress to convert (ASCII, including control characters) * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none */ @@ -301,7 +301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> switch (key) { case BKEY_UP: -@@ -1937,7 +1937,7 @@ char *eficonfig_choice_change_boot_order +@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order cli_ch_init(cch); while (1) { @@ -312,7 +312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> case BKEY_PLUS: --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c -@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri +@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri key = 0; if (ichar) { diff --git a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch index 149a156ba2..f017ce92ad 100644 --- a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch +++ b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c -@@ -16,7 +16,11 @@ +@@ -17,7 +17,11 @@ uint32_t __weak spl_nand_get_uboot_raw_page(void) { diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index 93a940b943..ef20c2dfb6 100644 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> reg = <0x11014000 0x1000>; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME +@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 default "lk=1" if TARGET_MT7623 +source "board/mediatek/mt7629/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch index cb3f1ff2af..9dc1a57722 100644 --- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1308,6 +1308,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt7981-rfb.dtb \ diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch index bd68677eb0..15e943b1c0 100644 --- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch +++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor +@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: @@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -468,6 +474,16 @@ const struct flash_info spi_nor_ids[] = +@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { @@ -62,7 +62,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -517,6 +533,11 @@ const struct flash_info spi_nor_ids[] = +@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch index 0e233bb1d2..20489d8726 100644 --- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch +++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -20,66 +20,17 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 10 files changed, 923 insertions(+), 225 deletions(-) create mode 100644 drivers/mtd/nand/spi/etron.c ---- a/drivers/mtd/nand/spi/Kconfig -+++ b/drivers/mtd/nand/spi/Kconfig -@@ -5,3 +5,4 @@ menuconfig MTD_SPI_NAND - select SPI_MEM - help - This is the framework for the SPI NAND device drivers. -+ --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o -+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o +-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o ++spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -17,6 +17,7 @@ - #include <linux/mtd/spinand.h> - #include <linux/of.h> - #include <linux/slab.h> -+#include <linux/string.h> - #include <linux/spi/spi.h> - #include <linux/spi/spi-mem.h> - #else -@@ -451,10 +452,11 @@ out: - return status & STATUS_BUSY ? -ETIMEDOUT : 0; - } - --static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) -+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, -+ u8 ndummy, u8 *buf) - { -- struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, -- SPINAND_MAX_ID_LEN); -+ struct spi_mem_op op = SPINAND_READID_OP( -+ naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); - int ret; - - ret = spi_mem_exec_op(spinand->slave, &op); -@@ -464,18 +466,6 @@ static int spinand_read_id_op(struct spi - return ret; - } - --static int spinand_reset_op(struct spinand_device *spinand) --{ -- struct spi_mem_op op = SPINAND_RESET_OP; -- int ret; -- -- ret = spi_mem_exec_op(spinand->slave, &op); -- if (ret) -- return ret; -- -- return spinand_wait(spinand, NULL); --} -- - static int spinand_lock_block(struct spinand_device *spinand, u8 lock) - { - return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); -@@ -829,6 +819,7 @@ static const struct nand_ops spinand_ops +@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops }; static const struct spinand_manufacturer *spinand_manufacturers[] = { @@ -87,140 +38,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> &gigadevice_spinand_manufacturer, ¯onix_spinand_manufacturer, µn_spinand_manufacturer, -@@ -836,24 +827,63 @@ static const struct spinand_manufacturer - &winbond_spinand_manufacturer, - }; - --static int spinand_manufacturer_detect(struct spinand_device *spinand) -+static int spinand_manufacturer_match(struct spinand_device *spinand, -+ enum spinand_readid_method rdid_method) - { -+ u8 *id = spinand->id.data; - unsigned int i; - int ret; - - for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { -- ret = spinand_manufacturers[i]->ops->detect(spinand); -- if (ret > 0) { -- spinand->manufacturer = spinand_manufacturers[i]; -- return 0; -- } else if (ret < 0) { -- return ret; -- } -+ const struct spinand_manufacturer *manufacturer = -+ spinand_manufacturers[i]; -+ -+ if (id[0] != manufacturer->id) -+ continue; -+ -+ ret = spinand_match_and_init(spinand, -+ manufacturer->chips, -+ manufacturer->nchips, -+ rdid_method); -+ if (ret < 0) -+ continue; -+ -+ spinand->manufacturer = manufacturer; -+ return 0; - } - - return -ENOTSUPP; - } - -+static int spinand_id_detect(struct spinand_device *spinand) -+{ -+ u8 *id = spinand->id.data; -+ int ret; -+ -+ ret = spinand_read_id_op(spinand, 0, 0, id); -+ if (ret) -+ return ret; -+ ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); -+ if (!ret) -+ return 0; -+ -+ ret = spinand_read_id_op(spinand, 1, 0, id); -+ if (ret) -+ return ret; -+ ret = spinand_manufacturer_match(spinand, -+ SPINAND_READID_METHOD_OPCODE_ADDR); -+ if (!ret) -+ return 0; -+ -+ ret = spinand_read_id_op(spinand, 0, 1, id); -+ if (ret) -+ return ret; -+ ret = spinand_manufacturer_match(spinand, -+ SPINAND_READID_METHOD_OPCODE_DUMMY); -+ -+ return ret; -+} -+ - static int spinand_manufacturer_init(struct spinand_device *spinand) - { - if (spinand->manufacturer->ops->init) -@@ -909,9 +939,9 @@ spinand_select_op_variant(struct spinand - * @spinand: SPI NAND object - * @table: SPI NAND device description table - * @table_size: size of the device description table -+ * @rdid_method: read id method to match - * -- * Should be used by SPI NAND manufacturer drivers when they want to find a -- * match between a device ID retrieved through the READ_ID command and an -+ * Match between a device ID retrieved through the READ_ID command and an - * entry in the SPI NAND description table. If a match is found, the spinand - * object will be initialized with information provided by the matching - * spinand_info entry. -@@ -920,8 +950,10 @@ spinand_select_op_variant(struct spinand - */ - int spinand_match_and_init(struct spinand_device *spinand, - const struct spinand_info *table, -- unsigned int table_size, u8 devid) -+ unsigned int table_size, -+ enum spinand_readid_method rdid_method) - { -+ u8 *id = spinand->id.data; - struct nand_device *nand = spinand_to_nand(spinand); - unsigned int i; - -@@ -929,13 +961,17 @@ int spinand_match_and_init(struct spinan - const struct spinand_info *info = &table[i]; - const struct spi_mem_op *op; - -- if (devid != info->devid) -+ if (rdid_method != info->devid.method) -+ continue; -+ -+ if (memcmp(id + 1, info->devid.id, info->devid.len)) - continue; - - nand->memorg = table[i].memorg; - nand->eccreq = table[i].eccreq; - spinand->eccinfo = table[i].eccinfo; - spinand->flags = table[i].flags; -+ spinand->id.len = 1 + table[i].devid.len; - spinand->select_target = table[i].select_target; - - op = spinand_select_op_variant(spinand, -@@ -967,17 +1003,7 @@ static int spinand_detect(struct spinand - struct nand_device *nand = spinand_to_nand(spinand); - int ret; - -- ret = spinand_reset_op(spinand); -- if (ret) -- return ret; -- -- ret = spinand_read_id_op(spinand, spinand->id.data); -- if (ret) -- return ret; -- -- spinand->id.len = SPINAND_MAX_ID_LEN; -- -- ret = spinand_manufacturer_detect(spinand); -+ ret = spinand_id_detect(spinand); - if (ret) { - dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n", - spinand->id.data[0], spinand->id.data[1], --- /dev/null +++ b/drivers/mtd/nand/spi/etron.c @@ -0,0 +1,181 @@ @@ -320,7 +137,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + /* EM73C 1Gb 3.3V */ + SPINAND_INFO("EM73C044VCF", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -330,7 +147,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + /* EM7xD 2Gb */ + SPINAND_INFO("EM73D044VCR", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -339,7 +156,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), + SPINAND_INFO("EM73D044VCO", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -348,7 +165,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), + SPINAND_INFO("EM78D044VCM", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -358,7 +175,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + /* EM7xE 4Gb */ + SPINAND_INFO("EM73E044VCE", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -367,7 +184,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), + SPINAND_INFO("EM78E044VCD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -377,7 +194,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + /* EM7xF044VCA 8Gb */ + SPINAND_INFO("EM73F044VCA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), -+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -386,7 +203,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), + SPINAND_INFO("EM78F044VCA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D), -+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -407,45 +224,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +}; --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -22,8 +22,13 @@ - - #define GD5FXGQXXEXXG_REG_STATUS2 0xf0 - -+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) -+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) -+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4) -+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) -+ - /* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */ --static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants, -+static SPINAND_OP_VARIANTS(read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), -@@ -31,8 +36,17 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read - SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); +@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); --/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ --static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, -+static SPINAND_OP_VARIANTS(read_cache_variants_f, -+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); -+ -+/* For Q5 devices, QUADIO use different dummy byte settings */ +/* Q5 1Gb */ +static SPINAND_OP_VARIANTS(dummy2_read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), -@@ -40,6 +54,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read - SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); - ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ +/* Q5 2Gb & 4Gb */ +static SPINAND_OP_VARIANTS(dummy4_read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), @@ -458,124 +249,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static SPINAND_OP_VARIANTS(write_cache_variants, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)); -@@ -48,7 +71,65 @@ static SPINAND_OP_VARIANTS(update_cache_ - SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), - SPINAND_PROG_LOAD(false, 0, NULL, 0)); - --static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section, -+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ if (section) { -+ region->offset = 16 * section; -+ region->length = 8; -+ } else { -+ /* section 0 has one byte reserved for bad block mark */ -+ region->offset = 1; -+ region->length = 7; -+ } -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = { -+ .ecc = gd5fxgq4xa_ooblayout_ecc, -+ .rfree = gd5fxgq4xa_ooblayout_free, -+}; -+ -+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand, -+ u8 status) -+{ -+ switch (status & STATUS_ECC_MASK) { -+ case STATUS_ECC_NO_BITFLIPS: -+ return 0; -+ -+ case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS: -+ /* 1-7 bits are flipped. return the maximum. */ -+ return 7; -+ -+ case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS: -+ return 8; -+ -+ case STATUS_ECC_UNCOR_ERROR: -+ return -EBADMSG; -+ -+ default: -+ break; -+ } -+ -+ return -EINVAL; -+} -+ -+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) - { - if (section) -@@ -60,7 +141,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(s - return 0; - } - --static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section, -+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) - { - if (section) -@@ -73,7 +154,13 @@ static int gd5fxgqxxexxg_ooblayout_free( - return 0; - } - --static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand, -+/* Valid for Q4/Q5 and Q6 (untested) devices */ -+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { -+ .ecc = gd5fxgqx_variant2_ooblayout_ecc, -+ .rfree = gd5fxgqx_variant2_ooblayout_free, -+}; -+ -+static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, - u8 status) - { - u8 status2; -@@ -152,59 +239,214 @@ static int gd5fxgq5xexxg_ecc_get_status( +@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status( return -EINVAL; } --static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = { -- .ecc = gd5fxgqxxexxg_ooblayout_ecc, -- .rfree = gd5fxgqxxexxg_ooblayout_free, -+static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, -+ u8 status) -+{ -+ switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) { -+ case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS: -+ return 0; -+ -+ case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS: -+ return 3; -+ -+ case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR: -+ return -EBADMSG; -+ -+ default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */ -+ return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2; -+ } -+ -+ return -EINVAL; -+} -+ +static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ @@ -603,90 +280,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +static const struct mtd_ooblayout_ops esmt_1_ooblayout = { + .ecc = esmt_1_ooblayout_ecc, + .rfree = esmt_1_ooblayout_free, - }; - ++ }; ++ static const struct spinand_info gigadevice_spinand_table[] = { -- SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, -- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + SPINAND_INFO("F50L1G41LB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), -- SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants, -+ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, - &write_cache_variants, - &update_cache_variants), - 0, -- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, -- gd5fxgq4xexxg_ecc_get_status)), -- SPINAND_INFO("GD5F1GQ5UExxG", 0x51, -+ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)), -+ SPINAND_INFO("GD5F1GQ4xA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, -+ gd5fxgq4xa_ecc_get_status)), -+ SPINAND_INFO("GD5F2GQ4xA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, -+ gd5fxgq4xa_ecc_get_status)), -+ SPINAND_INFO("GD5F4GQ4xA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), -+ NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, -+ gd5fxgq4xa_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ4UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ4UFxxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4ufxxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ5UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(4, 512), -- SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, - &write_cache_variants, - &update_cache_variants), -- 0, -- SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)), + SPINAND_INFO("GD5F1GQ4xA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), +@@ -349,6 +405,87 @@ static const struct spinand_info gigadev + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F2GQ5UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, + &write_cache_variants, @@ -696,7 +311,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F4GQ6UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, + &write_cache_variants, @@ -706,7 +321,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GM7UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -716,7 +331,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F2GM7UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -726,7 +341,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F4GM8UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -736,7 +351,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ5UExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, + &write_cache_variants, @@ -746,7 +361,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F2GQ5UExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, + &write_cache_variants, @@ -756,600 +371,21 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + gd5fxgq5xexxg_ecc_get_status)), + SPINAND_INFO("GD5F4GQ6UExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), -+ NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq5xexxg_ecc_get_status)), - }; - --static int gigadevice_spinand_detect(struct spinand_device *spinand) --{ -- u8 *id = spinand->id.data; -- int ret; -- -- /* -- * For GD NANDs, There is an address byte needed to shift in before IDs -- * are read out, so the first byte in raw_id is dummy. -- */ -- if (id[1] != SPINAND_MFR_GIGADEVICE) -- return 0; -- -- ret = spinand_match_and_init(spinand, gigadevice_spinand_table, -- ARRAY_SIZE(gigadevice_spinand_table), -- id[2]); -- if (ret) -- return ret; -- -- return 1; --} -- - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { -- .detect = gigadevice_spinand_detect, - }; - - const struct spinand_manufacturer gigadevice_spinand_manufacturer = { - .id = SPINAND_MFR_GIGADEVICE, - .name = "GigaDevice", -+ .chips = gigadevice_spinand_table, -+ .nchips = ARRAY_SIZE(gigadevice_spinand_table), - .ops = &gigadevice_spinand_manuf_ops, - }; ---- a/drivers/mtd/nand/spi/macronix.c -+++ b/drivers/mtd/nand/spi/macronix.c -@@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(s - } - - static const struct spinand_info macronix_spinand_table[] = { -- SPINAND_INFO("MX35LF1GE4AB", 0x12, -+ SPINAND_INFO("MX35LF1GE4AB", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), - NAND_ECCREQ(4, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -114,7 +115,8 @@ static const struct spinand_info macroni - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), -- SPINAND_INFO("MX35LF2GE4AB", 0x22, -+ SPINAND_INFO("MX35LF2GE4AB", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), - NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), - NAND_ECCREQ(4, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -122,7 +124,96 @@ static const struct spinand_info macroni - &update_cache_variants), - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), -- SPINAND_INFO("MX35UF4GE4AD", 0xb7, -+ SPINAND_INFO("MX35LF2GE4AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35LF4GE4AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37), -+ NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35LF1G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), -+ SPINAND_INFO("MX35LF2G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), -+ SPINAND_INFO("MX35LF4G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), -+ NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), -+ SPINAND_INFO("MX31LF1GE4BC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX31UF1GE4BC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), ++ gd5fxgq5xexxg_ecc_get_status)), + -+ SPINAND_INFO("MX35LF2G14AC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF4G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5), -+ NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF4GE4AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -131,7 +222,28 @@ static const struct spinand_info macroni - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), -- SPINAND_INFO("MX35UF2GE4AD", 0xa6, -+ SPINAND_INFO("MX35UF2G14AC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF2G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF2GE4AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6), - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -140,16 +252,28 @@ static const struct spinand_info macroni - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), -- SPINAND_INFO("MX35UF2GE4AC", 0xa2, -+ SPINAND_INFO("MX35UF2GE4AC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2), - NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), - NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF1G14AC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(4, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, - &write_cache_variants, - &update_cache_variants), - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), -- SPINAND_INFO("MX35UF1GE4AD", 0x96, -+ SPINAND_INFO("MX35UF1G24AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -158,7 +282,18 @@ static const struct spinand_info macroni - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), -- SPINAND_INFO("MX35UF1GE4AC", 0x92, -+ SPINAND_INFO("MX35UF1GE4AD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, -+ mx35lf1ge4ab_ecc_get_status)), -+ SPINAND_INFO("MX35UF1GE4AC", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), - NAND_ECCREQ(4, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -170,33 +305,13 @@ static const struct spinand_info macroni - - }; - --static int macronix_spinand_detect(struct spinand_device *spinand) --{ -- u8 *id = spinand->id.data; -- int ret; -- -- /* -- * Macronix SPI NAND read ID needs a dummy byte, so the first byte in -- * raw_id is garbage. -- */ -- if (id[1] != SPINAND_MFR_MACRONIX) -- return 0; -- -- ret = spinand_match_and_init(spinand, macronix_spinand_table, -- ARRAY_SIZE(macronix_spinand_table), -- id[2]); -- if (ret) -- return ret; -- -- return 1; --} -- - static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { -- .detect = macronix_spinand_detect, - }; - - const struct spinand_manufacturer macronix_spinand_manufacturer = { - .id = SPINAND_MFR_MACRONIX, - .name = "Macronix", -+ .chips = macronix_spinand_table, -+ .nchips = ARRAY_SIZE(macronix_spinand_table), - .ops = ¯onix_spinand_manuf_ops, }; ---- a/drivers/mtd/nand/spi/micron.c -+++ b/drivers/mtd/nand/spi/micron.c -@@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struc - static const struct spinand_info micron_spinand_table[] = { - /* M79A 2Gb 3.3V */ -- SPINAND_INFO("MT29F2G01ABAGD", 0x24, -+ SPINAND_INFO("MT29F2G01ABAGD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -130,7 +131,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M79A 2Gb 1.8V */ -- SPINAND_INFO("MT29F2G01ABBGD", 0x25, -+ SPINAND_INFO("MT29F2G01ABBGD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -140,7 +142,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M78A 1Gb 3.3V */ -- SPINAND_INFO("MT29F1G01ABAFD", 0x14, -+ SPINAND_INFO("MT29F1G01ABAFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -150,7 +153,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M78A 1Gb 1.8V */ -- SPINAND_INFO("MT29F1G01ABAFD", 0x15, -+ SPINAND_INFO("MT29F1G01ABAFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -160,7 +164,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M79A 4Gb 3.3V */ -- SPINAND_INFO("MT29F4G01ADAGD", 0x36, -+ SPINAND_INFO("MT29F4G01ADAGD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), - NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -171,7 +176,8 @@ static const struct spinand_info micron_ - micron_8_ecc_get_status), - SPINAND_SELECT_TARGET(micron_select_target)), - /* M70A 4Gb 3.3V */ -- SPINAND_INFO("MT29F4G01ABAFD", 0x34, -+ SPINAND_INFO("MT29F4G01ABAFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -181,7 +187,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M70A 4Gb 1.8V */ -- SPINAND_INFO("MT29F4G01ABBFD", 0x35, -+ SPINAND_INFO("MT29F4G01ABBFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -191,7 +198,8 @@ static const struct spinand_info micron_ - SPINAND_ECCINFO(µn_8_ooblayout, - micron_8_ecc_get_status)), - /* M70A 8Gb 3.3V */ -- SPINAND_INFO("MT29F8G01ADAFD", 0x46, -+ SPINAND_INFO("MT29F8G01ADAFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -202,7 +210,8 @@ static const struct spinand_info micron_ - micron_8_ecc_get_status), - SPINAND_SELECT_TARGET(micron_select_target)), - /* M70A 8Gb 1.8V */ -- SPINAND_INFO("MT29F8G01ADBFD", 0x47, -+ SPINAND_INFO("MT29F8G01ADBFD", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -214,26 +223,6 @@ static const struct spinand_info micron_ - SPINAND_SELECT_TARGET(micron_select_target)), - }; - --static int micron_spinand_detect(struct spinand_device *spinand) --{ -- u8 *id = spinand->id.data; -- int ret; -- -- /* -- * Micron SPI NAND read ID need a dummy byte, -- * so the first byte in raw_id is dummy. -- */ -- if (id[1] != SPINAND_MFR_MICRON) -- return 0; -- -- ret = spinand_match_and_init(spinand, micron_spinand_table, -- ARRAY_SIZE(micron_spinand_table), id[2]); -- if (ret) -- return ret; -- -- return 1; --} -- - static int micron_spinand_init(struct spinand_device *spinand) - { - /* -@@ -248,12 +237,13 @@ static int micron_spinand_init(struct sp - } - - static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { -- .detect = micron_spinand_detect, - .init = micron_spinand_init, - }; - - const struct spinand_manufacturer micron_spinand_manufacturer = { - .id = SPINAND_MFR_MICRON, - .name = "Micron", -+ .chips = micron_spinand_table, -+ .nchips = ARRAY_SIZE(micron_spinand_table), - .ops = µn_spinand_manuf_ops, - }; ---- a/drivers/mtd/nand/spi/toshiba.c -+++ b/drivers/mtd/nand/spi/toshiba.c -@@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status - - static const struct spinand_info toshiba_spinand_table[] = { - /* 3.3V 1Gb (1st generation) */ -- SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2, -+ SPINAND_INFO("TC58CVG0S3HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -121,7 +122,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 3.3V 2Gb (1st generation) */ -- SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB, -+ SPINAND_INFO("TC58CVG1S3HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -131,7 +133,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 3.3V 4Gb (1st generation) */ -- SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD, -+ SPINAND_INFO("TC58CVG2S0HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -141,7 +144,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 1Gb (1st generation) */ -- SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2, -+ SPINAND_INFO("TC58CYG0S3HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -151,7 +155,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 2Gb (1st generation) */ -- SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB, -+ SPINAND_INFO("TC58CYG1S3HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -161,7 +166,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 4Gb (1st generation) */ -- SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD, -+ SPINAND_INFO("TC58CYG2S0HRAIG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -176,7 +182,8 @@ static const struct spinand_info toshiba - * QE_BIT. - */ - /* 3.3V 1Gb (2nd generation) */ -- SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2, -+ SPINAND_INFO("TC58CVG0S3HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -186,7 +193,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 3.3V 2Gb (2nd generation) */ -- SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB, -+ SPINAND_INFO("TC58CVG1S3HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -196,7 +204,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 3.3V 4Gb (2nd generation) */ -- SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED, -+ SPINAND_INFO("TC58CVG2S0HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -206,7 +215,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 3.3V 8Gb (2nd generation) */ -- SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4, -+ SPINAND_INFO("TH58CVG3S0HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), - NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -216,7 +226,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 1Gb (2nd generation) */ -- SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2, -+ SPINAND_INFO("TC58CYG0S3HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -226,7 +237,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 2Gb (2nd generation) */ -- SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB, -+ SPINAND_INFO("TC58CYG1S3HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), - NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -236,7 +248,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 4Gb (2nd generation) */ -- SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD, -+ SPINAND_INFO("TC58CYG2S0HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), - NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -246,7 +259,8 @@ static const struct spinand_info toshiba - SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, - tx58cxgxsxraix_ecc_get_status)), - /* 1.8V 8Gb (2nd generation) */ -- SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4, -+ SPINAND_INFO("TH58CYG3S0HRAIJ", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), - NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), - NAND_ECCREQ(8, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -257,33 +271,13 @@ static const struct spinand_info toshiba - tx58cxgxsxraix_ecc_get_status)), - }; - --static int toshiba_spinand_detect(struct spinand_device *spinand) --{ -- u8 *id = spinand->id.data; -- int ret; -- -- /* -- * Toshiba SPI NAND read ID needs a dummy byte, -- * so the first byte in id is garbage. -- */ -- if (id[1] != SPINAND_MFR_TOSHIBA) -- return 0; -- -- ret = spinand_match_and_init(spinand, toshiba_spinand_table, -- ARRAY_SIZE(toshiba_spinand_table), -- id[2]); -- if (ret) -- return ret; -- -- return 1; --} -- - static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { -- .detect = toshiba_spinand_detect, - }; - - const struct spinand_manufacturer toshiba_spinand_manufacturer = { - .id = SPINAND_MFR_TOSHIBA, - .name = "Toshiba", -+ .chips = toshiba_spinand_table, -+ .nchips = ARRAY_SIZE(toshiba_spinand_table), - .ops = &toshiba_spinand_manuf_ops, - }; + static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c -@@ -19,6 +19,23 @@ +@@ -18,6 +18,23 @@ #define WINBOND_CFG_BUF_READ BIT(3) @@ -1373,7 +409,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -@@ -35,6 +52,35 @@ static SPINAND_OP_VARIANTS(update_cache_ +@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); @@ -1409,9 +445,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { -@@ -78,8 +124,61 @@ static int w25m02gv_select_target(struct - return spi_mem_exec_op(spinand->slave, &op); - } +@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2 + .rfree = w25n02kv_ooblayout_free, + }; +static int w25n01kv_ecc_get_status(struct spinand_device *spinand, + u8 status) @@ -1465,77 +501,32 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + return -EINVAL; +} + - static const struct spinand_info winbond_spinand_table[] = { -- SPINAND_INFO("W25M02GV", 0xAB, -+ SPINAND_INFO("W25M02GV", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21), - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2), - NAND_ECCREQ(1, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -88,7 +187,17 @@ static const struct spinand_info winbond + static int w25n02kv_ecc_get_status(struct spinand_device *spinand, + u8 status) + { +@@ -163,6 +261,15 @@ static const struct spinand_info winbond + &update_cache_variants), 0, - SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), - SPINAND_SELECT_TARGET(w25m02gv_select_target)), -- SPINAND_INFO("W25N01GV", 0xAA, + SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), + SPINAND_INFO("W25N01KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)), -+ SPINAND_INFO("W25N01GV", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), - NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), - NAND_ECCREQ(1, 512), - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -96,32 +205,30 @@ static const struct spinand_info winbond + SPINAND_INFO("W25N02KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), +@@ -172,6 +279,16 @@ static const struct spinand_info winbond &update_cache_variants), 0, - SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), --}; -- --/** -- * winbond_spinand_detect - initialize device related part in spinand_device -- * struct if it is a Winbond device. -- * @spinand: SPI NAND device structure -- */ --static int winbond_spinand_detect(struct spinand_device *spinand) --{ -- u8 *id = spinand->id.data; -- int ret; -- -- /* -- * Winbond SPI NAND read ID need a dummy byte, -- * so the first byte in raw_id is dummy. -+ SPINAND_INFO("W25N02KV", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ 0, -+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, -+ w25n02kv_n04kv_ecc_get_status)), -+ /* W25N04KV has 2-die(lun), however, it can select die automatically. -+ * Treat it as single die here and double block size. - */ -- if (id[1] != SPINAND_MFR_WINBOND) -- return 0; -- -- ret = spinand_match_and_init(spinand, winbond_spinand_table, -- ARRAY_SIZE(winbond_spinand_table), id[2]); -- if (ret) -- return ret; -- -- return 1; --} + SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), + SPINAND_INFO("W25N04KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, @@ -1543,162 +534,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + 0, + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, + w25n02kv_n04kv_ecc_get_status)), -+}; - - static int winbond_spinand_init(struct spinand_device *spinand) - { -@@ -142,12 +249,13 @@ static int winbond_spinand_init(struct s - } - - static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { -- .detect = winbond_spinand_detect, - .init = winbond_spinand_init, }; - const struct spinand_manufacturer winbond_spinand_manufacturer = { - .id = SPINAND_MFR_WINBOND, - .name = "Winbond", -+ .chips = winbond_spinand_table, -+ .nchips = ARRAY_SIZE(winbond_spinand_table), - .ops = &winbond_spinand_manuf_ops, - }; + static int winbond_spinand_init(struct spinand_device *spinand) --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -39,15 +39,15 @@ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - --#define SPINAND_READID_OP(ndummy, buf, len) \ -+#define SPINAND_READID_OP(naddr, ndummy, buf, len) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ -- SPI_MEM_OP_NO_ADDR, \ -+ SPI_MEM_OP_ADDR(naddr, 0, 1), \ - SPI_MEM_OP_DUMMY(ndummy, 1), \ - SPI_MEM_OP_DATA_IN(len, buf, 1)) - - #define SPINAND_SET_FEATURE_OP(reg, valptr) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ -- SPI_MEM_OP_ADDR(1, reg, 1), \ -+ SPI_MEM_OP_ADDR(1, reg, 1), \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_DATA_OUT(1, valptr, 1)) - -@@ -75,18 +75,36 @@ - SPI_MEM_OP_DUMMY(ndummy, 1), \ - SPI_MEM_OP_DATA_IN(len, buf, 1)) - -+#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len)\ -+ SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ -+ SPI_MEM_OP_ADDR(3, addr, 1), \ -+ SPI_MEM_OP_DUMMY(ndummy, 1), \ -+ SPI_MEM_OP_DATA_IN(len, buf, 1)) -+ - #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ - SPI_MEM_OP_ADDR(2, addr, 1), \ - SPI_MEM_OP_DUMMY(ndummy, 1), \ - SPI_MEM_OP_DATA_IN(len, buf, 2)) - -+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ -+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ -+ SPI_MEM_OP_ADDR(3, addr, 1), \ -+ SPI_MEM_OP_DUMMY(ndummy, 1), \ -+ SPI_MEM_OP_DATA_IN(len, buf, 2)) -+ - #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ - SPI_MEM_OP_ADDR(2, addr, 1), \ - SPI_MEM_OP_DUMMY(ndummy, 1), \ - SPI_MEM_OP_DATA_IN(len, buf, 4)) - -+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ -+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ -+ SPI_MEM_OP_ADDR(3, addr, 1), \ -+ SPI_MEM_OP_DUMMY(ndummy, 1), \ -+ SPI_MEM_OP_DATA_IN(len, buf, 4)) -+ - #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ - SPI_MEM_OP_ADDR(2, addr, 2), \ -@@ -153,37 +171,46 @@ struct spinand_device; - * @data: buffer containing the id bytes. Currently 4 bytes large, but can - * be extended if required - * @len: ID length -- * -- * struct_spinand_id->data contains all bytes returned after a READ_ID command, -- * including dummy bytes if the chip does not emit ID bytes right after the -- * READ_ID command. The responsibility to extract real ID bytes is left to -- * struct_manufacurer_ops->detect(). - */ - struct spinand_id { - u8 data[SPINAND_MAX_ID_LEN]; - int len; - }; - -+enum spinand_readid_method { -+ SPINAND_READID_METHOD_OPCODE, -+ SPINAND_READID_METHOD_OPCODE_ADDR, -+ SPINAND_READID_METHOD_OPCODE_DUMMY, -+}; -+ -+/** -+ * struct spinand_devid - SPI NAND device id structure -+ * @id: device id of current chip -+ * @len: number of bytes in device id -+ * @method: method to read chip id -+ * There are 3 possible variants: -+ * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately -+ * after read_id opcode. -+ * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after -+ * read_id opcode + 1-byte address. -+ * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after -+ * read_id opcode + 1 dummy byte. -+ */ -+struct spinand_devid { -+ const u8 *id; -+ const u8 len; -+ const enum spinand_readid_method method; -+}; -+ - /** - * struct manufacurer_ops - SPI NAND manufacturer specific operations -- * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed -- * the core calls the struct_manufacurer_ops->detect() hook of each -- * registered manufacturer until one of them return 1. Note that -- * the first thing to check in this hook is that the manufacturer ID -- * in struct_spinand_device->id matches the manufacturer whose -- * ->detect() hook has been called. Should return 1 if there's a -- * match, 0 if the manufacturer ID does not match and a negative -- * error code otherwise. When true is returned, the core assumes -- * that properties of the NAND chip (spinand->base.memorg and -- * spinand->base.eccreq) have been filled - * @init: initialize a SPI NAND device - * @cleanup: cleanup a SPI NAND device - * - * Each SPI NAND manufacturer driver should implement this interface so that -- * NAND chips coming from this vendor can be detected and initialized properly. -+ * NAND chips coming from this vendor can be initialized properly. - */ - struct spinand_manufacturer_ops { -- int (*detect)(struct spinand_device *spinand); - int (*init)(struct spinand_device *spinand); - void (*cleanup)(struct spinand_device *spinand); - }; -@@ -192,15 +219,21 @@ struct spinand_manufacturer_ops { - * struct spinand_manufacturer - SPI NAND manufacturer instance - * @id: manufacturer ID - * @name: manufacturer name -+ * @devid_len: number of bytes in device ID -+ * @chips: supported SPI NANDs under current manufacturer -+ * @nchips: number of SPI NANDs available in chips array - * @ops: manufacturer operations - */ - struct spinand_manufacturer { - u8 id; - char *name; -+ const struct spinand_info *chips; -+ const size_t nchips; - const struct spinand_manufacturer_ops *ops; +@@ -245,6 +245,7 @@ struct spinand_manufacturer { }; /* SPI NAND manufacturers */ @@ -1706,39 +547,3 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; -@@ -268,7 +301,7 @@ struct spinand_ecc_info { - */ - struct spinand_info { - const char *model; -- u8 devid; -+ struct spinand_devid devid; - u32 flags; - struct nand_memory_organization memorg; - struct nand_ecc_req eccreq; -@@ -282,6 +315,13 @@ struct spinand_info { - unsigned int target); - }; - -+#define SPINAND_ID(__method, ...) \ -+ { \ -+ .id = (const u8[]){ __VA_ARGS__ }, \ -+ .len = sizeof((u8[]){ __VA_ARGS__ }), \ -+ .method = __method, \ -+ } -+ - #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ - { \ - .read_cache = __read, \ -@@ -440,9 +480,10 @@ static inline void spinand_set_ofnode(st - } - #endif /* __UBOOT__ */ - --int spinand_match_and_init(struct spinand_device *dev, -+int spinand_match_and_init(struct spinand_device *spinand, - const struct spinand_info *table, -- unsigned int table_size, u8 devid); -+ unsigned int table_size, -+ enum spinand_readid_method rdid_method); - - int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); - int spinand_select_target(struct spinand_device *spinand, unsigned int target); diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch index 0c68f429c6..5c90e24ebf 100644 --- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig -@@ -820,6 +820,14 @@ config MMC_MTK +@@ -815,6 +815,14 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. @@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config FSL_SDHC_V2_3 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile -@@ -83,3 +83,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm +@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o @@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +endif --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c -@@ -778,18 +778,24 @@ static int msdc_ops_send_cmd(struct udev +@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev if (cmd_ret && !(cmd_ret == -EIO && (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch index 98c81acdcf..fb8d15ddf9 100644 --- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch +++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/env/Kconfig +++ b/env/Kconfig -@@ -675,6 +675,12 @@ config ENV_UBI_VOLUME_REDUND +@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND help Name of the redundant volume that you want to store the environment in. diff --git a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch index cd1794f0d1..9c83e6cc25 100644 --- a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch +++ b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/ubi/attach.c +++ b/drivers/mtd/ubi/attach.c -@@ -802,6 +802,13 @@ out_unlock: +@@ -803,6 +803,13 @@ out_unlock: return err; } @@ -29,7 +29,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> /** * scan_peb - scan and process UBI headers of a PEB. * @ubi: UBI device description object -@@ -832,9 +839,21 @@ static int scan_peb(struct ubi_device *u +@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u return 0; } @@ -56,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> break; --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h -@@ -745,6 +745,7 @@ struct ubi_attach_info { +@@ -746,6 +746,7 @@ struct ubi_attach_info { int mean_ec; uint64_t ec_sum; int ec_count; diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch index b561a79944..f22449ae76 100644 --- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch +++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch @@ -24,7 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support DECLARE_GLOBAL_DATA_PTR; int board_init(void) -@@ -24,3 +29,36 @@ int board_late_init(void) +@@ -23,3 +28,36 @@ int board_late_init(void) env_relocate(); return 0; } diff --git a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch b/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch deleted file mode 100644 index 645b7801c8..0000000000 --- a/package/boot/uboot-mediatek/patches/101-01-arm-mediatek-retrieve-ram_base-from-dts-node-for-arm.patch +++ /dev/null @@ -1,297 +0,0 @@ -From 63336ec7fd7d480ac58a91f3b20d08bf1b3a13ad Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:15:41 +0800 -Subject: [PATCH 01/29] arm: mediatek: retrieve ram_base from dts node for - armv8 platform - -Now we use fdtdec_setup_mem_size_base() to get DRAM base from fdt ram node -and update gd->ram_base. CFG_SYS_SDRAM_BASE is unused and will be removed. - -Also, since mt7622 always passes fdt to linux kernel, there's no need to -assign value to gd->bd->bi_boot_params. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/mt7981-emmc-rfb.dts | 5 +++++ - arch/arm/dts/mt7981-rfb.dts | 5 +++++ - arch/arm/dts/mt7981-sd-rfb.dts | 5 +++++ - arch/arm/dts/mt7986a-bpi-r3-sd.dts | 5 +++++ - arch/arm/dts/mt7986a-rfb.dts | 5 +++++ - arch/arm/dts/mt7986a-sd-rfb.dts | 5 +++++ - arch/arm/dts/mt7986b-rfb.dts | 5 +++++ - arch/arm/dts/mt7986b-sd-rfb.dts | 5 +++++ - arch/arm/mach-mediatek/mt7622/init.c | 13 +++++++++---- - arch/arm/mach-mediatek/mt7981/init.c | 11 +++++++++-- - arch/arm/mach-mediatek/mt7986/init.c | 11 +++++++++-- - board/mediatek/mt7622/mt7622_rfb.c | 1 - - include/configs/mt7622.h | 10 ---------- - include/configs/mt7981.h | 9 --------- - include/configs/mt7986.h | 9 --------- - 15 files changed, 67 insertions(+), 37 deletions(-) - ---- a/arch/arm/dts/mt7981-emmc-rfb.dts -+++ b/arch/arm/dts/mt7981-emmc-rfb.dts -@@ -18,6 +18,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/dts/mt7981-rfb.dts -+++ b/arch/arm/dts/mt7981-rfb.dts -@@ -17,6 +17,11 @@ - stdout-path = &uart0; - tick-timer = &timer0; - }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; - }; - - &uart0 { ---- a/arch/arm/dts/mt7981-sd-rfb.dts -+++ b/arch/arm/dts/mt7981-sd-rfb.dts -@@ -18,6 +18,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts -+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts -@@ -19,6 +19,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x80000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/dts/mt7986a-rfb.dts -+++ b/arch/arm/dts/mt7986a-rfb.dts -@@ -18,6 +18,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; ---- a/arch/arm/dts/mt7986a-sd-rfb.dts -+++ b/arch/arm/dts/mt7986a-sd-rfb.dts -@@ -19,6 +19,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/dts/mt7986b-rfb.dts -+++ b/arch/arm/dts/mt7986b-rfb.dts -@@ -18,6 +18,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/dts/mt7986b-sd-rfb.dts -+++ b/arch/arm/dts/mt7986b-sd-rfb.dts -@@ -19,6 +19,11 @@ - tick-timer = &timer0; - }; - -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0x40000000 0x10000000>; -+ }; -+ - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; ---- a/arch/arm/mach-mediatek/mt7622/init.c -+++ b/arch/arm/mach-mediatek/mt7622/init.c -@@ -4,11 +4,14 @@ - * Author: Sam Shih <sam.shih@mediatek.com> - */ - --#include <common.h> - #include <fdtdec.h> - #include <init.h> - #include <asm/armv8/mmu.h> --#include <asm/cache.h> -+#include <asm/global_data.h> -+#include <asm/u-boot.h> -+#include <linux/sizes.h> -+ -+DECLARE_GLOBAL_DATA_PTR; - - int print_cpuinfo(void) - { -@@ -20,11 +23,13 @@ int dram_init(void) - { - int ret; - -- ret = fdtdec_setup_memory_banksize(); -+ ret = fdtdec_setup_mem_size_base(); - if (ret) - return ret; -- return fdtdec_setup_mem_size_base(); - -+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); -+ -+ return 0; - } - - void reset_cpu(void) ---- a/arch/arm/mach-mediatek/mt7981/init.c -+++ b/arch/arm/mach-mediatek/mt7981/init.c -@@ -4,18 +4,25 @@ - * Author: Sam Shih <sam.shih@mediatek.com> - */ - --#include <cpu_func.h> -+#include <fdtdec.h> - #include <init.h> - #include <asm/armv8/mmu.h> - #include <asm/system.h> - #include <asm/global_data.h> -+#include <asm/u-boot.h> - #include <linux/sizes.h> - - DECLARE_GLOBAL_DATA_PTR; - - int dram_init(void) - { -- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); -+ int ret; -+ -+ ret = fdtdec_setup_mem_size_base(); -+ if (ret) -+ return ret; -+ -+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G); - - return 0; - } ---- a/arch/arm/mach-mediatek/mt7986/init.c -+++ b/arch/arm/mach-mediatek/mt7986/init.c -@@ -4,18 +4,25 @@ - * Author: Sam Shih <sam.shih@mediatek.com> - */ - --#include <cpu_func.h> -+#include <fdtdec.h> - #include <init.h> - #include <asm/armv8/mmu.h> - #include <asm/system.h> - #include <asm/global_data.h> -+#include <asm/u-boot.h> - #include <linux/sizes.h> - - DECLARE_GLOBAL_DATA_PTR; - - int dram_init(void) - { -- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); -+ int ret; -+ -+ ret = fdtdec_setup_mem_size_base(); -+ if (ret) -+ return ret; -+ -+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_2G); - - return 0; - } ---- a/board/mediatek/mt7622/mt7622_rfb.c -+++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -19,7 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; - - int board_init(void) - { -- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; - return 0; - } - ---- a/include/configs/mt7622.h -+++ b/include/configs/mt7622.h -@@ -9,14 +9,4 @@ - #ifndef __MT7622_H - #define __MT7622_H - --/* Uboot definition */ --#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE -- --/* SPL -> Uboot */ --#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE --/* DRAM */ --#define CFG_SYS_SDRAM_BASE 0x40000000 -- --/* Ethernet */ -- - #endif ---- a/include/configs/mt7981.h -+++ b/include/configs/mt7981.h -@@ -9,13 +9,4 @@ - #ifndef __MT7981_H - #define __MT7981_H - --/* Uboot definition */ --#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE -- --/* SPL -> Uboot */ --#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE -- --/* DRAM */ --#define CFG_SYS_SDRAM_BASE 0x40000000 -- - #endif ---- a/include/configs/mt7986.h -+++ b/include/configs/mt7986.h -@@ -9,13 +9,4 @@ - #ifndef __MT7986_H - #define __MT7986_H - --/* Uboot definition */ --#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE -- --/* SPL -> Uboot */ --#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE -- --/* DRAM */ --#define CFG_SYS_SDRAM_BASE 0x40000000 -- - #endif diff --git a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch b/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch deleted file mode 100644 index b64ee15171..0000000000 --- a/package/boot/uboot-mediatek/patches/101-02-board-mediatek-update-config-headers.patch +++ /dev/null @@ -1,129 +0,0 @@ -From df3a0091b249ea82198ea019d145d05a7cf49c0d Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:15:47 +0800 -Subject: [PATCH 02/29] board: mediatek: update config headers - -Remove unused information from include/configs/mtxxxx.h - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - include/configs/mt7620.h | 3 +-- - include/configs/mt7621.h | 6 ++---- - include/configs/mt7623.h | 8 -------- - include/configs/mt7628.h | 5 ++--- - include/configs/mt7629.h | 13 +------------ - 5 files changed, 6 insertions(+), 29 deletions(-) - ---- a/include/configs/mt7620.h -+++ b/include/configs/mt7620.h -@@ -10,10 +10,9 @@ - - #define CFG_SYS_SDRAM_BASE 0x80000000 - --#define CFG_SYS_INIT_SP_OFFSET 0x400000 -+#define CFG_SYS_INIT_SP_OFFSET 0x400000 - - /* SPL */ -- - #define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE - - /* Dummy value */ ---- a/include/configs/mt7621.h -+++ b/include/configs/mt7621.h -@@ -12,13 +12,11 @@ - - #define CFG_MAX_MEM_MAPPED 0x1c000000 - --#define CFG_SYS_INIT_SP_OFFSET 0x800000 -+#define CFG_SYS_INIT_SP_OFFSET 0x800000 - - /* MMC */ - #define MMC_SUPPORTS_TUNING - --/* NAND */ -- - /* Serial SPL */ - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) - #define CFG_SYS_NS16550_CLK 50000000 -@@ -26,7 +24,7 @@ - #endif - - /* Serial common */ --#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ -+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 460800, 921600 } - - /* Dummy value */ ---- a/include/configs/mt7623.h -+++ b/include/configs/mt7623.h -@@ -11,12 +11,6 @@ - - #include <linux/sizes.h> - --/* Miscellaneous configurable options */ -- --/* Environment */ -- --/* Preloader -> Uboot */ -- - /* MMC */ - #define MMC_SUPPORTS_TUNING - -@@ -32,8 +26,6 @@ - "fdt_addr_r=" FDT_HIGH "\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" - --/* Ethernet */ -- - #ifdef CONFIG_DISTRO_DEFAULTS - - #define BOOT_TARGET_DEVICES(func) \ ---- a/include/configs/mt7628.h -+++ b/include/configs/mt7628.h -@@ -10,7 +10,7 @@ - - #define CFG_SYS_SDRAM_BASE 0x80000000 - --#define CFG_SYS_INIT_SP_OFFSET 0x80000 -+#define CFG_SYS_INIT_SP_OFFSET 0x80000 - - /* Serial SPL */ - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -@@ -19,11 +19,10 @@ - #endif - - /* Serial common */ --#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ -+#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 460800, 921600 } - - /* SPL */ -- - #define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE - - /* Dummy value */ ---- a/include/configs/mt7629.h -+++ b/include/configs/mt7629.h -@@ -9,21 +9,10 @@ - #ifndef __MT7629_H - #define __MT7629_H - --#include <linux/sizes.h> -- --/* Miscellaneous configurable options */ -- --/* Environment */ -- -+/* SPL */ - #define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO) - --/* SPL -> Uboot */ -- --/* UBoot -> Kernel */ -- - /* DRAM */ - #define CFG_SYS_SDRAM_BASE 0x40000000 - --/* Ethernet */ -- - #endif diff --git a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch b/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch deleted file mode 100644 index 323bb24933..0000000000 --- a/package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:15:54 +0800 -Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once - -We don't really need to switch clk rate during operating SPIM controller. -Get clk rate only once at driver probing. - -Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> -Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> ---- - drivers/spi/mtk_spim.c | 21 +++++++++++++-------- - 1 file changed, 13 insertions(+), 8 deletions(-) - ---- a/drivers/spi/mtk_spim.c -+++ b/drivers/spi/mtk_spim.c -@@ -137,6 +137,8 @@ struct mtk_spim_capability { - * @state: Controller state - * @sel_clk: Pad clock - * @spi_clk: Core clock -+ * @pll_clk_rate: Controller's PLL source clock rate, which is different -+ * from SPI bus clock rate - * @xfer_len: Current length of data for transfer - * @hw_cap: Controller capabilities - * @tick_dly: Used to postpone SPI sampling time -@@ -149,6 +151,7 @@ struct mtk_spim_priv { - void __iomem *base; - u32 state; - struct clk sel_clk, spi_clk; -+ u32 pll_clk_rate; - u32 xfer_len; - struct mtk_spim_capability hw_cap; - u32 tick_dly; -@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s - static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv, - u32 speed_hz) - { -- u32 spi_clk_hz, div, sck_time, cs_time, reg_val; -+ u32 div, sck_time, cs_time, reg_val; - -- spi_clk_hz = clk_get_rate(&priv->spi_clk); -- if (speed_hz <= spi_clk_hz / 4) -- div = DIV_ROUND_UP(spi_clk_hz, speed_hz); -+ if (speed_hz <= priv->pll_clk_rate / 4) -+ div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz); - else - div = 4; - -@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct - { - struct udevice *bus = dev_get_parent(slave->dev); - struct mtk_spim_priv *priv = dev_get_priv(bus); -- u32 sck_l, sck_h, spi_bus_clk, clk_count, reg; -+ u32 sck_l, sck_h, clk_count, reg; - ulong us = 1; - int ret = 0; - -@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct - else - clk_count = op->data.nbytes; - -- spi_bus_clk = clk_get_rate(&priv->spi_clk); - sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET; - sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK; -- do_div(spi_bus_clk, sck_l + sck_h + 2); -+ do_div(priv->pll_clk_rate, sck_l + sck_h + 2); - -- us = CLK_TO_US(spi_bus_clk, clk_count * 8); -+ us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8); - us += 1000 * 1000; /* 1s tolerance */ - - if (us > UINT_MAX) -@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice - clk_enable(&priv->sel_clk); - clk_enable(&priv->spi_clk); - -+ priv->pll_clk_rate = clk_get_rate(&priv->spi_clk); -+ if (priv->pll_clk_rate == 0) -+ return -EINVAL; -+ - return 0; - } - diff --git a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch b/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch deleted file mode 100644 index e8577f63bf..0000000000 --- a/package/boot/uboot-mediatek/patches/101-04-spi-mtk_spim-clear-IRQ-enable-bits.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a7b630f02bb12f71f23866aee6f9a1a07497d475 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:02 +0800 -Subject: [PATCH 04/29] spi: mtk_spim: clear IRQ enable bits - -In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS. - -However these IRQ enable bits may be set in previous boot stage (BootROM). - -If we leave these bits not cleared, although u-boot has disabled IRQ and -nothing will happen, the linux kernel may encounter panic during -initializing the spim driver due to IRQ event happens before IRQ handler -is properly setup. - -This patch clear IRQ bits to prevent this from happening. - -Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> -Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> ---- - drivers/spi/mtk_spim.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/spi/mtk_spim.c -+++ b/drivers/spi/mtk_spim.c -@@ -242,6 +242,9 @@ static int mtk_spim_hw_init(struct spi_s - reg_val &= ~SPI_CMD_SAMPLE_SEL; - } - -+ /* Disable interrupt enable for pause mode & normal mode */ -+ reg_val &= ~(SPI_CMD_PAUSE_IE | SPI_CMD_FINISH_IE); -+ - /* disable dma mode */ - reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); - diff --git a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch b/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch deleted file mode 100644 index 6f805765c1..0000000000 --- a/package/boot/uboot-mediatek/patches/101-05-serial-mtk-initial-priv-data-before-using.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 73060da8b54e74c51ef6c1fd31c4fac6ad6b8d0e Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:07 +0800 -Subject: [PATCH 05/29] serial: mtk: initial priv data before using - -This patch ensures driver private data being fully initialized in -_debug_uart_init which is not covered by .priv_auto ops. - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> -Reviewed-by: Stefan Roese <sr@denx.de> ---- - drivers/serial/serial_mtk.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/serial/serial_mtk.c -+++ b/drivers/serial/serial_mtk.c -@@ -439,6 +439,7 @@ static inline void _debug_uart_init(void - { - struct mtk_serial_priv priv; - -+ memset(&priv, 0, sizeof(struct mtk_serial_priv)); - priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); - priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; - diff --git a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch b/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch deleted file mode 100644 index b319f5e27e..0000000000 --- a/package/boot/uboot-mediatek/patches/101-06-reset-mediatek-check-malloc-return-valaue-before-use.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 06e6d224f7d564a34407eba21b51797da7f22628 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:11 +0800 -Subject: [PATCH 06/29] reset: mediatek: check malloc return valaue before use - -This patch add missing return value check for allocating the driver's -private data. -ENOMEM will be returned if malloc() fails. - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/reset/reset-mediatek.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/reset/reset-mediatek.c -+++ b/drivers/reset/reset-mediatek.c -@@ -79,6 +79,9 @@ int mediatek_reset_bind(struct udevice * - return ret; - - priv = malloc(sizeof(struct mediatek_reset_priv)); -+ if (!priv) -+ return -ENOMEM; -+ - priv->regofs = regofs; - priv->nr_resets = num_regs * 32; - dev_set_priv(rst_dev, priv); diff --git a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch b/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch deleted file mode 100644 index dd00104c39..0000000000 --- a/package/boot/uboot-mediatek/patches/101-07-i2c-mediatek-fix-I2C-usability-for-MT7981.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 77898faf6ce56eb08109cdb853f074bad5acee55 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:15 +0800 -Subject: [PATCH 07/29] i2c: mediatek: fix I2C usability for MT7981 - -MT7981 actually uses MediaTek I2C controller v3 instead of v1. -This patch adds support for I2C controller v3 fix fixes the I2C usability -for MT7981. - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/i2c/mtk_i2c.c | 45 +++++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 43 insertions(+), 2 deletions(-) - ---- a/drivers/i2c/mtk_i2c.c -+++ b/drivers/i2c/mtk_i2c.c -@@ -183,9 +183,36 @@ static const uint mt_i2c_regs_v2[] = { - [REG_DCM_EN] = 0xf88, - }; - -+static const uint mt_i2c_regs_v3[] = { -+ [REG_PORT] = 0x0, -+ [REG_INTR_MASK] = 0x8, -+ [REG_INTR_STAT] = 0xc, -+ [REG_CONTROL] = 0x10, -+ [REG_TRANSFER_LEN] = 0x14, -+ [REG_TRANSAC_LEN] = 0x18, -+ [REG_DELAY_LEN] = 0x1c, -+ [REG_TIMING] = 0x20, -+ [REG_START] = 0x24, -+ [REG_EXT_CONF] = 0x28, -+ [REG_LTIMING] = 0x2c, -+ [REG_HS] = 0x30, -+ [REG_IO_CONFIG] = 0x34, -+ [REG_FIFO_ADDR_CLR] = 0x38, -+ [REG_TRANSFER_LEN_AUX] = 0x44, -+ [REG_CLOCK_DIV] = 0x48, -+ [REG_SOFTRESET] = 0x50, -+ [REG_SLAVE_ADDR] = 0x94, -+ [REG_DEBUGSTAT] = 0xe4, -+ [REG_DEBUGCTRL] = 0xe8, -+ [REG_FIFO_STAT] = 0xf4, -+ [REG_FIFO_THRESH] = 0xf8, -+ [REG_DCM_EN] = 0xf88, -+}; -+ - struct mtk_i2c_soc_data { - const uint *regs; - uint dma_sync: 1; -+ uint ltiming_adjust: 1; - }; - - struct mtk_i2c_priv { -@@ -401,6 +428,10 @@ static int mtk_i2c_set_speed(struct udev - (sample_cnt << HS_SAMPLE_OFFSET) | - (step_cnt << HS_STEP_OFFSET); - i2c_writel(priv, REG_HS, high_speed_reg); -+ if (priv->soc_data->ltiming_adjust) { -+ timing_reg = (sample_cnt << 12) | (step_cnt << 9); -+ i2c_writel(priv, REG_LTIMING, timing_reg); -+ } - } else { - ret = mtk_i2c_calculate_speed(clk_src, priv->speed, - &step_cnt, &sample_cnt); -@@ -412,7 +443,12 @@ static int mtk_i2c_set_speed(struct udev - high_speed_reg = I2C_TIME_CLR_VALUE; - i2c_writel(priv, REG_TIMING, timing_reg); - i2c_writel(priv, REG_HS, high_speed_reg); -+ if (priv->soc_data->ltiming_adjust) { -+ timing_reg = (sample_cnt << 6) | step_cnt; -+ i2c_writel(priv, REG_LTIMING, timing_reg); -+ } - } -+ - exit: - if (mtk_i2c_clk_disable(priv)) - return log_msg_ret("set_speed disable clk", -1); -@@ -725,7 +761,6 @@ static int mtk_i2c_probe(struct udevice - return log_msg_ret("probe enable clk", -1); - - mtk_i2c_init_hw(priv); -- - if (mtk_i2c_clk_disable(priv)) - return log_msg_ret("probe disable clk", -1); - -@@ -750,31 +785,37 @@ static int mtk_i2c_deblock(struct udevic - static const struct mtk_i2c_soc_data mt76xx_soc_data = { - .regs = mt_i2c_regs_v1, - .dma_sync = 0, -+ .ltiming_adjust = 0, - }; - - static const struct mtk_i2c_soc_data mt7981_soc_data = { -- .regs = mt_i2c_regs_v1, -+ .regs = mt_i2c_regs_v3, - .dma_sync = 1, -+ .ltiming_adjust = 1, - }; - - static const struct mtk_i2c_soc_data mt7986_soc_data = { - .regs = mt_i2c_regs_v1, - .dma_sync = 1, -+ .ltiming_adjust = 0, - }; - - static const struct mtk_i2c_soc_data mt8183_soc_data = { - .regs = mt_i2c_regs_v2, - .dma_sync = 1, -+ .ltiming_adjust = 0, - }; - - static const struct mtk_i2c_soc_data mt8518_soc_data = { - .regs = mt_i2c_regs_v1, - .dma_sync = 0, -+ .ltiming_adjust = 0, - }; - - static const struct mtk_i2c_soc_data mt8512_soc_data = { - .regs = mt_i2c_regs_v1, - .dma_sync = 1, -+ .ltiming_adjust = 0, - }; - - static const struct dm_i2c_ops mtk_i2c_ops = { diff --git a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch b/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch deleted file mode 100644 index 77c4023493..0000000000 --- a/package/boot/uboot-mediatek/patches/101-08-arm-dts-enable-i2c-support-for-MediaTek-MT7981.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e9467f40d4327cfcb80944a0f12ae195b0d7cd40 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:19 +0800 -Subject: [PATCH 08/29] arm: dts: enable i2c support for MediaTek MT7981 - -This patch enables i2c support for MediaTek MT7981 - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/mt7981.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm/dts/mt7981.dtsi -+++ b/arch/arm/dts/mt7981.dtsi -@@ -181,6 +181,20 @@ - status = "disabled"; - }; - -+ i2c0: i2c@11007000 { -+ compatible = "mediatek,mt7981-i2c"; -+ reg = <0x11007000 0x1000>, -+ <0x10217080 0x80>; -+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; -+ clock-div = <1>; -+ clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, -+ <&infracfg_ao CK_INFRA_AP_DMA_CK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,hsuart"; - reg = <0x11002000 0x400>; diff --git a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch deleted file mode 100644 index 6ef62811cb..0000000000 --- a/package/boot/uboot-mediatek/patches/101-09-pwm-mtk-add-support-for-MediaTek-MT7988-SoC.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 646dab4a8e853b2d0789fa2ff64e7c48f5396cfa Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:24 +0800 -Subject: [PATCH 09/29] pwm: mtk: add support for MediaTek MT7988 SoC - -This patch adds PWM support for MediaTek MT7988 SoC. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pwm/pwm-mtk.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/pwm/pwm-mtk.c -+++ b/drivers/pwm/pwm-mtk.c -@@ -205,12 +205,19 @@ static const struct mtk_pwm_soc mt7986_d - .reg_ver = PWM_REG_V1, - }; - -+static const struct mtk_pwm_soc mt7988_data = { -+ .num_pwms = 8, -+ .pwm45_fixup = false, -+ .reg_ver = PWM_REG_V2, -+}; -+ - static const struct udevice_id mtk_pwm_ids[] = { - { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, - { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, - { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, - { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data }, - { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, -+ { .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data }, - { } - }; - diff --git a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch deleted file mode 100644 index 12eda828fa..0000000000 --- a/package/boot/uboot-mediatek/patches/101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ /dev/null @@ -1,1505 +0,0 @@ -From 94306126baa215c39e9fd5328550586dedf00230 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:28 +0800 -Subject: [PATCH 10/29] clk: mediatek: add clock driver support for MediaTek - MT7988 SoC - -This patch adds clock driver support for MediaTek MT7988 SoC - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/clk/mediatek/Makefile | 1 + - drivers/clk/mediatek/clk-mt7988.c | 1123 ++++++++++++++++++++++++ - include/dt-bindings/clock/mt7988-clk.h | 349 ++++++++ - 3 files changed, 1473 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7988.c - create mode 100644 include/dt-bindings/clock/mt7988-clk.h - ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt762 - obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o - obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o - obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o -+obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o - obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o - obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o - obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988.c -@@ -0,0 +1,1123 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek clock driver for MT7988 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#include <dm.h> -+#include <log.h> -+#include <asm/arch-mediatek/reset.h> -+#include <asm/io.h> -+#include <dt-bindings/clock/mt7988-clk.h> -+#include <linux/bitops.h> -+ -+#include "clk-mtk.h" -+ -+#define MT7988_CLK_PDN 0x250 -+#define MT7988_CLK_PDN_EN_WRITE BIT(31) -+ -+#define MT7988_ETHDMA_RST_CTRL_OFS 0x34 -+#define MT7988_ETHWARP_RST_CTRL_OFS 0x8 -+ -+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) -+ -+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) -+ -+#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) -+ -+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ -+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) -+ -+/* FIXED PLLS */ -+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { -+ FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), -+ FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), -+ FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), -+ FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), -+ FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), -+ FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), -+ FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), -+ FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), -+ FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000), -+ FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), -+ FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), -+ FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), -+}; -+ -+/* TOPCKGEN FIXED DIV */ -+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { -+ XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), -+ PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), -+ PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), -+ PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), -+ PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), -+ PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), -+ PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), -+ PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), -+ PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), -+ PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), -+ PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), -+ PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64), -+ PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1, -+ 128), -+ PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, -+ 1), -+ PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), -+ PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), -+ PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), -+ PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32), -+ PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), -+ PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8), -+ PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", -+ CK_APMIXED_WEDMCUPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", -+ CK_APMIXED_NETSYSPLL, 1, 1), -+ PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), -+ TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, -+ 1250), -+ TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, -+ 1220), -+ TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1, -+ 1), -+ XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", -+ CK_TOP_NETSYS_MCU_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", -+ CK_TOP_USB_FRMCNT_P1_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), -+ TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL, -+ 1, 1), -+ TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1), -+ TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1), -+}; -+ -+/* TOPCKGEN MUX PARENTS */ -+static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, -+ CK_TOP_CB_MM_D2 }; -+ -+static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET1_D5, -+ CK_TOP_NET1_D5_D2 }; -+ -+static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_800M, -+ CK_TOP_CB_MM_720M }; -+ -+static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4, -+ CK_TOP_CB_NET1_D5 }; -+ -+static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; -+ -+static const int netsys_mcu_parents[] = { -+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M, -+ CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M -+}; -+ -+static const int eip197_parents[] = { -+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M, -+ CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5 -+}; -+ -+static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D8_D2 }; -+ -+static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, -+ CK_TOP_M_D8_D2 }; -+ -+static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2, -+ CK_TOP_CB_MM_D4 }; -+ -+static const int emmc_400m_parents[] = { -+ CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2, -+ CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2 -+}; -+ -+static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, -+ CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, -+ CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; -+ -+static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, -+ CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, -+ CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, -+ CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; -+ -+static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, -+ CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, -+ CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; -+ -+static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, -+ CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, -+ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; -+ -+static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, -+ CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; -+ -+static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D5_D2 }; -+ -+static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8, -+ CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; -+ -+static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_MM_D3_D5 }; -+ -+static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; -+ -+static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 }; -+ -+static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, -+ CK_TOP_M_D8_D2 }; -+ -+static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; -+ -+static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET1_D8_D4 }; -+ -+static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M }; -+ -+static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; -+ -+static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_NET2_D4_D4 }; -+ -+static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_D4 }; -+ -+static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8, -+ CK_TOP_NET1_D8_D16 }; -+ -+static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, -+ CK_TOP_CB_NET2_D2 }; -+ -+static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_800M }; -+ -+static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, -+ CK_TOP_CB_WEDMCU_208M }; -+ -+static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_D8 }; -+ -+static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET1_D4 }; -+ -+static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M, -+ CK_TOP_CB_NET1_D8 }; -+ -+static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M, -+ CK_TOP_CB_NET2_D2 }; -+ -+static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; -+ -+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ -+ _shift, _width, _gate, _upd_ofs, _upd) \ -+ { \ -+ .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ -+ .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ -+ .upd_shift = _upd, .mux_shift = _shift, \ -+ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ -+ .gate_shift = _gate, .parent = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD, \ -+ } -+ -+/* TOPCKGEN MUX_GATE */ -+static const struct mtk_composite topckgen_mtk_muxes[] = { -+ TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, -+ 0, 2, 7, 0x1c0, 0), -+ TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, -+ 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1), -+ TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, -+ 0x4, 0x8, 16, 2, 23, 0x1c0, 2), -+ TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, -+ 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3), -+ TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, -+ 0x14, 0x18, 0, 1, 7, 0x1c0, 4), -+ TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, -+ 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), -+ TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", -+ netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6), -+ TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, -+ 0x18, 24, 3, 31, 0x1c0, 7), -+ TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, -+ 0x24, 0x28, 0, 1, 7, 0x1c0, 8), -+ TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, -+ 2, 15, 0x1c0, 9), -+ TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, -+ 0x24, 0x28, 16, 2, 23, 0x1c0, 10), -+ TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, -+ 0x24, 0x28, 24, 3, 31, 0x1c0, 11), -+ TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, -+ 7, 0x1c0, 12), -+ TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, -+ 0x38, 8, 3, 15, 0x1c0, 13), -+ TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, -+ 16, 3, 23, 0x1c0, 14), -+ TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, -+ 0x38, 24, 3, 31, 0x1c0, 15), -+ TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, -+ 7, 0x1c0, 16), -+ TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, -+ 15, 0x1c0, 17), -+ TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", -+ pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, -+ 18), -+ TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, -+ 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), -+ TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", -+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20), -+ TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", -+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21), -+ TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", -+ pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22), -+ TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, -+ 0x58, 24, 1, 31, 0x1c0, 23), -+ TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, -+ 0x64, 0x68, 0, 1, 7, 0x1c0, 24), -+ TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, -+ 0x64, 0x68, 8, 1, 15, 0x1c0, 25), -+ TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, -+ 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), -+ TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, -+ 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27), -+ TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", -+ usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28), -+ TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, -+ 15, 0x1c0, 29), -+ TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, -+ 16, 1, 23, 0x1c0, 30), -+ TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, -+ 24, 2, 31, 0x1c4, 0), -+ TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, -+ 0x88, 0, 1, 7, 0x1c4, 1), -+ TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, -+ 0x88, 8, 1, 15, 0x1c4, 2), -+ TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, -+ 0x88, 16, 1, 23, 0x1c4, 3), -+ TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", -+ usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4), -+ TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", -+ usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5), -+ TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, -+ 8, 1, 15, 0x1c4, 6), -+ TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, -+ 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7), -+ TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, -+ 24, 1, 31, 0x1c4, 8), -+ TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, -+ 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9), -+ TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, -+ 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10), -+ TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, -+ 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11), -+ TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, -+ 0xa8, 24, 1, 31, 0x1c4, 12), -+ TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, -+ 0xb8, 0, 1, 7, 0x1c4, 13), -+ TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", -+ eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14), -+ TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", -+ eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15), -+ TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, -+ 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16), -+ TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, -+ 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17), -+ TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, -+ 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18), -+ TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, -+ 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19), -+ TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, -+ 24, 1, 31, 0x1c4, 20), -+ TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, -+ 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21), -+ TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, -+ 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22), -+ TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, -+ 0xd8, 16, 1, 23, 0x1c4, 23), -+ TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, -+ 0xd8, 24, 1, 31, 0x1c4, 24), -+ TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, -+ 0xe8, 0, 1, 7, 0x1c4, 25), -+ TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, -+ 0xe8, 8, 1, 15, 0x1c4, 26), -+ TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", -+ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27), -+ TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", -+ da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28), -+ TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", -+ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29), -+ TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", -+ da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30), -+ TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, -+ 1, 23, 0x1c8, 0), -+ TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents, -+ 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1), -+ TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, -+ 0x108, 0, 1, 7, 0x1c8, 2), -+ TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, -+ 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3), -+ TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", -+ mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23, -+ 0x1c8, 4), -+ TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", -+ pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8, -+ 5), -+ TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, -+ 0x118, 0, 2, 7, 0x1c8, 6), -+ TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", -+ netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8, -+ 7), -+ TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", -+ pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8, -+ 8), -+ TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, -+ 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9), -+ TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, -+ 0x124, 0x128, 0, 1, 7, 0x1c8, 10), -+ TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel", -+ netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), -+}; -+ -+/* INFRA FIXED DIV */ -+static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = { -+ TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", -+ CK_TOP_PEXTP_TL_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1", -+ CK_TOP_PEXTP_TL_P1_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2", -+ CK_TOP_PEXTP_TL_P2_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3", -+ CK_TOP_PEXTP_TL_P3_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), -+ INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK, -+ 1, 1), -+ INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1), -+ TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1), -+ TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1), -+ TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1), -+ TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1), -+ INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC, -+ 1, 1), -+ TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1), -+ TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", -+ CK_TOP_EMMC_250M, 1, 1), -+ TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", -+ CK_TOP_USB_FRMCNT, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1", -+ CK_TOP_USB_FRMCNT_P1, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", -+ CK_TOP_USB_XHCI_P1, 1, 1), -+ XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1), -+ XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1, -+ 1), -+ XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1), -+ XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1, -+ 1), -+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0", -+ CLK_XTAL, 1, 1), -+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1", -+ CLK_XTAL, 1, 1), -+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2", -+ CLK_XTAL, 1, 1), -+ XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3", -+ CLK_XTAL, 1, 1), -+ TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1), -+ TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1), -+ TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1), -+ TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1, -+ 1), -+ TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1), -+ TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", -+ CK_TOP_USB_SYS_P1, 1, 1), -+}; -+ -+/* INFRASYS MUX PARENTS */ -+static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M, -+ CK_INFRA_UART_O0 }; -+ -+static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M, -+ CK_INFRA_UART_O1 }; -+ -+static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M, -+ CK_INFRA_UART_O2 }; -+ -+static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O }; -+ -+static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O }; -+ -+static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K, -+ CK_INFRA_CK_F26M, CK_INFRA_66M_MCK, -+ CK_INFRA_PWM_O }; -+ -+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { -+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, -+ CK_INFRA_PCIE_OCC_P0 -+}; -+ -+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { -+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, -+ CK_INFRA_PCIE_OCC_P1 -+}; -+ -+static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { -+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, -+ CK_INFRA_PCIE_OCC_P2 -+}; -+ -+static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { -+ CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, -+ CK_INFRA_PCIE_OCC_P3 -+}; -+ -+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ -+ { \ -+ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ -+ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ -+ .mux_mask = BIT(_width) - 1, .parent = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA MUX */ -+static const struct mtk_composite infracfg_mtk_mux[] = { -+ INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", -+ infra_mux_uart0_parents, 0x10, 0, 1), -+ INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", -+ infra_mux_uart1_parents, 0x10, 1, 1), -+ INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", -+ infra_mux_uart2_parents, 0x10, 2, 1), -+ INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", -+ infra_mux_spi0_parents, 0x10, 4, 1), -+ INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", -+ infra_mux_spi1_parents, 0x10, 5, 1), -+ INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", -+ infra_mux_spi0_parents, 0x10, 6, 1), -+ INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, -+ 0x10, 14, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", -+ infra_pwm_bck_parents, 0x10, 16, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", -+ infra_pwm_bck_parents, 0x10, 18, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", -+ infra_pwm_bck_parents, 0x10, 20, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", -+ infra_pwm_bck_parents, 0x10, 22, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", -+ infra_pwm_bck_parents, 0x10, 24, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", -+ infra_pwm_bck_parents, 0x10, 26, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", -+ infra_pwm_bck_parents, 0x10, 28, 2), -+ INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", -+ infra_pwm_bck_parents, 0x10, 30, 2), -+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, -+ "infra_pcie_gfmux_tl_o_p0_sel", -+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2), -+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, -+ "infra_pcie_gfmux_tl_o_p1_sel", -+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2), -+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, -+ "infra_pcie_gfmux_tl_o_p2_sel", -+ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2), -+ INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, -+ "infra_pcie_gfmux_tl_o_p3_sel", -+ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2), -+}; -+ -+static const struct mtk_gate_regs infra_0_cg_regs = { -+ .set_ofs = 0x10, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x18, -+}; -+ -+static const struct mtk_gate_regs infra_1_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra_2_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra_3_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+#define GATE_INFRA3(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ -+ } -+ -+/* INFRA GATE */ -+static const struct mtk_gate infracfg_mtk_gates[] = { -+ GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", -+ CK_INFRA_66M_MCK, 0), -+ GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", -+ CK_INFRA_66M_MCK, 1), -+ GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", -+ CK_INFRA_PWM_SEL, 2), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", -+ CK_INFRA_PWM_CK1_SEL, 3), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", -+ CK_INFRA_PWM_CK2_SEL, 4), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", -+ CK_INFRA_PWM_CK3_SEL, 5), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", -+ CK_INFRA_PWM_CK4_SEL, 6), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", -+ CK_INFRA_PWM_CK5_SEL, 7), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", -+ CK_INFRA_PWM_CK6_SEL, 8), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", -+ CK_INFRA_PWM_CK7_SEL, 9), -+ GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", -+ CK_INFRA_PWM_CK8_SEL, 10), -+ GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", -+ CK_INFRA_133M_MCK, 12), -+ GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", -+ CK_INFRA_66M_PHCK, 13), -+ GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14), -+ GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15), -+ GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O, -+ 16), -+ GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O, -+ 18), -+ GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M, -+ 19), -+ GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", -+ CK_INFRA_133M_MCK, 20), -+ GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", -+ CK_INFRA_66M_MCK, 21), -+ GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", -+ CK_INFRA_66M_MCK, 29), -+ GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", -+ CK_INFRA_CK_F26M, 30), -+ GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O, -+ 31), -+ GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", -+ CK_INFRA_CK_F26M, 0), -+ GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1), -+ GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", -+ CK_INFRA_66M_MCK, 3), -+ GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", -+ CK_INFRA_66M_MCK, 4), -+ GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", -+ CK_INFRA_66M_MCK, 5), -+ GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", -+ CK_INFRA_MUX_UART0_SEL, 3), -+ GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", -+ CK_INFRA_MUX_UART1_SEL, 4), -+ GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", -+ CK_INFRA_MUX_UART2_SEL, 5), -+ GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9), -+ GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10), -+ GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", -+ CK_INFRA_66M_MCK, 11), -+ GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0", -+ CK_INFRA_MUX_SPI0_SEL, 12), -+ GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1", -+ CK_INFRA_MUX_SPI1_SEL, 13), -+ GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", -+ CK_INFRA_MUX_SPI2_SEL, 14), -+ GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", -+ CK_INFRA_66M_MCK, 15), -+ GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", -+ CK_INFRA_66M_MCK, 16), -+ GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", -+ CK_INFRA_66M_MCK, 17), -+ GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", -+ CK_INFRA_66M_MCK, 18), -+ GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19), -+ GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", -+ CK_INFRA_F26M_O1, 20), -+ GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK, -+ 21), -+ GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O, -+ 22), -+ GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", -+ CK_INFRA_FMSDC2_HCK_OCC, 23), -+ GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", -+ CK_INFRA_PERI_133M, 24), -+ GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", -+ CK_INFRA_66M_PHCK, 25), -+ GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", -+ CK_INFRA_133M_MCK, 26), -+ GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O, -+ 27), -+ GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", -+ CK_INFRA_133M_MCK, 29), -+ GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", -+ CK_INFRA_66M_PHCK, 31), -+ GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", -+ CK_INFRA_133M_PHCK, 0), -+ GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", -+ CK_INFRA_133M_PHCK, 1), -+ GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", -+ CK_INFRA_66M_PHCK, 2), -+ GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", -+ CK_INFRA_66M_PHCK, 3), -+ GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4), -+ GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", -+ CK_INFRA_USB_SYS_O_P1, 5), -+ GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6), -+ GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1, -+ 7), -+ GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", -+ CK_INFRA_USB_FRMCNT_O, 8), -+ GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", -+ CK_INFRA_USB_FRMCNT_O_P1, 9), -+ GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O, -+ 10), -+ GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", -+ CK_INFRA_USB_PIPE_O_P1, 11), -+ GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O, -+ 12), -+ GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", -+ CK_INFRA_USB_UTMI_O_P1, 13), -+ GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O, -+ 14), -+ GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", -+ CK_INFRA_USB_XHCI_O_P1, 15), -+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", -+ CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), -+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", -+ CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), -+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", -+ CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), -+ GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", -+ CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), -+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", -+ CK_INFRA_PCIE_PIPE_OCC_P0, 24), -+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", -+ CK_INFRA_PCIE_PIPE_OCC_P1, 25), -+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", -+ CK_INFRA_PCIE_PIPE_OCC_P2, 26), -+ GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", -+ CK_INFRA_PCIE_PIPE_OCC_P3, 27), -+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", -+ CK_INFRA_133M_PHCK, 28), -+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", -+ CK_INFRA_133M_PHCK, 29), -+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", -+ CK_INFRA_133M_PHCK, 30), -+ GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", -+ CK_INFRA_133M_PHCK, 31), -+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0, -+ "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7), -+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1, -+ "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8), -+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2, -+ "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9), -+ GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3, -+ "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10), -+}; -+ -+static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { -+ .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), -+ .fclks = apmixedsys_mtk_plls, -+ .xtal_rate = 40 * MHZ, -+}; -+ -+static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { -+ .fdivs_offs = CK_TOP_CB_CKSQ_40M, -+ .muxes_offs = CK_TOP_NETSYS_SEL, -+ .fdivs = topckgen_mtk_fixed_factors, -+ .muxes = topckgen_mtk_muxes, -+ .flags = CLK_BYPASS_XTAL, -+ .xtal_rate = 40 * MHZ, -+}; -+ -+static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { -+ .fdivs_offs = CK_INFRA_CK_F26M, -+ .muxes_offs = CK_INFRA_MUX_UART0_SEL, -+ .fdivs = infracfg_mtk_fixed_factor, -+ .muxes = infracfg_mtk_mux, -+ .flags = CLK_BYPASS_XTAL, -+ .xtal_rate = 40 * MHZ, -+}; -+ -+static const struct udevice_id mt7988_fixed_pll_compat[] = { -+ { .compatible = "mediatek,mt7988-fixed-plls" }, -+ {} -+}; -+ -+static const struct udevice_id mt7988_topckgen_compat[] = { -+ { .compatible = "mediatek,mt7988-topckgen" }, -+ {} -+}; -+ -+static int mt7988_fixed_pll_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree); -+} -+ -+static int mt7988_topckgen_probe(struct udevice *dev) -+{ -+ struct mtk_clk_priv *priv = dev_get_priv(dev); -+ -+ priv->base = dev_read_addr_ptr(dev); -+ if (!priv->base) -+ return -ENOENT; -+ -+ writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN); -+ return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree); -+} -+ -+U_BOOT_DRIVER(mtk_clk_apmixedsys) = { -+ .name = "mt7988-clock-fixed-pll", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_fixed_pll_compat, -+ .probe = mt7988_fixed_pll_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_topckgen) = { -+ .name = "mt7988-clock-topckgen", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_topckgen_compat, -+ .probe = mt7988_topckgen_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_topckgen_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+static const struct udevice_id mt7988_infracfg_compat[] = { -+ { .compatible = "mediatek,mt7988-infracfg" }, -+ {} -+}; -+ -+static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = { -+ { .compatible = "mediatek,mt7988-infracfg_ao_cgs" }, -+ {} -+}; -+ -+static int mt7988_infracfg_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree); -+} -+ -+static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree, -+ infracfg_mtk_gates); -+} -+ -+U_BOOT_DRIVER(mtk_clk_infracfg) = { -+ .name = "mt7988-clock-infracfg", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_infracfg_compat, -+ .probe = mt7988_infracfg_probe, -+ .priv_auto = sizeof(struct mtk_clk_priv), -+ .ops = &mtk_clk_infrasys_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = { -+ .name = "mt7988-clock-infracfg_ao_cgs", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_infracfg_ao_cgs_compat, -+ .probe = mt7988_infracfg_ao_cgs_probe, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+ .flags = DM_FLAG_PRE_RELOC, -+}; -+ -+/* ETHDMA */ -+ -+static const struct mtk_gate_regs ethdma_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETHDMA(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = ðdma_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate ethdma_mtk_gate[] = { -+ GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6), -+}; -+ -+static int mt7988_ethdma_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, -+ ethdma_mtk_gate); -+} -+ -+static int mt7988_ethdma_bind(struct udevice *dev) -+{ -+ int ret = 0; -+ -+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { -+ ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1); -+ if (ret) -+ debug("Warning: failed to bind reset controller\n"); -+ } -+ -+ return ret; -+} -+ -+static const struct udevice_id mt7988_ethdma_compat[] = { -+ { -+ .compatible = "mediatek,mt7988-ethdma", -+ }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_clk_ethdma) = { -+ .name = "mt7988-clock-ethdma", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_ethdma_compat, -+ .probe = mt7988_ethdma_probe, -+ .bind = mt7988_ethdma_bind, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; -+ -+/* SGMIISYS_0 */ -+ -+static const struct mtk_gate_regs sgmii0_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &sgmii0_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate sgmiisys_0_mtk_gate[] = { -+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ -+ GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2), -+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ -+ GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3), -+}; -+ -+static int mt7988_sgmiisys_0_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, -+ sgmiisys_0_mtk_gate); -+} -+ -+static const struct udevice_id mt7988_sgmiisys_0_compat[] = { -+ { -+ .compatible = "mediatek,mt7988-sgmiisys_0", -+ }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = { -+ .name = "mt7988-clock-sgmiisys_0", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_sgmiisys_0_compat, -+ .probe = mt7988_sgmiisys_0_probe, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; -+ -+/* SGMIISYS_1 */ -+ -+static const struct mtk_gate_regs sgmii1_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = &sgmii1_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate sgmiisys_1_mtk_gate[] = { -+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ -+ GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2), -+ /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ -+ GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3), -+}; -+ -+static int mt7988_sgmiisys_1_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, -+ sgmiisys_1_mtk_gate); -+} -+ -+static const struct udevice_id mt7988_sgmiisys_1_compat[] = { -+ { -+ .compatible = "mediatek,mt7988-sgmiisys_1", -+ }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = { -+ .name = "mt7988-clock-sgmiisys_1", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_sgmiisys_1_compat, -+ .probe = mt7988_sgmiisys_1_probe, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; -+ -+/* ETHWARP */ -+ -+static const struct mtk_gate_regs ethwarp_cg_regs = { -+ .set_ofs = 0x14, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x14, -+}; -+ -+#define GATE_ETHWARP(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .parent = _parent, .regs = ðwarp_cg_regs, \ -+ .shift = _shift, \ -+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ -+ } -+ -+static const struct mtk_gate ethwarp_mtk_gate[] = { -+ GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", -+ CK_TOP_NETSYS_WED_MCU, 13), -+ GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", -+ CK_TOP_NETSYS_WED_MCU, 14), -+ GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", -+ CK_TOP_NETSYS_WED_MCU, 15), -+}; -+ -+static int mt7988_ethwarp_probe(struct udevice *dev) -+{ -+ return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree, -+ ethwarp_mtk_gate); -+} -+ -+static int mt7988_ethwarp_bind(struct udevice *dev) -+{ -+ int ret = 0; -+ -+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { -+ ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2); -+ if (ret) -+ debug("Warning: failed to bind reset controller\n"); -+ } -+ -+ return ret; -+} -+ -+static const struct udevice_id mt7988_ethwarp_compat[] = { -+ { -+ .compatible = "mediatek,mt7988-ethwarp", -+ }, -+ {} -+}; -+ -+U_BOOT_DRIVER(mtk_clk_ethwarp) = { -+ .name = "mt7988-clock-ethwarp", -+ .id = UCLASS_CLK, -+ .of_match = mt7988_ethwarp_compat, -+ .probe = mt7988_ethwarp_probe, -+ .bind = mt7988_ethwarp_bind, -+ .priv_auto = sizeof(struct mtk_cg_priv), -+ .ops = &mtk_clk_gate_ops, -+}; ---- /dev/null -+++ b/include/dt-bindings/clock/mt7988-clk.h -@@ -0,0 +1,349 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2022 MediaTek Inc. All rights reserved. -+ * -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7988_H -+#define _DT_BINDINGS_CLK_MT7988_H -+ -+/* INFRACFG */ -+/* mtk_fixed_factor */ -+#define CK_INFRA_CK_F26M 0 -+#define CK_INFRA_PWM_O 1 -+#define CK_INFRA_PCIE_OCC_P0 2 -+#define CK_INFRA_PCIE_OCC_P1 3 -+#define CK_INFRA_PCIE_OCC_P2 4 -+#define CK_INFRA_PCIE_OCC_P3 5 -+#define CK_INFRA_133M_HCK 6 -+#define CK_INFRA_133M_PHCK 7 -+#define CK_INFRA_66M_PHCK 8 -+#define CK_INFRA_FAUD_L_O 9 -+#define CK_INFRA_FAUD_AUD_O 10 -+#define CK_INFRA_FAUD_EG2_O 11 -+#define CK_INFRA_I2C_O 12 -+#define CK_INFRA_UART_O0 13 -+#define CK_INFRA_UART_O1 14 -+#define CK_INFRA_UART_O2 15 -+#define CK_INFRA_NFI_O 16 -+#define CK_INFRA_SPINFI_O 17 -+#define CK_INFRA_SPI0_O 18 -+#define CK_INFRA_SPI1_O 19 -+#define CK_INFRA_LB_MUX_FRTC 20 -+#define CK_INFRA_FRTC 21 -+#define CK_INFRA_FMSDC400_O 22 -+#define CK_INFRA_FMSDC2_HCK_OCC 23 -+#define CK_INFRA_PERI_133M 24 -+#define CK_INFRA_USB_O 25 -+#define CK_INFRA_USB_O_P1 26 -+#define CK_INFRA_USB_FRMCNT_O 27 -+#define CK_INFRA_USB_FRMCNT_O_P1 28 -+#define CK_INFRA_USB_XHCI_O 29 -+#define CK_INFRA_USB_XHCI_O_P1 30 -+#define CK_INFRA_USB_PIPE_O 31 -+#define CK_INFRA_USB_PIPE_O_P1 32 -+#define CK_INFRA_USB_UTMI_O 33 -+#define CK_INFRA_USB_UTMI_O_P1 34 -+#define CK_INFRA_PCIE_PIPE_OCC_P0 35 -+#define CK_INFRA_PCIE_PIPE_OCC_P1 36 -+#define CK_INFRA_PCIE_PIPE_OCC_P2 37 -+#define CK_INFRA_PCIE_PIPE_OCC_P3 38 -+#define CK_INFRA_F26M_O0 39 -+#define CK_INFRA_F26M_O1 40 -+#define CK_INFRA_133M_MCK 41 -+#define CK_INFRA_66M_MCK 42 -+#define CK_INFRA_PERI_66M_O 43 -+#define CK_INFRA_USB_SYS_O 44 -+#define CK_INFRA_USB_SYS_O_P1 45 -+ -+/* INFRACFG_AO */ -+#define GATE_OFFSET 65 -+/* mtk_mux */ -+#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */ -+#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */ -+#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */ -+#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */ -+#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */ -+#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */ -+#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */ -+#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */ -+#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */ -+#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */ -+#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */ -+#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */ -+#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */ -+#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */ -+#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */ -+#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */ -+#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */ -+#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */ -+#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */ -+/* mtk_gate */ -+#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */ -+#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */ -+#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */ -+#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */ -+#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */ -+#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */ -+#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */ -+#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */ -+#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */ -+#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */ -+#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */ -+#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */ -+#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */ -+#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */ -+#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */ -+#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */ -+#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */ -+#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */ -+#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */ -+#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */ -+#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */ -+#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */ -+#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */ -+#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */ -+#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */ -+#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */ -+#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */ -+#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */ -+#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */ -+#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */ -+#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */ -+#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */ -+#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */ -+#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */ -+#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */ -+#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */ -+#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */ -+#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */ -+#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */ -+#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */ -+#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */ -+#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */ -+#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */ -+#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */ -+#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */ -+#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */ -+#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */ -+#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */ -+#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */ -+#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */ -+#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */ -+#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */ -+#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */ -+#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */ -+#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */ -+#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */ -+#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */ -+#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */ -+#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */ -+#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */ -+#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */ -+#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */ -+#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */ -+#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */ -+#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */ -+#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */ -+#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */ -+#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */ -+#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */ -+#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */ -+#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */ -+#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */ -+#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */ -+#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */ -+#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */ -+#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */ -+#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */ -+#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */ -+#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */ -+#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */ -+#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */ -+#define CK_INFRA_PCIE_PERI_26M_CK_P1 \ -+ (146 - GATE_OFFSET) /* Linux CLK ID (100) */ -+#define CK_INFRA_PCIE_PERI_26M_CK_P2 \ -+ (147 - GATE_OFFSET) /* Linux CLK ID (101) */ -+#define CK_INFRA_PCIE_PERI_26M_CK_P3 \ -+ (148 - GATE_OFFSET) /* Linux CLK ID (102) */ -+ -+/* TOPCKGEN */ -+/* mtk_fixed_factor */ -+#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */ -+#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */ -+#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */ -+#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */ -+#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */ -+#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ -+#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ -+#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */ -+#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */ -+#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */ -+#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */ -+#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */ -+#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */ -+#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */ -+#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */ -+#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */ -+#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ -+#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ -+#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */ -+#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */ -+#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ -+#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ -+#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */ -+#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */ -+#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */ -+#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */ -+#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */ -+#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */ -+#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */ -+#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */ -+#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */ -+#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */ -+#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */ -+#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */ -+#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */ -+#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */ -+#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */ -+#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */ -+#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */ -+#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */ -+#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */ -+#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */ -+#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */ -+#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */ -+#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */ -+#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */ -+#define CK_TOP_SPI 46 /* Linux CLK ID (120) */ -+#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */ -+#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */ -+#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */ -+#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */ -+#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */ -+#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */ -+#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */ -+#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */ -+#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */ -+#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */ -+#define CK_TOP_AUD 57 /* Linux CLK ID (131) */ -+#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */ -+#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */ -+#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */ -+#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */ -+#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */ -+#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */ -+#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */ -+/* mtk_mux */ -+#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */ -+#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */ -+#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */ -+#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */ -+#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */ -+#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */ -+#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */ -+#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */ -+#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */ -+#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */ -+#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */ -+#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */ -+#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */ -+#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */ -+#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */ -+#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */ -+#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */ -+#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */ -+#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */ -+#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */ -+#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */ -+#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */ -+#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */ -+#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */ -+#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */ -+#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */ -+#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */ -+#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */ -+#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */ -+#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */ -+#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */ -+#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */ -+#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */ -+#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */ -+#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */ -+#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */ -+#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */ -+#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */ -+#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */ -+#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */ -+#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */ -+#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */ -+#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */ -+#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */ -+#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */ -+#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */ -+#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */ -+#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */ -+#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */ -+#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */ -+#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */ -+#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */ -+#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */ -+#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */ -+#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */ -+#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */ -+#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */ -+#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */ -+#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */ -+#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */ -+#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */ -+#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */ -+#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */ -+#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */ -+#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */ -+#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */ -+#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */ -+#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */ -+#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */ -+#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */ -+#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */ -+#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */ -+#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */ -+#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */ -+ -+/* APMIXEDSYS */ -+/* mtk_pll_data */ -+#define CK_APMIXED_NETSYSPLL 0 -+#define CK_APMIXED_MPLL 1 -+#define CK_APMIXED_MMPLL 2 -+#define CK_APMIXED_APLL2 3 -+#define CK_APMIXED_NET1PLL 4 -+#define CK_APMIXED_NET2PLL 5 -+#define CK_APMIXED_WEDMCUPLL 6 -+#define CK_APMIXED_SGMPLL 7 -+#define CK_APMIXED_ARM_B 8 -+#define CK_APMIXED_CCIPLL2_B 9 -+#define CK_APMIXED_USXGMIIPLL 10 -+#define CK_APMIXED_MSDCPLL 11 -+ -+/* ETHSYS ETH DMA */ -+/* mtk_gate */ -+#define CK_ETHDMA_FE_EN 0 -+ -+/* SGMIISYS_0 */ -+/* mtk_gate */ -+#define CK_SGM0_TX_EN 0 -+#define CK_SGM0_RX_EN 1 -+ -+/* SGMIISYS_1 */ -+/* mtk_gate */ -+#define CK_SGM1_TX_EN 0 -+#define CK_SGM1_RX_EN 1 -+ -+/* ETHWARP */ -+/* mtk_gate */ -+#define CK_ETHWARP_WOCPU2_EN 0 -+#define CK_ETHWARP_WOCPU1_EN 1 -+#define CK_ETHWARP_WOCPU0_EN 2 -+ -+#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch b/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch deleted file mode 100644 index f14c383638..0000000000 --- a/package/boot/uboot-mediatek/patches/101-11-reset-mediatek-add-reset-definition-for-MediaTek-MT7.patch +++ /dev/null @@ -1,49 +0,0 @@ -From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:33 +0800 -Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek - MT7988 SoC - -This patch adds reset bits for MediaTek MT7988 - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++ - 1 file changed, 31 insertions(+) - create mode 100644 include/dt-bindings/reset/mt7988-reset.h - ---- /dev/null -+++ b/include/dt-bindings/reset/mt7988-reset.h -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ */ -+ -+#ifndef _DT_BINDINGS_MTK_RESET_H_ -+#define _DT_BINDINGS_MTK_RESET_H_ -+ -+/* ETHDMA Subsystem resets */ -+#define ETHDMA_FE_RST 6 -+#define ETHDMA_PMTR_RST 8 -+#define ETHDMA_GMAC_RST 23 -+#define ETHDMA_WDMA0_RST 24 -+#define ETHDMA_WDMA1_RST 25 -+#define ETHDMA_WDMA2_RST 26 -+#define ETHDMA_PPE0_RST 29 -+#define ETHDMA_PPE1_RST 30 -+#define ETHDMA_PPE2_RST 31 -+ -+/* ETHWARP Subsystem resets */ -+#define ETHWARP_GSW_RST 9 -+#define ETHWARP_EIP197_RST 10 -+#define ETHWARP_WOCPU0_RST 32 -+#define ETHWARP_WOCPU1_RST 33 -+#define ETHWARP_WOCPU2_RST 34 -+#define ETHWARP_WOX_NET_MUX_RST 35 -+#define ETHWARP_WED0_RST 36 -+#define ETHWARP_WED1_RST 37 -+#define ETHWARP_WED2_RST 38 -+ -+#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch b/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch deleted file mode 100644 index 4085f11541..0000000000 --- a/package/boot/uboot-mediatek/patches/101-12-pinctrl-mediatek-convert-most-definitions-to-const.patch +++ /dev/null @@ -1,2267 +0,0 @@ -From 30227fcf55ac95ad6778de2fc3e6d1e00cf82566 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:37 +0800 -Subject: [PATCH 12/29] pinctrl: mediatek: convert most definitions to const - -There exists a situation of the mediatek pinctrl driver that may return -wrong pin function value for the pinmux driver: -- All pin function arrays are defined without const -- Some pin function arrays contain all-zero value, e.g.: - static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; -- These arrays will be put into .bss section during compilation -- .bss section has no "a" attribute and does not exist in the final binary - file after objcopy. -- FDT binary blob is appended to the u-boot binary, which occupies the - .bss section. -- During board_f stage, .bss has not been initialized, and contains the - data of FDT, which is not full-zero data. -- pinctrl driver is initialized in board_f stage, and it will get wrong - data if another driver is going to set default pinctrl. - -Since pinmux information and soc data are only meant to be read-only, thus -should be declared as const. This will force all pinctrl data being put -into .rodata section. Since .rodata has "a" attribute, even the all-zero -data will be allocated and filled with correct value in to u-boot binary. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mt7622.c | 474 ++++++------- - drivers/pinctrl/mediatek/pinctrl-mt7623.c | 650 +++++++++--------- - drivers/pinctrl/mediatek/pinctrl-mt7629.c | 174 ++--- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 270 ++++---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 145 ++-- - drivers/pinctrl/mediatek/pinctrl-mt8512.c | 24 +- - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 18 +- - drivers/pinctrl/mediatek/pinctrl-mt8518.c | 20 +- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 +- - drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +- - 10 files changed, 898 insertions(+), 889 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c -@@ -233,283 +233,285 @@ static const struct mtk_pin_desc mt7622_ - */ - - /* EMMC */ --static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; --static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+static const int mt7622_emmc_pins[] = { -+ 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; -+static const int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - --static int mt7622_emmc_rst_pins[] = { 37, }; --static int mt7622_emmc_rst_funcs[] = { 1, }; -+static const int mt7622_emmc_rst_pins[] = { 37, }; -+static const int mt7622_emmc_rst_funcs[] = { 1, }; - - /* LED for EPHY */ --static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; --static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; --static int mt7622_ephy0_led_pins[] = { 86, }; --static int mt7622_ephy0_led_funcs[] = { 0, }; --static int mt7622_ephy1_led_pins[] = { 91, }; --static int mt7622_ephy1_led_funcs[] = { 2, }; --static int mt7622_ephy2_led_pins[] = { 92, }; --static int mt7622_ephy2_led_funcs[] = { 2, }; --static int mt7622_ephy3_led_pins[] = { 93, }; --static int mt7622_ephy3_led_funcs[] = { 2, }; --static int mt7622_ephy4_led_pins[] = { 94, }; --static int mt7622_ephy4_led_funcs[] = { 2, }; -+static const int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; -+static const int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; -+static const int mt7622_ephy0_led_pins[] = { 86, }; -+static const int mt7622_ephy0_led_funcs[] = { 0, }; -+static const int mt7622_ephy1_led_pins[] = { 91, }; -+static const int mt7622_ephy1_led_funcs[] = { 2, }; -+static const int mt7622_ephy2_led_pins[] = { 92, }; -+static const int mt7622_ephy2_led_funcs[] = { 2, }; -+static const int mt7622_ephy3_led_pins[] = { 93, }; -+static const int mt7622_ephy3_led_funcs[] = { 2, }; -+static const int mt7622_ephy4_led_pins[] = { 94, }; -+static const int mt7622_ephy4_led_funcs[] = { 2, }; - - /* Embedded Switch */ --static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, -- 62, 63, 64, 65, 66, 67, 68, 69, 70, }; --static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, 0, 0, 0, 0, 0, 0, }; --static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; --static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; --static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, -- 68, 69, 70, }; --static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, }; -+static const int mt7622_esw_pins[] = { -+ 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, -+ 69, 70, }; -+static const int mt7622_esw_funcs[] = { -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -+static const int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; -+static const int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -+static const int mt7622_esw_p2_p3_p4_pins[] = { -+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; -+static const int mt7622_esw_p2_p3_p4_funcs[] = { -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; - /* RGMII via ESW */ --static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, -- 67, 68, 69, 70, }; --static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, }; -+static const int mt7622_rgmii_via_esw_pins[] = { -+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; -+static const int mt7622_rgmii_via_esw_funcs[] = { -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; - - /* RGMII via GMAC1 */ --static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, -- 67, 68, 69, 70, }; --static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, }; -+static const int mt7622_rgmii_via_gmac1_pins[] = { -+ 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, }; -+static const int mt7622_rgmii_via_gmac1_funcs[] = { -+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - - /* RGMII via GMAC2 */ --static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, -- 33, 34, 35, 36, }; --static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, }; -+static const int mt7622_rgmii_via_gmac2_pins[] = { -+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, }; -+static const int mt7622_rgmii_via_gmac2_funcs[] = { -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; - - /* I2C */ --static int mt7622_i2c0_pins[] = { 14, 15, }; --static int mt7622_i2c0_funcs[] = { 0, 0, }; --static int mt7622_i2c1_0_pins[] = { 55, 56, }; --static int mt7622_i2c1_0_funcs[] = { 0, 0, }; --static int mt7622_i2c1_1_pins[] = { 73, 74, }; --static int mt7622_i2c1_1_funcs[] = { 3, 3, }; --static int mt7622_i2c1_2_pins[] = { 87, 88, }; --static int mt7622_i2c1_2_funcs[] = { 0, 0, }; --static int mt7622_i2c2_0_pins[] = { 57, 58, }; --static int mt7622_i2c2_0_funcs[] = { 0, 0, }; --static int mt7622_i2c2_1_pins[] = { 75, 76, }; --static int mt7622_i2c2_1_funcs[] = { 3, 3, }; --static int mt7622_i2c2_2_pins[] = { 89, 90, }; --static int mt7622_i2c2_2_funcs[] = { 0, 0, }; -+static const int mt7622_i2c0_pins[] = { 14, 15, }; -+static const int mt7622_i2c0_funcs[] = { 0, 0, }; -+static const int mt7622_i2c1_0_pins[] = { 55, 56, }; -+static const int mt7622_i2c1_0_funcs[] = { 0, 0, }; -+static const int mt7622_i2c1_1_pins[] = { 73, 74, }; -+static const int mt7622_i2c1_1_funcs[] = { 3, 3, }; -+static const int mt7622_i2c1_2_pins[] = { 87, 88, }; -+static const int mt7622_i2c1_2_funcs[] = { 0, 0, }; -+static const int mt7622_i2c2_0_pins[] = { 57, 58, }; -+static const int mt7622_i2c2_0_funcs[] = { 0, 0, }; -+static const int mt7622_i2c2_1_pins[] = { 75, 76, }; -+static const int mt7622_i2c2_1_funcs[] = { 3, 3, }; -+static const int mt7622_i2c2_2_pins[] = { 89, 90, }; -+static const int mt7622_i2c2_2_funcs[] = { 0, 0, }; - - /* I2S */ --static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; --static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; --static int mt7622_i2s1_in_data_pins[] = { 1, }; --static int mt7622_i2s1_in_data_funcs[] = { 0, }; --static int mt7622_i2s2_in_data_pins[] = { 16, }; --static int mt7622_i2s2_in_data_funcs[] = { 0, }; --static int mt7622_i2s3_in_data_pins[] = { 17, }; --static int mt7622_i2s3_in_data_funcs[] = { 0, }; --static int mt7622_i2s4_in_data_pins[] = { 18, }; --static int mt7622_i2s4_in_data_funcs[] = { 0, }; --static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; --static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; --static int mt7622_i2s1_out_data_pins[] = { 2, }; --static int mt7622_i2s1_out_data_funcs[] = { 0, }; --static int mt7622_i2s2_out_data_pins[] = { 19, }; --static int mt7622_i2s2_out_data_funcs[] = { 0, }; --static int mt7622_i2s3_out_data_pins[] = { 20, }; --static int mt7622_i2s3_out_data_funcs[] = { 0, }; --static int mt7622_i2s4_out_data_pins[] = { 21, }; --static int mt7622_i2s4_out_data_funcs[] = { 0, }; -+static const int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; -+static const int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; -+static const int mt7622_i2s1_in_data_pins[] = { 1, }; -+static const int mt7622_i2s1_in_data_funcs[] = { 0, }; -+static const int mt7622_i2s2_in_data_pins[] = { 16, }; -+static const int mt7622_i2s2_in_data_funcs[] = { 0, }; -+static const int mt7622_i2s3_in_data_pins[] = { 17, }; -+static const int mt7622_i2s3_in_data_funcs[] = { 0, }; -+static const int mt7622_i2s4_in_data_pins[] = { 18, }; -+static const int mt7622_i2s4_in_data_funcs[] = { 0, }; -+static const int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; -+static const int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; -+static const int mt7622_i2s1_out_data_pins[] = { 2, }; -+static const int mt7622_i2s1_out_data_funcs[] = { 0, }; -+static const int mt7622_i2s2_out_data_pins[] = { 19, }; -+static const int mt7622_i2s2_out_data_funcs[] = { 0, }; -+static const int mt7622_i2s3_out_data_pins[] = { 20, }; -+static const int mt7622_i2s3_out_data_funcs[] = { 0, }; -+static const int mt7622_i2s4_out_data_pins[] = { 21, }; -+static const int mt7622_i2s4_out_data_funcs[] = { 0, }; - - /* IR */ --static int mt7622_ir_0_tx_pins[] = { 16, }; --static int mt7622_ir_0_tx_funcs[] = { 4, }; --static int mt7622_ir_1_tx_pins[] = { 59, }; --static int mt7622_ir_1_tx_funcs[] = { 5, }; --static int mt7622_ir_2_tx_pins[] = { 99, }; --static int mt7622_ir_2_tx_funcs[] = { 3, }; --static int mt7622_ir_0_rx_pins[] = { 17, }; --static int mt7622_ir_0_rx_funcs[] = { 4, }; --static int mt7622_ir_1_rx_pins[] = { 60, }; --static int mt7622_ir_1_rx_funcs[] = { 5, }; --static int mt7622_ir_2_rx_pins[] = { 100, }; --static int mt7622_ir_2_rx_funcs[] = { 3, }; -+static const int mt7622_ir_0_tx_pins[] = { 16, }; -+static const int mt7622_ir_0_tx_funcs[] = { 4, }; -+static const int mt7622_ir_1_tx_pins[] = { 59, }; -+static const int mt7622_ir_1_tx_funcs[] = { 5, }; -+static const int mt7622_ir_2_tx_pins[] = { 99, }; -+static const int mt7622_ir_2_tx_funcs[] = { 3, }; -+static const int mt7622_ir_0_rx_pins[] = { 17, }; -+static const int mt7622_ir_0_rx_funcs[] = { 4, }; -+static const int mt7622_ir_1_rx_pins[] = { 60, }; -+static const int mt7622_ir_1_rx_funcs[] = { 5, }; -+static const int mt7622_ir_2_rx_pins[] = { 100, }; -+static const int mt7622_ir_2_rx_funcs[] = { 3, }; - - /* MDIO */ --static int mt7622_mdc_mdio_pins[] = { 23, 24, }; --static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; -+static const int mt7622_mdc_mdio_pins[] = { 23, 24, }; -+static const int mt7622_mdc_mdio_funcs[] = { 0, 0, }; - - /* PCIE */ --static int mt7622_pcie0_0_waken_pins[] = { 14, }; --static int mt7622_pcie0_0_waken_funcs[] = { 2, }; --static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; --static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; --static int mt7622_pcie0_1_waken_pins[] = { 79, }; --static int mt7622_pcie0_1_waken_funcs[] = { 4, }; --static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; --static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; --static int mt7622_pcie1_0_waken_pins[] = { 14, }; --static int mt7622_pcie1_0_waken_funcs[] = { 3, }; --static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; --static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; -- --static int mt7622_pcie0_pad_perst_pins[] = { 83, }; --static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; --static int mt7622_pcie1_pad_perst_pins[] = { 84, }; --static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; -+static const int mt7622_pcie0_0_waken_pins[] = { 14, }; -+static const int mt7622_pcie0_0_waken_funcs[] = { 2, }; -+static const int mt7622_pcie0_0_clkreq_pins[] = { 15, }; -+static const int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; -+static const int mt7622_pcie0_1_waken_pins[] = { 79, }; -+static const int mt7622_pcie0_1_waken_funcs[] = { 4, }; -+static const int mt7622_pcie0_1_clkreq_pins[] = { 80, }; -+static const int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; -+static const int mt7622_pcie1_0_waken_pins[] = { 14, }; -+static const int mt7622_pcie1_0_waken_funcs[] = { 3, }; -+static const int mt7622_pcie1_0_clkreq_pins[] = { 15, }; -+static const int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; -+ -+static const int mt7622_pcie0_pad_perst_pins[] = { 83, }; -+static const int mt7622_pcie0_pad_perst_funcs[] = { 0, }; -+static const int mt7622_pcie1_pad_perst_pins[] = { 84, }; -+static const int mt7622_pcie1_pad_perst_funcs[] = { 0, }; - - /* PMIC bus */ --static int mt7622_pmic_bus_pins[] = { 71, 72, }; --static int mt7622_pmic_bus_funcs[] = { 0, 0, }; -+static const int mt7622_pmic_bus_pins[] = { 71, 72, }; -+static const int mt7622_pmic_bus_funcs[] = { 0, 0, }; - - /* Parallel NAND */ --static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, -- 48, 49, 50, }; --static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, }; -+static const int mt7622_pnand_pins[] = { -+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, }; -+static const int mt7622_pnand_funcs[] = { -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; - - /* PWM */ --static int mt7622_pwm_ch1_0_pins[] = { 51, }; --static int mt7622_pwm_ch1_0_funcs[] = { 3, }; --static int mt7622_pwm_ch1_1_pins[] = { 73, }; --static int mt7622_pwm_ch1_1_funcs[] = { 4, }; --static int mt7622_pwm_ch1_2_pins[] = { 95, }; --static int mt7622_pwm_ch1_2_funcs[] = { 0, }; --static int mt7622_pwm_ch2_0_pins[] = { 52, }; --static int mt7622_pwm_ch2_0_funcs[] = { 3, }; --static int mt7622_pwm_ch2_1_pins[] = { 74, }; --static int mt7622_pwm_ch2_1_funcs[] = { 4, }; --static int mt7622_pwm_ch2_2_pins[] = { 96, }; --static int mt7622_pwm_ch2_2_funcs[] = { 0, }; --static int mt7622_pwm_ch3_0_pins[] = { 53, }; --static int mt7622_pwm_ch3_0_funcs[] = { 3, }; --static int mt7622_pwm_ch3_1_pins[] = { 75, }; --static int mt7622_pwm_ch3_1_funcs[] = { 4, }; --static int mt7622_pwm_ch3_2_pins[] = { 97, }; --static int mt7622_pwm_ch3_2_funcs[] = { 0, }; --static int mt7622_pwm_ch4_0_pins[] = { 54, }; --static int mt7622_pwm_ch4_0_funcs[] = { 3, }; --static int mt7622_pwm_ch4_1_pins[] = { 67, }; --static int mt7622_pwm_ch4_1_funcs[] = { 3, }; --static int mt7622_pwm_ch4_2_pins[] = { 76, }; --static int mt7622_pwm_ch4_2_funcs[] = { 4, }; --static int mt7622_pwm_ch4_3_pins[] = { 98, }; --static int mt7622_pwm_ch4_3_funcs[] = { 0, }; --static int mt7622_pwm_ch5_0_pins[] = { 68, }; --static int mt7622_pwm_ch5_0_funcs[] = { 3, }; --static int mt7622_pwm_ch5_1_pins[] = { 77, }; --static int mt7622_pwm_ch5_1_funcs[] = { 4, }; --static int mt7622_pwm_ch5_2_pins[] = { 99, }; --static int mt7622_pwm_ch5_2_funcs[] = { 0, }; --static int mt7622_pwm_ch6_0_pins[] = { 69, }; --static int mt7622_pwm_ch6_0_funcs[] = { 3, }; --static int mt7622_pwm_ch6_1_pins[] = { 78, }; --static int mt7622_pwm_ch6_1_funcs[] = { 4, }; --static int mt7622_pwm_ch6_2_pins[] = { 81, }; --static int mt7622_pwm_ch6_2_funcs[] = { 4, }; --static int mt7622_pwm_ch6_3_pins[] = { 100, }; --static int mt7622_pwm_ch6_3_funcs[] = { 0, }; --static int mt7622_pwm_ch7_0_pins[] = { 70, }; --static int mt7622_pwm_ch7_0_funcs[] = { 3, }; --static int mt7622_pwm_ch7_1_pins[] = { 82, }; --static int mt7622_pwm_ch7_1_funcs[] = { 4, }; --static int mt7622_pwm_ch7_2_pins[] = { 101, }; --static int mt7622_pwm_ch7_2_funcs[] = { 0, }; -+static const int mt7622_pwm_ch1_0_pins[] = { 51, }; -+static const int mt7622_pwm_ch1_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch1_1_pins[] = { 73, }; -+static const int mt7622_pwm_ch1_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch1_2_pins[] = { 95, }; -+static const int mt7622_pwm_ch1_2_funcs[] = { 0, }; -+static const int mt7622_pwm_ch2_0_pins[] = { 52, }; -+static const int mt7622_pwm_ch2_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch2_1_pins[] = { 74, }; -+static const int mt7622_pwm_ch2_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch2_2_pins[] = { 96, }; -+static const int mt7622_pwm_ch2_2_funcs[] = { 0, }; -+static const int mt7622_pwm_ch3_0_pins[] = { 53, }; -+static const int mt7622_pwm_ch3_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch3_1_pins[] = { 75, }; -+static const int mt7622_pwm_ch3_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch3_2_pins[] = { 97, }; -+static const int mt7622_pwm_ch3_2_funcs[] = { 0, }; -+static const int mt7622_pwm_ch4_0_pins[] = { 54, }; -+static const int mt7622_pwm_ch4_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch4_1_pins[] = { 67, }; -+static const int mt7622_pwm_ch4_1_funcs[] = { 3, }; -+static const int mt7622_pwm_ch4_2_pins[] = { 76, }; -+static const int mt7622_pwm_ch4_2_funcs[] = { 4, }; -+static const int mt7622_pwm_ch4_3_pins[] = { 98, }; -+static const int mt7622_pwm_ch4_3_funcs[] = { 0, }; -+static const int mt7622_pwm_ch5_0_pins[] = { 68, }; -+static const int mt7622_pwm_ch5_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch5_1_pins[] = { 77, }; -+static const int mt7622_pwm_ch5_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch5_2_pins[] = { 99, }; -+static const int mt7622_pwm_ch5_2_funcs[] = { 0, }; -+static const int mt7622_pwm_ch6_0_pins[] = { 69, }; -+static const int mt7622_pwm_ch6_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch6_1_pins[] = { 78, }; -+static const int mt7622_pwm_ch6_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch6_2_pins[] = { 81, }; -+static const int mt7622_pwm_ch6_2_funcs[] = { 4, }; -+static const int mt7622_pwm_ch6_3_pins[] = { 100, }; -+static const int mt7622_pwm_ch6_3_funcs[] = { 0, }; -+static const int mt7622_pwm_ch7_0_pins[] = { 70, }; -+static const int mt7622_pwm_ch7_0_funcs[] = { 3, }; -+static const int mt7622_pwm_ch7_1_pins[] = { 82, }; -+static const int mt7622_pwm_ch7_1_funcs[] = { 4, }; -+static const int mt7622_pwm_ch7_2_pins[] = { 101, }; -+static const int mt7622_pwm_ch7_2_funcs[] = { 0, }; - - /* SD */ --static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; --static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; --static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; --static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+static const int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static const int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+static const int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; -+static const int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; - - /* Serial NAND */ --static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; --static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+static const int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; -+static const int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; - - /* SPI NOR */ --static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; --static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; -+static const int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; -+static const int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; - - /* SPIC */ --static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; --static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; --static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; --static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; --static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; --static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; --static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; --static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; --static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; --static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; --static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; --static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; -+static const int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; -+static const int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; -+static const int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; -+static const int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; -+static const int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; -+static const int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; -+static const int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; -+static const int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; -+static const int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; - - /* TDM */ --static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; --static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; --static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; --static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; --static int mt7622_tdm_0_out_data_pins[] = { 20, }; --static int mt7622_tdm_0_out_data_funcs[] = { 3, }; --static int mt7622_tdm_0_in_data_pins[] = { 21, }; --static int mt7622_tdm_0_in_data_funcs[] = { 3, }; --static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; --static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; --static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; --static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; --static int mt7622_tdm_1_out_data_pins[] = { 55, }; --static int mt7622_tdm_1_out_data_funcs[] = { 3, }; --static int mt7622_tdm_1_in_data_pins[] = { 56, }; --static int mt7622_tdm_1_in_data_funcs[] = { 3, }; -+static const int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; -+static const int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -+static const int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; -+static const int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -+static const int mt7622_tdm_0_out_data_pins[] = { 20, }; -+static const int mt7622_tdm_0_out_data_funcs[] = { 3, }; -+static const int mt7622_tdm_0_in_data_pins[] = { 21, }; -+static const int mt7622_tdm_0_in_data_funcs[] = { 3, }; -+static const int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; -+static const int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -+static const int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; -+static const int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; -+static const int mt7622_tdm_1_out_data_pins[] = { 55, }; -+static const int mt7622_tdm_1_out_data_funcs[] = { 3, }; -+static const int mt7622_tdm_1_in_data_pins[] = { 56, }; -+static const int mt7622_tdm_1_in_data_funcs[] = { 3, }; - - /* UART */ --static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; --static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; --static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; --static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; --static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; --static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; --static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; --static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; --static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; --static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; --static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; --static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; --static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; --static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; --static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; --static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; --static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; --static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; --static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; --static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; --static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; --static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; --static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; --static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; --static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; --static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; --static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; --static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; --static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; --static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; --static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; --static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; --static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; --static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; --static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; --static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; --static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; --static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; --static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; --static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; -+static const int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; -+static const int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; -+static const int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; -+static const int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; -+static const int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; -+static const int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; -+static const int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; -+static const int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; -+static const int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; -+static const int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; -+static const int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; -+static const int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; -+static const int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; -+static const int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; -+static const int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; -+static const int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; -+static const int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; -+static const int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; -+static const int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; -+static const int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; -+static const int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; -+static const int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; -+static const int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; -+static const int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; -+static const int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; -+static const int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; -+static const int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; -+static const int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; -+static const int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; -+static const int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; -+static const int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; -+static const int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; -+static const int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; -+static const int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; -+static const int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; -+static const int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; -+static const int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; -+static const int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; -+static const int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; -+static const int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; - - /* Watchdog */ --static int mt7622_watchdog_pins[] = { 78, }; --static int mt7622_watchdog_funcs[] = { 0, }; -+static const int mt7622_watchdog_pins[] = { 78, }; -+static const int mt7622_watchdog_funcs[] = { 0, }; - - /* WLAN LED */ --static int mt7622_wled_pins[] = { 85, }; --static int mt7622_wled_funcs[] = { 0, }; -+static const int mt7622_wled_pins[] = { 85, }; -+static const int mt7622_wled_funcs[] = { 0, }; - - static const struct mtk_group_desc mt7622_groups[] = { - PINCTRL_PIN_GROUP("emmc", mt7622_emmc), -@@ -719,7 +721,7 @@ static const struct mtk_function_desc mt - {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, - }; - --static struct mtk_pinctrl_soc mt7622_data = { -+static const struct mtk_pinctrl_soc mt7622_data = { - .name = "mt7622_pinctrl", - .reg_cal = mt7622_reg_cals, - .pins = mt7622_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c -@@ -692,377 +692,377 @@ static const struct mtk_pin_desc mt7623_ - */ - - /* AUDIO EXT CLK */ --static int mt7623_aud_ext_clk0_pins[] = { 208, }; --static int mt7623_aud_ext_clk0_funcs[] = { 1, }; --static int mt7623_aud_ext_clk1_pins[] = { 209, }; --static int mt7623_aud_ext_clk1_funcs[] = { 1, }; -+static const int mt7623_aud_ext_clk0_pins[] = { 208, }; -+static const int mt7623_aud_ext_clk0_funcs[] = { 1, }; -+static const int mt7623_aud_ext_clk1_pins[] = { 209, }; -+static const int mt7623_aud_ext_clk1_funcs[] = { 1, }; - - /* DISP PWM */ --static int mt7623_disp_pwm_0_pins[] = { 72, }; --static int mt7623_disp_pwm_0_funcs[] = { 5, }; --static int mt7623_disp_pwm_1_pins[] = { 203, }; --static int mt7623_disp_pwm_1_funcs[] = { 2, }; --static int mt7623_disp_pwm_2_pins[] = { 208, }; --static int mt7623_disp_pwm_2_funcs[] = { 5, }; -+static const int mt7623_disp_pwm_0_pins[] = { 72, }; -+static const int mt7623_disp_pwm_0_funcs[] = { 5, }; -+static const int mt7623_disp_pwm_1_pins[] = { 203, }; -+static const int mt7623_disp_pwm_1_funcs[] = { 2, }; -+static const int mt7623_disp_pwm_2_pins[] = { 208, }; -+static const int mt7623_disp_pwm_2_funcs[] = { 5, }; - - /* ESW */ --static int mt7623_esw_int_pins[] = { 273, }; --static int mt7623_esw_int_funcs[] = { 1, }; --static int mt7623_esw_rst_pins[] = { 277, }; --static int mt7623_esw_rst_funcs[] = { 1, }; -+static const int mt7623_esw_int_pins[] = { 273, }; -+static const int mt7623_esw_int_funcs[] = { 1, }; -+static const int mt7623_esw_rst_pins[] = { 277, }; -+static const int mt7623_esw_rst_funcs[] = { 1, }; - - /* EPHY */ --static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, -- 269, 270, 271, 272, 274, }; --static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, -+ 269, 270, 271, 272, 274, }; -+static const int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - /* EXT_SDIO */ --static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; --static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; -+static const int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; - - /* HDMI RX */ --static int mt7623_hdmi_rx_pins[] = { 247, 248, }; --static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; --static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; --static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; -+static const int mt7623_hdmi_rx_pins[] = { 247, 248, }; -+static const int mt7623_hdmi_rx_funcs[] = { 1, 1 }; -+static const int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; -+static const int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; - - /* HDMI TX */ --static int mt7623_hdmi_cec_pins[] = { 122, }; --static int mt7623_hdmi_cec_funcs[] = { 1, }; --static int mt7623_hdmi_htplg_pins[] = { 123, }; --static int mt7623_hdmi_htplg_funcs[] = { 1, }; --static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; --static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; -+static const int mt7623_hdmi_cec_pins[] = { 122, }; -+static const int mt7623_hdmi_cec_funcs[] = { 1, }; -+static const int mt7623_hdmi_htplg_pins[] = { 123, }; -+static const int mt7623_hdmi_htplg_funcs[] = { 1, }; -+static const int mt7623_hdmi_i2c_pins[] = { 124, 125, }; -+static const int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; - - /* I2C */ --static int mt7623_i2c0_pins[] = { 75, 76, }; --static int mt7623_i2c0_funcs[] = { 1, 1, }; --static int mt7623_i2c1_0_pins[] = { 57, 58, }; --static int mt7623_i2c1_0_funcs[] = { 1, 1, }; --static int mt7623_i2c1_1_pins[] = { 242, 243, }; --static int mt7623_i2c1_1_funcs[] = { 4, 4, }; --static int mt7623_i2c1_2_pins[] = { 85, 86, }; --static int mt7623_i2c1_2_funcs[] = { 3, 3, }; --static int mt7623_i2c1_3_pins[] = { 105, 106, }; --static int mt7623_i2c1_3_funcs[] = { 3, 3, }; --static int mt7623_i2c1_4_pins[] = { 124, 125, }; --static int mt7623_i2c1_4_funcs[] = { 4, 4, }; --static int mt7623_i2c2_0_pins[] = { 77, 78, }; --static int mt7623_i2c2_0_funcs[] = { 1, 1, }; --static int mt7623_i2c2_1_pins[] = { 89, 90, }; --static int mt7623_i2c2_1_funcs[] = { 3, 3, }; --static int mt7623_i2c2_2_pins[] = { 109, 110, }; --static int mt7623_i2c2_2_funcs[] = { 3, 3, }; --static int mt7623_i2c2_3_pins[] = { 122, 123, }; --static int mt7623_i2c2_3_funcs[] = { 4, 4, }; -+static const int mt7623_i2c0_pins[] = { 75, 76, }; -+static const int mt7623_i2c0_funcs[] = { 1, 1, }; -+static const int mt7623_i2c1_0_pins[] = { 57, 58, }; -+static const int mt7623_i2c1_0_funcs[] = { 1, 1, }; -+static const int mt7623_i2c1_1_pins[] = { 242, 243, }; -+static const int mt7623_i2c1_1_funcs[] = { 4, 4, }; -+static const int mt7623_i2c1_2_pins[] = { 85, 86, }; -+static const int mt7623_i2c1_2_funcs[] = { 3, 3, }; -+static const int mt7623_i2c1_3_pins[] = { 105, 106, }; -+static const int mt7623_i2c1_3_funcs[] = { 3, 3, }; -+static const int mt7623_i2c1_4_pins[] = { 124, 125, }; -+static const int mt7623_i2c1_4_funcs[] = { 4, 4, }; -+static const int mt7623_i2c2_0_pins[] = { 77, 78, }; -+static const int mt7623_i2c2_0_funcs[] = { 1, 1, }; -+static const int mt7623_i2c2_1_pins[] = { 89, 90, }; -+static const int mt7623_i2c2_1_funcs[] = { 3, 3, }; -+static const int mt7623_i2c2_2_pins[] = { 109, 110, }; -+static const int mt7623_i2c2_2_funcs[] = { 3, 3, }; -+static const int mt7623_i2c2_3_pins[] = { 122, 123, }; -+static const int mt7623_i2c2_3_funcs[] = { 4, 4, }; - - /* I2S */ --static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; --static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; --static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; --static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; --static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; --static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; --static int mt7623_i2s2_data_in_pins[] = { 51, }; --static int mt7623_i2s2_data_in_funcs[] = { 1, }; --static int mt7623_i2s2_data_0_pins[] = { 203, }; --static int mt7623_i2s2_data_0_funcs[] = { 9, }; --static int mt7623_i2s2_data_1_pins[] = { 38, }; --static int mt7623_i2s2_data_1_funcs[] = { 4, }; --static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; --static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; --static int mt7623_i2s3_data_in_pins[] = { 190, }; --static int mt7623_i2s3_data_in_funcs[] = { 1, }; --static int mt7623_i2s3_data_0_pins[] = { 204, }; --static int mt7623_i2s3_data_0_funcs[] = { 9, }; --static int mt7623_i2s3_data_1_pins[] = { 2, }; --static int mt7623_i2s3_data_1_funcs[] = { 0, }; --static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; --static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; --static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; --static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; -+static const int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; -+static const int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; -+static const int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; -+static const int mt7623_i2s2_data_in_pins[] = { 51, }; -+static const int mt7623_i2s2_data_in_funcs[] = { 1, }; -+static const int mt7623_i2s2_data_0_pins[] = { 203, }; -+static const int mt7623_i2s2_data_0_funcs[] = { 9, }; -+static const int mt7623_i2s2_data_1_pins[] = { 38, }; -+static const int mt7623_i2s2_data_1_funcs[] = { 4, }; -+static const int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; -+static const int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; -+static const int mt7623_i2s3_data_in_pins[] = { 190, }; -+static const int mt7623_i2s3_data_in_funcs[] = { 1, }; -+static const int mt7623_i2s3_data_0_pins[] = { 204, }; -+static const int mt7623_i2s3_data_0_funcs[] = { 9, }; -+static const int mt7623_i2s3_data_1_pins[] = { 2, }; -+static const int mt7623_i2s3_data_1_funcs[] = { 0, }; -+static const int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; -+static const int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; -+static const int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; - - /* IR */ --static int mt7623_ir_pins[] = { 46, }; --static int mt7623_ir_funcs[] = { 1, }; -+static const int mt7623_ir_pins[] = { 46, }; -+static const int mt7623_ir_funcs[] = { 1, }; - - /* LCD */ --static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, -- 99, 100, }; --static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; --static int mt7623_dsi_te_pins[] = { 84, }; --static int mt7623_dsi_te_funcs[] = { 1, }; --static int mt7623_lcm_rst_pins[] = { 83, }; --static int mt7623_lcm_rst_funcs[] = { 1, }; -+static const int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, -+ 99, 100, }; -+static const int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_dsi_te_pins[] = { 84, }; -+static const int mt7623_dsi_te_funcs[] = { 1, }; -+static const int mt7623_lcm_rst_pins[] = { 83, }; -+static const int mt7623_lcm_rst_funcs[] = { 1, }; - - /* MDC/MDIO */ --static int mt7623_mdc_mdio_pins[] = { 275, 276, }; --static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; -+static const int mt7623_mdc_mdio_pins[] = { 275, 276, }; -+static const int mt7623_mdc_mdio_funcs[] = { 1, 1, }; - - /* MSDC */ --static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, -- 119, 120, 121, }; --static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; --static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; --static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; --static int mt7623_msdc1_ins_pins[] = { 261, }; --static int mt7623_msdc1_ins_funcs[] = { 1, }; --static int mt7623_msdc1_wp_0_pins[] = { 29, }; --static int mt7623_msdc1_wp_0_funcs[] = { 1, }; --static int mt7623_msdc1_wp_1_pins[] = { 55, }; --static int mt7623_msdc1_wp_1_funcs[] = { 3, }; --static int mt7623_msdc1_wp_2_pins[] = { 209, }; --static int mt7623_msdc1_wp_2_funcs[] = { 2, }; --static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; --static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; --static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, -- 257, 258, 259, 260, }; --static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, -+ 119, 120, 121, }; -+static const int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; -+static const int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_msdc1_ins_pins[] = { 261, }; -+static const int mt7623_msdc1_ins_funcs[] = { 1, }; -+static const int mt7623_msdc1_wp_0_pins[] = { 29, }; -+static const int mt7623_msdc1_wp_0_funcs[] = { 1, }; -+static const int mt7623_msdc1_wp_1_pins[] = { 55, }; -+static const int mt7623_msdc1_wp_1_funcs[] = { 3, }; -+static const int mt7623_msdc1_wp_2_pins[] = { 209, }; -+static const int mt7623_msdc1_wp_2_funcs[] = { 2, }; -+static const int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; -+static const int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, -+ 257, 258, 259, 260, }; -+static const int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - /* NAND */ --static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, -- 116, 117, 118, 119, 120, 121, }; --static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, -- 4, 4, }; --static int mt7623_nandc_ceb0_pins[] = { 45, }; --static int mt7623_nandc_ceb0_funcs[] = { 1, }; --static int mt7623_nandc_ceb1_pins[] = { 44, }; --static int mt7623_nandc_ceb1_funcs[] = { 1, }; -+static const int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, -+ 116, 117, 118, 119, 120, 121, }; -+static const int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, -+ 4, 4, }; -+static const int mt7623_nandc_ceb0_pins[] = { 45, }; -+static const int mt7623_nandc_ceb0_funcs[] = { 1, }; -+static const int mt7623_nandc_ceb1_pins[] = { 44, }; -+static const int mt7623_nandc_ceb1_funcs[] = { 1, }; - - /* RTC */ --static int mt7623_rtc_pins[] = { 10, }; --static int mt7623_rtc_funcs[] = { 1, }; -+static const int mt7623_rtc_pins[] = { 10, }; -+static const int mt7623_rtc_funcs[] = { 1, }; - - /* OTG */ --static int mt7623_otg_iddig0_0_pins[] = { 29, }; --static int mt7623_otg_iddig0_0_funcs[] = { 1, }; --static int mt7623_otg_iddig0_1_pins[] = { 44, }; --static int mt7623_otg_iddig0_1_funcs[] = { 2, }; --static int mt7623_otg_iddig0_2_pins[] = { 236, }; --static int mt7623_otg_iddig0_2_funcs[] = { 2, }; --static int mt7623_otg_iddig1_0_pins[] = { 27, }; --static int mt7623_otg_iddig1_0_funcs[] = { 2, }; --static int mt7623_otg_iddig1_1_pins[] = { 47, }; --static int mt7623_otg_iddig1_1_funcs[] = { 2, }; --static int mt7623_otg_iddig1_2_pins[] = { 238, }; --static int mt7623_otg_iddig1_2_funcs[] = { 2, }; --static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; --static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; --static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; --static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; --static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; --static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; --static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; --static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; --static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; --static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; --static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; --static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; -+static const int mt7623_otg_iddig0_0_pins[] = { 29, }; -+static const int mt7623_otg_iddig0_0_funcs[] = { 1, }; -+static const int mt7623_otg_iddig0_1_pins[] = { 44, }; -+static const int mt7623_otg_iddig0_1_funcs[] = { 2, }; -+static const int mt7623_otg_iddig0_2_pins[] = { 236, }; -+static const int mt7623_otg_iddig0_2_funcs[] = { 2, }; -+static const int mt7623_otg_iddig1_0_pins[] = { 27, }; -+static const int mt7623_otg_iddig1_0_funcs[] = { 2, }; -+static const int mt7623_otg_iddig1_1_pins[] = { 47, }; -+static const int mt7623_otg_iddig1_1_funcs[] = { 2, }; -+static const int mt7623_otg_iddig1_2_pins[] = { 238, }; -+static const int mt7623_otg_iddig1_2_funcs[] = { 2, }; -+static const int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; -+static const int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; -+static const int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; -+static const int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; -+static const int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; -+static const int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; -+static const int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; -+static const int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; -+static const int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; -+static const int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; -+static const int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; -+static const int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; - - /* PCIE */ --static int mt7623_pcie0_0_perst_pins[] = { 208, }; --static int mt7623_pcie0_0_perst_funcs[] = { 3, }; --static int mt7623_pcie0_1_perst_pins[] = { 22, }; --static int mt7623_pcie0_1_perst_funcs[] = { 2, }; --static int mt7623_pcie1_0_perst_pins[] = { 209, }; --static int mt7623_pcie1_0_perst_funcs[] = { 3, }; --static int mt7623_pcie1_1_perst_pins[] = { 23, }; --static int mt7623_pcie1_1_perst_funcs[] = { 2, }; --static int mt7623_pcie2_0_perst_pins[] = { 24, }; --static int mt7623_pcie2_0_perst_funcs[] = { 2, }; --static int mt7623_pcie2_1_perst_pins[] = { 29, }; --static int mt7623_pcie2_1_perst_funcs[] = { 6, }; --static int mt7623_pcie0_0_wake_pins[] = { 28, }; --static int mt7623_pcie0_0_wake_funcs[] = { 6, }; --static int mt7623_pcie0_1_wake_pins[] = { 251, }; --static int mt7623_pcie0_1_wake_funcs[] = { 6, }; --static int mt7623_pcie1_0_wake_pins[] = { 27, }; --static int mt7623_pcie1_0_wake_funcs[] = { 6, }; --static int mt7623_pcie1_1_wake_pins[] = { 253, }; --static int mt7623_pcie1_1_wake_funcs[] = { 6, }; --static int mt7623_pcie2_0_wake_pins[] = { 26, }; --static int mt7623_pcie2_0_wake_funcs[] = { 6, }; --static int mt7623_pcie2_1_wake_pins[] = { 255, }; --static int mt7623_pcie2_1_wake_funcs[] = { 6, }; --static int mt7623_pcie0_clkreq_pins[] = { 250, }; --static int mt7623_pcie0_clkreq_funcs[] = { 6, }; --static int mt7623_pcie1_clkreq_pins[] = { 252, }; --static int mt7623_pcie1_clkreq_funcs[] = { 6, }; --static int mt7623_pcie2_clkreq_pins[] = { 254, }; --static int mt7623_pcie2_clkreq_funcs[] = { 6, }; -+static const int mt7623_pcie0_0_perst_pins[] = { 208, }; -+static const int mt7623_pcie0_0_perst_funcs[] = { 3, }; -+static const int mt7623_pcie0_1_perst_pins[] = { 22, }; -+static const int mt7623_pcie0_1_perst_funcs[] = { 2, }; -+static const int mt7623_pcie1_0_perst_pins[] = { 209, }; -+static const int mt7623_pcie1_0_perst_funcs[] = { 3, }; -+static const int mt7623_pcie1_1_perst_pins[] = { 23, }; -+static const int mt7623_pcie1_1_perst_funcs[] = { 2, }; -+static const int mt7623_pcie2_0_perst_pins[] = { 24, }; -+static const int mt7623_pcie2_0_perst_funcs[] = { 2, }; -+static const int mt7623_pcie2_1_perst_pins[] = { 29, }; -+static const int mt7623_pcie2_1_perst_funcs[] = { 6, }; -+static const int mt7623_pcie0_0_wake_pins[] = { 28, }; -+static const int mt7623_pcie0_0_wake_funcs[] = { 6, }; -+static const int mt7623_pcie0_1_wake_pins[] = { 251, }; -+static const int mt7623_pcie0_1_wake_funcs[] = { 6, }; -+static const int mt7623_pcie1_0_wake_pins[] = { 27, }; -+static const int mt7623_pcie1_0_wake_funcs[] = { 6, }; -+static const int mt7623_pcie1_1_wake_pins[] = { 253, }; -+static const int mt7623_pcie1_1_wake_funcs[] = { 6, }; -+static const int mt7623_pcie2_0_wake_pins[] = { 26, }; -+static const int mt7623_pcie2_0_wake_funcs[] = { 6, }; -+static const int mt7623_pcie2_1_wake_pins[] = { 255, }; -+static const int mt7623_pcie2_1_wake_funcs[] = { 6, }; -+static const int mt7623_pcie0_clkreq_pins[] = { 250, }; -+static const int mt7623_pcie0_clkreq_funcs[] = { 6, }; -+static const int mt7623_pcie1_clkreq_pins[] = { 252, }; -+static const int mt7623_pcie1_clkreq_funcs[] = { 6, }; -+static const int mt7623_pcie2_clkreq_pins[] = { 254, }; -+static const int mt7623_pcie2_clkreq_funcs[] = { 6, }; - /* the pcie_*_rev are only used for MT7623 */ --static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; --static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; --static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; --static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; --static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; --static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; --static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; --static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; --static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; --static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; --static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; --static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; -+static const int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; -+static const int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; -+static const int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; -+static const int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; -+static const int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; -+static const int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; -+static const int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; -+static const int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; -+static const int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; -+static const int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; -+static const int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; -+static const int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; - - /* PCM */ --static int mt7623_pcm_clk_0_pins[] = { 18, }; --static int mt7623_pcm_clk_0_funcs[] = { 1, }; --static int mt7623_pcm_clk_1_pins[] = { 17, }; --static int mt7623_pcm_clk_1_funcs[] = { 3, }; --static int mt7623_pcm_clk_2_pins[] = { 35, }; --static int mt7623_pcm_clk_2_funcs[] = { 3, }; --static int mt7623_pcm_clk_3_pins[] = { 50, }; --static int mt7623_pcm_clk_3_funcs[] = { 3, }; --static int mt7623_pcm_clk_4_pins[] = { 74, }; --static int mt7623_pcm_clk_4_funcs[] = { 3, }; --static int mt7623_pcm_clk_5_pins[] = { 191, }; --static int mt7623_pcm_clk_5_funcs[] = { 3, }; --static int mt7623_pcm_clk_6_pins[] = { 196, }; --static int mt7623_pcm_clk_6_funcs[] = { 3, }; --static int mt7623_pcm_sync_0_pins[] = { 19, }; --static int mt7623_pcm_sync_0_funcs[] = { 1, }; --static int mt7623_pcm_sync_1_pins[] = { 30, }; --static int mt7623_pcm_sync_1_funcs[] = { 3, }; --static int mt7623_pcm_sync_2_pins[] = { 36, }; --static int mt7623_pcm_sync_2_funcs[] = { 3, }; --static int mt7623_pcm_sync_3_pins[] = { 52, }; --static int mt7623_pcm_sync_3_funcs[] = { 31, }; --static int mt7623_pcm_sync_4_pins[] = { 73, }; --static int mt7623_pcm_sync_4_funcs[] = { 3, }; --static int mt7623_pcm_sync_5_pins[] = { 192, }; --static int mt7623_pcm_sync_5_funcs[] = { 3, }; --static int mt7623_pcm_sync_6_pins[] = { 197, }; --static int mt7623_pcm_sync_6_funcs[] = { 3, }; --static int mt7623_pcm_rx_0_pins[] = { 20, }; --static int mt7623_pcm_rx_0_funcs[] = { 1, }; --static int mt7623_pcm_rx_1_pins[] = { 16, }; --static int mt7623_pcm_rx_1_funcs[] = { 3, }; --static int mt7623_pcm_rx_2_pins[] = { 34, }; --static int mt7623_pcm_rx_2_funcs[] = { 3, }; --static int mt7623_pcm_rx_3_pins[] = { 51, }; --static int mt7623_pcm_rx_3_funcs[] = { 3, }; --static int mt7623_pcm_rx_4_pins[] = { 72, }; --static int mt7623_pcm_rx_4_funcs[] = { 3, }; --static int mt7623_pcm_rx_5_pins[] = { 190, }; --static int mt7623_pcm_rx_5_funcs[] = { 3, }; --static int mt7623_pcm_rx_6_pins[] = { 195, }; --static int mt7623_pcm_rx_6_funcs[] = { 3, }; --static int mt7623_pcm_tx_0_pins[] = { 21, }; --static int mt7623_pcm_tx_0_funcs[] = { 1, }; --static int mt7623_pcm_tx_1_pins[] = { 32, }; --static int mt7623_pcm_tx_1_funcs[] = { 3, }; --static int mt7623_pcm_tx_2_pins[] = { 33, }; --static int mt7623_pcm_tx_2_funcs[] = { 3, }; --static int mt7623_pcm_tx_3_pins[] = { 38, }; --static int mt7623_pcm_tx_3_funcs[] = { 3, }; --static int mt7623_pcm_tx_4_pins[] = { 49, }; --static int mt7623_pcm_tx_4_funcs[] = { 3, }; --static int mt7623_pcm_tx_5_pins[] = { 189, }; --static int mt7623_pcm_tx_5_funcs[] = { 3, }; --static int mt7623_pcm_tx_6_pins[] = { 194, }; --static int mt7623_pcm_tx_6_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_0_pins[] = { 18, }; -+static const int mt7623_pcm_clk_0_funcs[] = { 1, }; -+static const int mt7623_pcm_clk_1_pins[] = { 17, }; -+static const int mt7623_pcm_clk_1_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_2_pins[] = { 35, }; -+static const int mt7623_pcm_clk_2_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_3_pins[] = { 50, }; -+static const int mt7623_pcm_clk_3_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_4_pins[] = { 74, }; -+static const int mt7623_pcm_clk_4_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_5_pins[] = { 191, }; -+static const int mt7623_pcm_clk_5_funcs[] = { 3, }; -+static const int mt7623_pcm_clk_6_pins[] = { 196, }; -+static const int mt7623_pcm_clk_6_funcs[] = { 3, }; -+static const int mt7623_pcm_sync_0_pins[] = { 19, }; -+static const int mt7623_pcm_sync_0_funcs[] = { 1, }; -+static const int mt7623_pcm_sync_1_pins[] = { 30, }; -+static const int mt7623_pcm_sync_1_funcs[] = { 3, }; -+static const int mt7623_pcm_sync_2_pins[] = { 36, }; -+static const int mt7623_pcm_sync_2_funcs[] = { 3, }; -+static const int mt7623_pcm_sync_3_pins[] = { 52, }; -+static const int mt7623_pcm_sync_3_funcs[] = { 31, }; -+static const int mt7623_pcm_sync_4_pins[] = { 73, }; -+static const int mt7623_pcm_sync_4_funcs[] = { 3, }; -+static const int mt7623_pcm_sync_5_pins[] = { 192, }; -+static const int mt7623_pcm_sync_5_funcs[] = { 3, }; -+static const int mt7623_pcm_sync_6_pins[] = { 197, }; -+static const int mt7623_pcm_sync_6_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_0_pins[] = { 20, }; -+static const int mt7623_pcm_rx_0_funcs[] = { 1, }; -+static const int mt7623_pcm_rx_1_pins[] = { 16, }; -+static const int mt7623_pcm_rx_1_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_2_pins[] = { 34, }; -+static const int mt7623_pcm_rx_2_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_3_pins[] = { 51, }; -+static const int mt7623_pcm_rx_3_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_4_pins[] = { 72, }; -+static const int mt7623_pcm_rx_4_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_5_pins[] = { 190, }; -+static const int mt7623_pcm_rx_5_funcs[] = { 3, }; -+static const int mt7623_pcm_rx_6_pins[] = { 195, }; -+static const int mt7623_pcm_rx_6_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_0_pins[] = { 21, }; -+static const int mt7623_pcm_tx_0_funcs[] = { 1, }; -+static const int mt7623_pcm_tx_1_pins[] = { 32, }; -+static const int mt7623_pcm_tx_1_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_2_pins[] = { 33, }; -+static const int mt7623_pcm_tx_2_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_3_pins[] = { 38, }; -+static const int mt7623_pcm_tx_3_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_4_pins[] = { 49, }; -+static const int mt7623_pcm_tx_4_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_5_pins[] = { 189, }; -+static const int mt7623_pcm_tx_5_funcs[] = { 3, }; -+static const int mt7623_pcm_tx_6_pins[] = { 194, }; -+static const int mt7623_pcm_tx_6_funcs[] = { 3, }; - - /* PWM */ --static int mt7623_pwm_ch1_0_pins[] = { 203, }; --static int mt7623_pwm_ch1_0_funcs[] = { 1, }; --static int mt7623_pwm_ch1_1_pins[] = { 208, }; --static int mt7623_pwm_ch1_1_funcs[] = { 2, }; --static int mt7623_pwm_ch1_2_pins[] = { 72, }; --static int mt7623_pwm_ch1_2_funcs[] = { 4, }; --static int mt7623_pwm_ch1_3_pins[] = { 88, }; --static int mt7623_pwm_ch1_3_funcs[] = { 3, }; --static int mt7623_pwm_ch1_4_pins[] = { 108, }; --static int mt7623_pwm_ch1_4_funcs[] = { 3, }; --static int mt7623_pwm_ch2_0_pins[] = { 204, }; --static int mt7623_pwm_ch2_0_funcs[] = { 1, }; --static int mt7623_pwm_ch2_1_pins[] = { 53, }; --static int mt7623_pwm_ch2_1_funcs[] = { 5, }; --static int mt7623_pwm_ch2_2_pins[] = { 88, }; --static int mt7623_pwm_ch2_2_funcs[] = { 6, }; --static int mt7623_pwm_ch2_3_pins[] = { 108, }; --static int mt7623_pwm_ch2_3_funcs[] = { 6, }; --static int mt7623_pwm_ch2_4_pins[] = { 209, }; --static int mt7623_pwm_ch2_4_funcs[] = { 5, }; --static int mt7623_pwm_ch3_0_pins[] = { 205, }; --static int mt7623_pwm_ch3_0_funcs[] = { 1, }; --static int mt7623_pwm_ch3_1_pins[] = { 55, }; --static int mt7623_pwm_ch3_1_funcs[] = { 5, }; --static int mt7623_pwm_ch3_2_pins[] = { 89, }; --static int mt7623_pwm_ch3_2_funcs[] = { 6, }; --static int mt7623_pwm_ch3_3_pins[] = { 109, }; --static int mt7623_pwm_ch3_3_funcs[] = { 6, }; --static int mt7623_pwm_ch4_0_pins[] = { 206, }; --static int mt7623_pwm_ch4_0_funcs[] = { 1, }; --static int mt7623_pwm_ch4_1_pins[] = { 90, }; --static int mt7623_pwm_ch4_1_funcs[] = { 6, }; --static int mt7623_pwm_ch4_2_pins[] = { 110, }; --static int mt7623_pwm_ch4_2_funcs[] = { 6, }; --static int mt7623_pwm_ch4_3_pins[] = { 124, }; --static int mt7623_pwm_ch4_3_funcs[] = { 5, }; --static int mt7623_pwm_ch5_0_pins[] = { 207, }; --static int mt7623_pwm_ch5_0_funcs[] = { 1, }; --static int mt7623_pwm_ch5_1_pins[] = { 125, }; --static int mt7623_pwm_ch5_1_funcs[] = { 5, }; -+static const int mt7623_pwm_ch1_0_pins[] = { 203, }; -+static const int mt7623_pwm_ch1_0_funcs[] = { 1, }; -+static const int mt7623_pwm_ch1_1_pins[] = { 208, }; -+static const int mt7623_pwm_ch1_1_funcs[] = { 2, }; -+static const int mt7623_pwm_ch1_2_pins[] = { 72, }; -+static const int mt7623_pwm_ch1_2_funcs[] = { 4, }; -+static const int mt7623_pwm_ch1_3_pins[] = { 88, }; -+static const int mt7623_pwm_ch1_3_funcs[] = { 3, }; -+static const int mt7623_pwm_ch1_4_pins[] = { 108, }; -+static const int mt7623_pwm_ch1_4_funcs[] = { 3, }; -+static const int mt7623_pwm_ch2_0_pins[] = { 204, }; -+static const int mt7623_pwm_ch2_0_funcs[] = { 1, }; -+static const int mt7623_pwm_ch2_1_pins[] = { 53, }; -+static const int mt7623_pwm_ch2_1_funcs[] = { 5, }; -+static const int mt7623_pwm_ch2_2_pins[] = { 88, }; -+static const int mt7623_pwm_ch2_2_funcs[] = { 6, }; -+static const int mt7623_pwm_ch2_3_pins[] = { 108, }; -+static const int mt7623_pwm_ch2_3_funcs[] = { 6, }; -+static const int mt7623_pwm_ch2_4_pins[] = { 209, }; -+static const int mt7623_pwm_ch2_4_funcs[] = { 5, }; -+static const int mt7623_pwm_ch3_0_pins[] = { 205, }; -+static const int mt7623_pwm_ch3_0_funcs[] = { 1, }; -+static const int mt7623_pwm_ch3_1_pins[] = { 55, }; -+static const int mt7623_pwm_ch3_1_funcs[] = { 5, }; -+static const int mt7623_pwm_ch3_2_pins[] = { 89, }; -+static const int mt7623_pwm_ch3_2_funcs[] = { 6, }; -+static const int mt7623_pwm_ch3_3_pins[] = { 109, }; -+static const int mt7623_pwm_ch3_3_funcs[] = { 6, }; -+static const int mt7623_pwm_ch4_0_pins[] = { 206, }; -+static const int mt7623_pwm_ch4_0_funcs[] = { 1, }; -+static const int mt7623_pwm_ch4_1_pins[] = { 90, }; -+static const int mt7623_pwm_ch4_1_funcs[] = { 6, }; -+static const int mt7623_pwm_ch4_2_pins[] = { 110, }; -+static const int mt7623_pwm_ch4_2_funcs[] = { 6, }; -+static const int mt7623_pwm_ch4_3_pins[] = { 124, }; -+static const int mt7623_pwm_ch4_3_funcs[] = { 5, }; -+static const int mt7623_pwm_ch5_0_pins[] = { 207, }; -+static const int mt7623_pwm_ch5_0_funcs[] = { 1, }; -+static const int mt7623_pwm_ch5_1_pins[] = { 125, }; -+static const int mt7623_pwm_ch5_1_funcs[] = { 5, }; - - /* PWRAP */ --static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; --static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; -+static const int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; - - /* SPDIF */ --static int mt7623_spdif_in0_0_pins[] = { 56, }; --static int mt7623_spdif_in0_0_funcs[] = { 3, }; --static int mt7623_spdif_in0_1_pins[] = { 201, }; --static int mt7623_spdif_in0_1_funcs[] = { 1, }; --static int mt7623_spdif_in1_0_pins[] = { 54, }; --static int mt7623_spdif_in1_0_funcs[] = { 3, }; --static int mt7623_spdif_in1_1_pins[] = { 202, }; --static int mt7623_spdif_in1_1_funcs[] = { 1, }; --static int mt7623_spdif_out_pins[] = { 202, }; --static int mt7623_spdif_out_funcs[] = { 1, }; -+static const int mt7623_spdif_in0_0_pins[] = { 56, }; -+static const int mt7623_spdif_in0_0_funcs[] = { 3, }; -+static const int mt7623_spdif_in0_1_pins[] = { 201, }; -+static const int mt7623_spdif_in0_1_funcs[] = { 1, }; -+static const int mt7623_spdif_in1_0_pins[] = { 54, }; -+static const int mt7623_spdif_in1_0_funcs[] = { 3, }; -+static const int mt7623_spdif_in1_1_pins[] = { 202, }; -+static const int mt7623_spdif_in1_1_funcs[] = { 1, }; -+static const int mt7623_spdif_out_pins[] = { 202, }; -+static const int mt7623_spdif_out_funcs[] = { 1, }; - - /* SPI */ --static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; --static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; --static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; --static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; --static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; --static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; -+static const int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; -+static const int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; -+static const int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; - - /* UART */ --static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; --static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; --static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; --static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; --static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; --static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; --static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; --static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; --static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; --static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; --static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; --static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; --static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; --static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; --static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; --static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; --static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; --static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; --static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; --static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; --static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; --static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; --static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; --static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; --static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; --static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; --static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; --static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; -+static const int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; -+static const int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; -+static const int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; -+static const int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; -+static const int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; -+static const int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; -+static const int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; -+static const int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; -+static const int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; -+static const int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; -+static const int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; -+static const int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; -+static const int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; -+static const int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; -+static const int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; -+static const int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; -+static const int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; -+static const int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; -+static const int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; -+static const int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; -+static const int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; -+static const int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; -+static const int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; -+static const int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; -+static const int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; - - /* Watchdog */ --static int mt7623_watchdog_0_pins[] = { 11, }; --static int mt7623_watchdog_0_funcs[] = { 1, }; --static int mt7623_watchdog_1_pins[] = { 121, }; --static int mt7623_watchdog_1_funcs[] = { 5, }; -+static const int mt7623_watchdog_0_pins[] = { 11, }; -+static const int mt7623_watchdog_0_funcs[] = { 1, }; -+static const int mt7623_watchdog_1_pins[] = { 121, }; -+static const int mt7623_watchdog_1_funcs[] = { 5, }; - - static const struct mtk_group_desc mt7623_groups[] = { - PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), -@@ -1362,7 +1362,7 @@ static const struct mtk_function_desc mt - {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, - }; - --static struct mtk_pinctrl_soc mt7623_data = { -+static const struct mtk_pinctrl_soc mt7623_data = { - .name = "mt7623_pinctrl", - .reg_cal = mt7623_reg_cals, - .pins = mt7623_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c -@@ -180,118 +180,118 @@ static const struct mtk_pin_desc mt7629_ - */ - - /* WF 5G */ --static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; --static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; -+static const int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - /* LED for EPHY */ --static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; --static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; --static int mt7629_ephy_led0_pins[] = { 12, }; --static int mt7629_ephy_led0_funcs[] = { 1, }; --static int mt7629_ephy_led1_pins[] = { 13, }; --static int mt7629_ephy_led1_funcs[] = { 1, }; --static int mt7629_ephy_led2_pins[] = { 14, }; --static int mt7629_ephy_led2_funcs[] = { 1, }; --static int mt7629_ephy_led3_pins[] = { 15, }; --static int mt7629_ephy_led3_funcs[] = { 1, }; --static int mt7629_ephy_led4_pins[] = { 16, }; --static int mt7629_ephy_led4_funcs[] = { 1, }; --static int mt7629_wf2g_led_pins[] = { 17, }; --static int mt7629_wf2g_led_funcs[] = { 1, }; --static int mt7629_wf5g_led_pins[] = { 18, }; --static int mt7629_wf5g_led_funcs[] = { 1, }; -+static const int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; -+static const int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7629_ephy_led0_pins[] = { 12, }; -+static const int mt7629_ephy_led0_funcs[] = { 1, }; -+static const int mt7629_ephy_led1_pins[] = { 13, }; -+static const int mt7629_ephy_led1_funcs[] = { 1, }; -+static const int mt7629_ephy_led2_pins[] = { 14, }; -+static const int mt7629_ephy_led2_funcs[] = { 1, }; -+static const int mt7629_ephy_led3_pins[] = { 15, }; -+static const int mt7629_ephy_led3_funcs[] = { 1, }; -+static const int mt7629_ephy_led4_pins[] = { 16, }; -+static const int mt7629_ephy_led4_funcs[] = { 1, }; -+static const int mt7629_wf2g_led_pins[] = { 17, }; -+static const int mt7629_wf2g_led_funcs[] = { 1, }; -+static const int mt7629_wf5g_led_pins[] = { 18, }; -+static const int mt7629_wf5g_led_funcs[] = { 1, }; - - /* LED for EPHY used as JTAG */ --static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; --static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; -+static const int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; -+static const int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; - - /* Watchdog */ --static int mt7629_watchdog_pins[] = { 11, }; --static int mt7629_watchdog_funcs[] = { 1, }; -+static const int mt7629_watchdog_pins[] = { 11, }; -+static const int mt7629_watchdog_funcs[] = { 1, }; - - /* LED for GPHY */ --static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; --static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; --static int mt7629_gphy_led1_0_pins[] = { 21, }; --static int mt7629_gphy_led1_0_funcs[] = { 2, }; --static int mt7629_gphy_led2_0_pins[] = { 22, }; --static int mt7629_gphy_led2_0_funcs[] = { 2, }; --static int mt7629_gphy_led3_0_pins[] = { 23, }; --static int mt7629_gphy_led3_0_funcs[] = { 2, }; --static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; --static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; --static int mt7629_gphy_led1_1_pins[] = { 57, }; --static int mt7629_gphy_led1_1_funcs[] = { 1, }; --static int mt7629_gphy_led2_1_pins[] = { 58, }; --static int mt7629_gphy_led2_1_funcs[] = { 1, }; --static int mt7629_gphy_led3_1_pins[] = { 59, }; --static int mt7629_gphy_led3_1_funcs[] = { 1, }; -+static const int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; -+static const int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; -+static const int mt7629_gphy_led1_0_pins[] = { 21, }; -+static const int mt7629_gphy_led1_0_funcs[] = { 2, }; -+static const int mt7629_gphy_led2_0_pins[] = { 22, }; -+static const int mt7629_gphy_led2_0_funcs[] = { 2, }; -+static const int mt7629_gphy_led3_0_pins[] = { 23, }; -+static const int mt7629_gphy_led3_0_funcs[] = { 2, }; -+static const int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; -+static const int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; -+static const int mt7629_gphy_led1_1_pins[] = { 57, }; -+static const int mt7629_gphy_led1_1_funcs[] = { 1, }; -+static const int mt7629_gphy_led2_1_pins[] = { 58, }; -+static const int mt7629_gphy_led2_1_funcs[] = { 1, }; -+static const int mt7629_gphy_led3_1_pins[] = { 59, }; -+static const int mt7629_gphy_led3_1_funcs[] = { 1, }; - - /* I2C */ --static int mt7629_i2c_0_pins[] = { 19, 20, }; --static int mt7629_i2c_0_funcs[] = { 1, 1, }; --static int mt7629_i2c_1_pins[] = { 53, 54, }; --static int mt7629_i2c_1_funcs[] = { 1, 1, }; -+static const int mt7629_i2c_0_pins[] = { 19, 20, }; -+static const int mt7629_i2c_0_funcs[] = { 1, 1, }; -+static const int mt7629_i2c_1_pins[] = { 53, 54, }; -+static const int mt7629_i2c_1_funcs[] = { 1, 1, }; - - /* SPI */ --static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; --static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; --static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; --static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; --static int mt7629_spi_wp_pins[] = { 66, }; --static int mt7629_spi_wp_funcs[] = { 1, }; --static int mt7629_spi_hold_pins[] = { 67, }; --static int mt7629_spi_hold_funcs[] = { 1, }; -+static const int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; -+static const int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; -+static const int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7629_spi_wp_pins[] = { 66, }; -+static const int mt7629_spi_wp_funcs[] = { 1, }; -+static const int mt7629_spi_hold_pins[] = { 67, }; -+static const int mt7629_spi_hold_funcs[] = { 1, }; - - /* UART */ --static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; --static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; --static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; --static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; --static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; --static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; --static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; --static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; --static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; --static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; --static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; --static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; --static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; --static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; --static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; --static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; --static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; --static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; -+static const int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; -+static const int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; -+static const int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; -+static const int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; -+static const int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; -+static const int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; -+static const int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; -+static const int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; -+static const int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; -+static const int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; -+static const int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; -+static const int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; -+static const int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; -+static const int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; -+static const int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; -+static const int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; - - /* MDC/MDIO */ --static int mt7629_mdc_mdio_pins[] = { 49, 50, }; --static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; -+static const int mt7629_mdc_mdio_pins[] = { 49, 50, }; -+static const int mt7629_mdc_mdio_funcs[] = { 1, 1, }; - - /* PCIE */ --static int mt7629_pcie_pereset_pins[] = { 51, }; --static int mt7629_pcie_pereset_funcs[] = { 1, }; --static int mt7629_pcie_wake_pins[] = { 55, }; --static int mt7629_pcie_wake_funcs[] = { 1, }; --static int mt7629_pcie_clkreq_pins[] = { 56, }; --static int mt7629_pcie_clkreq_funcs[] = { 1, }; -+static const int mt7629_pcie_pereset_pins[] = { 51, }; -+static const int mt7629_pcie_pereset_funcs[] = { 1, }; -+static const int mt7629_pcie_wake_pins[] = { 55, }; -+static const int mt7629_pcie_wake_funcs[] = { 1, }; -+static const int mt7629_pcie_clkreq_pins[] = { 56, }; -+static const int mt7629_pcie_clkreq_funcs[] = { 1, }; - - /* PWM */ --static int mt7629_pwm_0_pins[] = { 52, }; --static int mt7629_pwm_0_funcs[] = { 1, }; --static int mt7629_pwm_1_pins[] = { 61, }; --static int mt7629_pwm_1_funcs[] = { 2, }; -+static const int mt7629_pwm_0_pins[] = { 52, }; -+static const int mt7629_pwm_0_funcs[] = { 1, }; -+static const int mt7629_pwm_1_pins[] = { 61, }; -+static const int mt7629_pwm_1_funcs[] = { 2, }; - - /* WF 2G */ --static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; --static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; -+static const int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; - - /* SNFI */ --static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; --static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+static const int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; -+static const int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - - /* SPI NOR */ --static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; --static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; -+static const int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; -+static const int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; - - static const struct mtk_group_desc mt7629_groups[] = { - PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), -@@ -385,7 +385,7 @@ static const struct mtk_function_desc mt - {"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)}, - }; - --static struct mtk_pinctrl_soc mt7629_data = { -+static const struct mtk_pinctrl_soc mt7629_data = { - .name = "mt7629_pinctrl", - .reg_cal = mt7629_reg_cals, - .pins = mt7629_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -570,242 +570,246 @@ static const struct mtk_pin_desc mt7981_ - }; - - /* WA_AICE */ --static int mt7981_wa_aice1_pins[] = { 0, 1, }; --static int mt7981_wa_aice1_funcs[] = { 2, 2, }; -+static const int mt7981_wa_aice1_pins[] = { 0, 1, }; -+static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; - --static int mt7981_wa_aice2_pins[] = { 0, 1, }; --static int mt7981_wa_aice2_funcs[] = { 3, 3, }; -+static const int mt7981_wa_aice2_pins[] = { 0, 1, }; -+static const int mt7981_wa_aice2_funcs[] = { 3, 3, }; - --static int mt7981_wa_aice3_pins[] = { 28, 29, }; --static int mt7981_wa_aice3_funcs[] = { 3, 3, }; -+static const int mt7981_wa_aice3_pins[] = { 28, 29, }; -+static const int mt7981_wa_aice3_funcs[] = { 3, 3, }; - --static int mt7981_wm_aice1_pins[] = { 9, 10, }; --static int mt7981_wm_aice1_funcs[] = { 2, 2, }; -+static const int mt7981_wm_aice1_pins[] = { 9, 10, }; -+static const int mt7981_wm_aice1_funcs[] = { 2, 2, }; - --static int mt7981_wm_aice2_pins[] = { 30, 31, }; --static int mt7981_wm_aice2_funcs[] = { 5, 5, }; -+static const int mt7981_wm_aice2_pins[] = { 30, 31, }; -+static const int mt7981_wm_aice2_funcs[] = { 5, 5, }; - - /* WM_UART */ --static int mt7981_wm_uart_0_pins[] = { 0, 1, }; --static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -+static const int mt7981_wm_uart_0_pins[] = { 0, 1, }; -+static const int mt7981_wm_uart_0_funcs[] = { 5, 5, }; - --static int mt7981_wm_uart_1_pins[] = { 20, 21, }; --static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -+static const int mt7981_wm_uart_1_pins[] = { 20, 21, }; -+static const int mt7981_wm_uart_1_funcs[] = { 4, 4, }; - --static int mt7981_wm_uart_2_pins[] = { 30, 31, }; --static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; -+static const int mt7981_wm_uart_2_pins[] = { 30, 31, }; -+static const int mt7981_wm_uart_2_funcs[] = { 3, 3, }; - - /* DFD */ --static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; --static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; -+static const int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -+static const int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; - - /* SYS_WATCHDOG */ --static int mt7981_watchdog_pins[] = { 2, }; --static int mt7981_watchdog_funcs[] = { 1, }; -+static const int mt7981_watchdog_pins[] = { 2, }; -+static const int mt7981_watchdog_funcs[] = { 1, }; - --static int mt7981_watchdog1_pins[] = { 13, }; --static int mt7981_watchdog1_funcs[] = { 5, }; -+static const int mt7981_watchdog1_pins[] = { 13, }; -+static const int mt7981_watchdog1_funcs[] = { 5, }; - - /* PCIE_PERESET_N */ --static int mt7981_pcie_pereset_pins[] = { 3, }; --static int mt7981_pcie_pereset_funcs[] = { 1, }; -+static const int mt7981_pcie_pereset_pins[] = { 3, }; -+static const int mt7981_pcie_pereset_funcs[] = { 1, }; - - /* JTAG */ --static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; --static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -+static const int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; - - /* WM_JTAG */ --static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; --static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -+static const int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -+static const int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; - --static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; --static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+static const int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -+static const int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - - /* WO0_JTAG */ --static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; --static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -+static const int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -+static const int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; - --static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; --static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+static const int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -+static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; - - /* UART2 */ --static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; --static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -+static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - - /* GBE_LED0 */ --static int mt7981_gbe_led0_pins[] = { 8, }; --static int mt7981_gbe_led0_funcs[] = { 3, }; -+static const int mt7981_gbe_led0_pins[] = { 8, }; -+static const int mt7981_gbe_led0_funcs[] = { 3, }; - - /* PTA_EXT */ --static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; --static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -+static const int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -+static const int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; - --static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; --static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; -+static const int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -+static const int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; - - /* PWM2 */ --static int mt7981_pwm2_pins[] = { 7, }; --static int mt7981_pwm2_funcs[] = { 4, }; -+static const int mt7981_pwm2_pins[] = { 7, }; -+static const int mt7981_pwm2_funcs[] = { 4, }; - - /* NET_WO0_UART_TXD */ --static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; --static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -+static const int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -+static const int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; - --static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; --static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -+static const int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -+static const int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; - --static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; --static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; -+static const int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -+static const int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; - - /* SPI1 */ --static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; --static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; -+static const int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -+static const int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; - - /* I2C */ --static int mt7981_i2c0_0_pins[] = { 6, 7, }; --static int mt7981_i2c0_0_funcs[] = { 6, 6, }; -+static const int mt7981_i2c0_0_pins[] = { 6, 7, }; -+static const int mt7981_i2c0_0_funcs[] = { 6, 6, }; - --static int mt7981_i2c0_1_pins[] = { 30, 31, }; --static int mt7981_i2c0_1_funcs[] = { 4, 4, }; -+static const int mt7981_i2c0_1_pins[] = { 30, 31, }; -+static const int mt7981_i2c0_1_funcs[] = { 4, 4, }; - --static int mt7981_i2c0_2_pins[] = { 36, 37, }; --static int mt7981_i2c0_2_funcs[] = { 2, 2, }; -+static const int mt7981_i2c0_2_pins[] = { 36, 37, }; -+static const int mt7981_i2c0_2_funcs[] = { 2, 2, }; - --static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; --static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -+static const int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -+static const int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; - --static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; --static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -+static const int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -+static const int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; - --static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; --static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -+static const int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -+static const int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; - --static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; --static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; -+static const int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -+static const int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; - - /* DFD_NTRST */ --static int mt7981_dfd_ntrst_pins[] = { 8, }; --static int mt7981_dfd_ntrst_funcs[] = { 6, }; -+static const int mt7981_dfd_ntrst_pins[] = { 8, }; -+static const int mt7981_dfd_ntrst_funcs[] = { 6, }; - - /* PWM0 */ --static int mt7981_pwm0_0_pins[] = { 13, }; --static int mt7981_pwm0_0_funcs[] = { 2, }; -+static const int mt7981_pwm0_0_pins[] = { 13, }; -+static const int mt7981_pwm0_0_funcs[] = { 2, }; - --static int mt7981_pwm0_1_pins[] = { 15, }; --static int mt7981_pwm0_1_funcs[] = { 1, }; -+static const int mt7981_pwm0_1_pins[] = { 15, }; -+static const int mt7981_pwm0_1_funcs[] = { 1, }; - - /* PWM1 */ --static int mt7981_pwm1_0_pins[] = { 14, }; --static int mt7981_pwm1_0_funcs[] = { 2, }; -+static const int mt7981_pwm1_0_pins[] = { 14, }; -+static const int mt7981_pwm1_0_funcs[] = { 2, }; - --static int mt7981_pwm1_1_pins[] = { 15, }; --static int mt7981_pwm1_1_funcs[] = { 3, }; -+static const int mt7981_pwm1_1_pins[] = { 15, }; -+static const int mt7981_pwm1_1_funcs[] = { 3, }; - - /* GBE_LED1 */ --static int mt7981_gbe_led1_pins[] = { 13, }; --static int mt7981_gbe_led1_funcs[] = { 3, }; -+static const int mt7981_gbe_led1_pins[] = { 13, }; -+static const int mt7981_gbe_led1_funcs[] = { 3, }; - - /* PCM */ --static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; --static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; -+static const int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -+static const int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; - - /* UDI */ --static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; --static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; -+static const int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -+static const int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; - - /* DRV_VBUS */ --static int mt7981_drv_vbus_pins[] = { 14, }; --static int mt7981_drv_vbus_funcs[] = { 1, }; -+static const int mt7981_drv_vbus_pins[] = { 14, }; -+static const int mt7981_drv_vbus_funcs[] = { 1, }; - - /* EMMC */ --static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; --static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+static const int mt7981_emmc_45_pins[] = { -+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static const int mt7981_emmc_45_funcs[] = { -+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - - /* SNFI */ --static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; --static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+static const int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static const int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; - - /* SPI0 */ --static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; --static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -+static const int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; - - /* SPI0 */ --static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; --static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; -+static const int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -+static const int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; - - /* SPI1 */ --static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; --static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -+static const int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; - - /* SPI2 */ --static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; --static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -+static const int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; - - /* SPI2 */ --static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; --static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; -+static const int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -+static const int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; - - /* UART1 */ --static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; --static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -+static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; - --static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; --static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; -+static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -+static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - - /* UART2 */ --static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; --static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -+static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; - - /* UART0 */ --static int mt7981_uart0_pins[] = { 32, 33, }; --static int mt7981_uart0_funcs[] = { 1, 1, }; -+static const int mt7981_uart0_pins[] = { 32, 33, }; -+static const int mt7981_uart0_funcs[] = { 1, 1, }; - - /* PCIE_CLK_REQ */ --static int mt7981_pcie_clk_pins[] = { 34, }; --static int mt7981_pcie_clk_funcs[] = { 2, }; -+static const int mt7981_pcie_clk_pins[] = { 34, }; -+static const int mt7981_pcie_clk_funcs[] = { 2, }; - - /* PCIE_WAKE_N */ --static int mt7981_pcie_wake_pins[] = { 35, }; --static int mt7981_pcie_wake_funcs[] = { 2, }; -+static const int mt7981_pcie_wake_pins[] = { 35, }; -+static const int mt7981_pcie_wake_funcs[] = { 2, }; - - /* MDC_MDIO */ --static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; --static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -+static const int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -+static const int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; - --static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; --static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; -+static const int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -+static const int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; - - /* WF0_MODE1 */ --static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, -- 50, 51, 52, 53, 54, 55, 56 }; --static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -- 1, 1, 1, 1 }; -+static const int mt7981_wf0_mode1_pins[] = { -+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -+static const int mt7981_wf0_mode1_funcs[] = { -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - - /* WF0_MODE3 */ --static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; --static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+static const int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -+static const int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; - - /* WF2G_LED */ --static int mt7981_wf2g_led0_pins[] = { 30, }; --static int mt7981_wf2g_led0_funcs[] = { 2, }; -+static const int mt7981_wf2g_led0_pins[] = { 30, }; -+static const int mt7981_wf2g_led0_funcs[] = { 2, }; - --static int mt7981_wf2g_led1_pins[] = { 34, }; --static int mt7981_wf2g_led1_funcs[] = { 1, }; -+static const int mt7981_wf2g_led1_pins[] = { 34, }; -+static const int mt7981_wf2g_led1_funcs[] = { 1, }; - - /* WF5G_LED */ --static int mt7981_wf5g_led0_pins[] = { 31, }; --static int mt7981_wf5g_led0_funcs[] = { 2, }; -+static const int mt7981_wf5g_led0_pins[] = { 31, }; -+static const int mt7981_wf5g_led0_funcs[] = { 2, }; - --static int mt7981_wf5g_led1_pins[] = { 35, }; --static int mt7981_wf5g_led1_funcs[] = { 1, }; -+static const int mt7981_wf5g_led1_pins[] = { 35, }; -+static const int mt7981_wf5g_led1_funcs[] = { 1, }; - - /* MT7531_INT */ --static int mt7981_mt7531_int_pins[] = { 38, }; --static int mt7981_mt7531_int_funcs[] = { 1, }; -+static const int mt7981_mt7531_int_pins[] = { 38, }; -+static const int mt7981_mt7531_int_funcs[] = { 1, }; - - /* ANT_SEL */ --static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; --static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; -+static const int mt7981_ant_sel_pins[] = { -+ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -+static const int mt7981_ant_sel_funcs[] = { -+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; - - static const struct mtk_group_desc mt7981_groups[] = { - /* @GPIO(0,1): WA_AICE(2) */ -@@ -1012,7 +1016,7 @@ static const char *const mt7981_pinctrl_ - "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", - }; - --static struct mtk_pinctrl_soc mt7981_data = { -+static const struct mtk_pinctrl_soc mt7981_data = { - .name = "mt7981_pinctrl", - .reg_cal = mt7981_reg_cals, - .pins = mt7981_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -554,114 +554,117 @@ static const struct mtk_io_type_desc mt7 - * The hardware probably has multiple combinations of these pinouts. - */ - --static int mt7986_watchdog_pins[] = { 0, }; --static int mt7986_watchdog_funcs[] = { 1, }; -+static const int mt7986_watchdog_pins[] = { 0, }; -+static const int mt7986_watchdog_funcs[] = { 1, }; - --static int mt7986_wifi_led_pins[] = { 1, 2, }; --static int mt7986_wifi_led_funcs[] = { 1, 1, }; -+static const int mt7986_wifi_led_pins[] = { 1, 2, }; -+static const int mt7986_wifi_led_funcs[] = { 1, 1, }; - --static int mt7986_i2c_pins[] = { 3, 4, }; --static int mt7986_i2c_funcs[] = { 1, 1, }; -+static const int mt7986_i2c_pins[] = { 3, 4, }; -+static const int mt7986_i2c_funcs[] = { 1, 1, }; - --static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; --static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, }; -+static const int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, }; - --static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; --static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, }; -+static const int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, }; - --static int mt7986_pwm1_1_pins[] = { 20, }; --static int mt7986_pwm1_1_funcs[] = { 2, }; -+static const int mt7986_pwm1_1_pins[] = { 20, }; -+static const int mt7986_pwm1_1_funcs[] = { 2, }; - --static int mt7986_pwm0_pins[] = { 21, }; --static int mt7986_pwm0_funcs[] = { 1, }; -+static const int mt7986_pwm0_pins[] = { 21, }; -+static const int mt7986_pwm0_funcs[] = { 1, }; - --static int mt7986_pwm1_0_pins[] = { 22, }; --static int mt7986_pwm1_0_funcs[] = { 1, }; -+static const int mt7986_pwm1_0_pins[] = { 22, }; -+static const int mt7986_pwm1_0_funcs[] = { 1, }; - --static int mt7986_emmc_45_pins[] = { -+static const int mt7986_emmc_45_pins[] = { - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, }; --static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+static const int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - --static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; --static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; -+static const int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, }; -+static const int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, }; - --static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; --static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, }; -+static const int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, }; - --static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; --static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, }; -+static const int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; - --static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; --static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; -+static const int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; -+static const int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; - --static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; -+static const int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; - --static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; --static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; -+static const int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; --static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; -+static const int mt7986_spi0_wp_hold_pins[] = { 37, 38, }; -+static const int mt7986_spi0_wp_hold_funcs[] = { 1, 1, }; - --static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; --static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+static const int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, }; -+static const int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, }; - --static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; --static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; -+static const int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, }; -+static const int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, }; - --static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; --static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; -+static const int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, }; -+static const int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, }; - --static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; --static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; -+static const int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, }; -+static const int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, }; - --static int mt7986_uart0_pins[] = { 39, 40, }; --static int mt7986_uart0_funcs[] = { 1, 1, }; -+static const int mt7986_uart0_pins[] = { 39, 40, }; -+static const int mt7986_uart0_funcs[] = { 1, 1, }; - --static int mt7986_pcie_reset_pins[] = { 41, }; --static int mt7986_pcie_reset_funcs[] = { 1, }; -+static const int mt7986_pcie_reset_pins[] = { 41, }; -+static const int mt7986_pcie_reset_funcs[] = { 1, }; - --static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; --static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; -+static const int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; --static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; -+static const int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_emmc_51_pins[] = { -+static const int mt7986_emmc_51_pins[] = { - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, }; --static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7986_emmc_51_funcs[] = { -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - --static int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; --static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_pcm_pins[] = { 62, 63, 64, 65, }; -+static const int mt7986_pcm_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; --static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; -+static const int mt7986_i2s_pins[] = { 62, 63, 64, 65, }; -+static const int mt7986_i2s_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_switch_int_pins[] = { 66, }; --static int mt7986_switch_int_funcs[] = { 1, }; -+static const int mt7986_switch_int_pins[] = { 66, }; -+static const int mt7986_switch_int_funcs[] = { 1, }; - --static int mt7986_mdc_mdio_pins[] = { 67, 68, }; --static int mt7986_mdc_mdio_funcs[] = { 1, 1, }; -+static const int mt7986_mdc_mdio_pins[] = { 67, 68, }; -+static const int mt7986_mdc_mdio_funcs[] = { 1, 1, }; - --static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; --static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7986_wf_2g_pins[] = { -+ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, }; -+static const int mt7986_wf_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - --static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; --static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt7986_wf_5g_pins[] = { -+ 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, }; -+static const int mt7986_wf_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - --static int mt7986_wf_dbdc_pins[] = { -+static const int mt7986_wf_dbdc_pins[] = { - 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, }; --static int mt7986_wf_dbdc_funcs[] = { -+static const int mt7986_wf_dbdc_funcs[] = { - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - --static int mt7986_pcie_clk_pins[] = { 9, }; --static int mt7986_pcie_clk_funcs[] = { 1, }; -+static const int mt7986_pcie_clk_pins[] = { 9, }; -+static const int mt7986_pcie_clk_funcs[] = { 1, }; - --static int mt7986_pcie_wake_pins[] = { 10, }; --static int mt7986_pcie_wake_funcs[] = { 1, }; -+static const int mt7986_pcie_wake_pins[] = { 10, }; -+static const int mt7986_pcie_wake_funcs[] = { 1, }; - - static const struct mtk_group_desc mt7986_groups[] = { - PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog), -@@ -738,7 +741,7 @@ static const struct mtk_function_desc mt - {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)}, - }; - --static struct mtk_pinctrl_soc mt7986_data = { -+static const struct mtk_pinctrl_soc mt7986_data = { - .name = "mt7986_pinctrl", - .reg_cal = mt7986_reg_cals, - .pins = mt7986_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c -@@ -315,12 +315,12 @@ static const struct mtk_pin_desc mt8512_ - */ - - /* UART */ --static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; --static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; --static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; --static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; -+static const int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; -+static const int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; -+static const int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; - - /* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. -@@ -330,13 +330,13 @@ static const char *const mt8512_uart_gro - "uart2_0_rxd_txd", }; - - /* SNAND */ --static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; --static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+static const int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; -+static const int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; - - /* MMC0 */ --static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, -- 85, 86, }; --static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, -+ 85, 86, }; -+static const int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - static const struct mtk_group_desc mt8512_groups[] = { - PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), -@@ -356,7 +356,7 @@ static const struct mtk_function_desc mt - {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, - }; - --static struct mtk_pinctrl_soc mt8512_data = { -+static const struct mtk_pinctrl_soc mt8512_data = { - .name = "mt8512_pinctrl", - .reg_cal = mt8512_reg_cals, - .pins = mt8512_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c -@@ -326,12 +326,12 @@ static const struct mtk_pin_desc mt8516_ - */ - - /* UART */ --static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; --static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; --static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; --static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, }; -+static const int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, }; -+static const int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, }; -+static const int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, }; - - /* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. -@@ -341,9 +341,9 @@ static const char *const mt8516_uart_gro - "uart2_0_rxd_txd", }; - - /* MMC0 */ --static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118, -- 119, 120, }; --static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, -+ 118, 119, 120, }; -+static const int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - static const struct mtk_group_desc mt8516_groups[] = { - PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd), ---- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c -@@ -346,12 +346,12 @@ static const struct mtk_pin_desc mt8518_ - */ - - /* UART */ --static int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; --static int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; --static int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; --static int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; --static int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8518_uart0_0_rxd_txd_pins[] = { 104, 105, }; -+static const int mt8518_uart0_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8518_uart1_0_rxd_txd_pins[] = { 52, 53, }; -+static const int mt8518_uart1_0_rxd_txd_funcs[] = { 1, 1, }; -+static const int mt8518_uart2_0_rxd_txd_pins[] = { 106, 107, }; -+static const int mt8518_uart2_0_rxd_txd_funcs[] = { 1, 1, }; - - /* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. -@@ -361,9 +361,9 @@ static const char *const mt8518_uart_gro - "uart2_0_rxd_txd", }; - - /* MMC0 */ --static int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, -- 12, 13, }; --static int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; -+static const int mt8518_msdc0_pins[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, -+ 12, 13, }; -+static const int mt8518_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; - - static const struct mtk_group_desc mt8518_groups[] = { - PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8518_uart0_0_rxd_txd), -@@ -380,7 +380,7 @@ static const struct mtk_function_desc mt - {"msdc", mt8518_msdc_groups, ARRAY_SIZE(mt8518_msdc_groups)}, - }; - --static struct mtk_pinctrl_soc mt8518_data = { -+static const struct mtk_pinctrl_soc mt8518_data = { - .name = "mt8518_pinctrl", - .reg_cal = mt8518_reg_cals, - .pins = mt8518_pins, ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -314,7 +314,7 @@ static int mtk_pinmux_group_set(struct u - int i; - - for (i = 0; i < grp->num_pins; i++) { -- int *pin_modes = grp->data; -+ const int *pin_modes = grp->data; - - mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, - pin_modes[i]); -@@ -769,7 +769,7 @@ static int mtk_gpiochip_register(struct - #endif - - int mtk_pinctrl_common_probe(struct udevice *dev, -- struct mtk_pinctrl_soc *soc) -+ const struct mtk_pinctrl_soc *soc) - { - struct mtk_pinctrl_priv *priv = dev_get_priv(dev); - int ret = 0; ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h -@@ -174,9 +174,9 @@ struct mtk_pin_desc { - */ - struct mtk_group_desc { - const char *name; -- int *pins; -+ const int *pins; - int num_pins; -- void *data; -+ const void *data; - }; - - /** -@@ -233,7 +233,7 @@ struct mtk_pinctrl_soc { - */ - struct mtk_pinctrl_priv { - void __iomem *base[MAX_BASE_CALC]; -- struct mtk_pinctrl_soc *soc; -+ const struct mtk_pinctrl_soc *soc; - }; - - extern const struct pinctrl_ops mtk_pinctrl_ops; -@@ -242,7 +242,7 @@ extern const struct pinctrl_ops mtk_pinc - void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); - void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set); - int mtk_pinctrl_common_probe(struct udevice *dev, -- struct mtk_pinctrl_soc *soc); -+ const struct mtk_pinctrl_soc *soc); - - #if CONFIG_IS_ENABLED(PINCONF) - diff --git a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch b/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch deleted file mode 100644 index d83a89ab37..0000000000 --- a/package/boot/uboot-mediatek/patches/101-13-pinctrl-mediatek-fix-the-return-value-in-driving-con.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 783c46d29f8b186bd65f3e83f38ad883e8bcec69 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:42 +0800 -Subject: [PATCH 13/29] pinctrl: mediatek: fix the return value in driving - configuration functions - -The original mediatek pinctrl functions for driving configuration -'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input -parameters are not supported. -This patch fixes the return value in those functions. - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -513,7 +513,7 @@ int mtk_pinconf_drive_set_v0(struct udev - return err; - } - -- return 0; -+ return err; - } - - int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) -@@ -531,7 +531,7 @@ int mtk_pinconf_drive_set_v1(struct udev - return err; - } - -- return 0; -+ return err; - } - - int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) diff --git a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch b/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch deleted file mode 100644 index 7cb185ff42..0000000000 --- a/package/boot/uboot-mediatek/patches/101-14-pinctrl-mediatek-add-pinmux_set-ops-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 090351b416e57e0f7b5d1a4c87d4ed9ab4f5c89b Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:46 +0800 -Subject: [PATCH 14/29] pinctrl: mediatek: add pinmux_set ops support - -This patch adds pinmux_set ops for mediatek pinctrl framework - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -304,6 +304,19 @@ static const char *mtk_get_function_name - return priv->soc->funcs[selector].name; - } - -+static int mtk_pinmux_set(struct udevice *dev, unsigned int pin_selector, -+ unsigned int func_selector) -+{ -+ int err; -+ -+ err = mtk_hw_set_value(dev, pin_selector, PINCTRL_PIN_REG_MODE, -+ func_selector); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ - static int mtk_pinmux_group_set(struct udevice *dev, - unsigned int group_selector, - unsigned int func_selector) -@@ -647,6 +660,7 @@ const struct pinctrl_ops mtk_pinctrl_ops - .get_group_name = mtk_get_group_name, - .get_functions_count = mtk_get_functions_count, - .get_function_name = mtk_get_function_name, -+ .pinmux_set = mtk_pinmux_set, - .pinmux_group_set = mtk_pinmux_group_set, - #if CONFIG_IS_ENABLED(PINCONF) - .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), diff --git a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch deleted file mode 100644 index cfc7c32ba3..0000000000 --- a/package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch +++ /dev/null @@ -1,1315 +0,0 @@ -From 5e821f4ebd9da4ccf3c8871e402996f6a6eb8d1c Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:50 +0800 -Subject: [PATCH 15/29] pinctrl: mediatek: add pinctrl driver for MT7988 SoC - -This patch adds pinctrl and gpio support for MT7988 SoC - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/Kconfig | 4 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 +++++++++++++++++++++ - 3 files changed, 1279 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -24,6 +24,10 @@ config PINCTRL_MT7986 - bool "MT7986 SoC pinctrl driver" - select PINCTRL_MTK - -+config PINCTRL_MT7988 -+ bool "MT7988 SoC pinctrl driver" -+ select PINCTRL_MTK -+ - config PINCTRL_MT8512 - bool "MT8512 SoC pinctrl driver" - select PINCTRL_MTK ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o - obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o - obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c -@@ -0,0 +1,1274 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#include <dm.h> -+#include "pinctrl-mtk-common.h" -+ -+enum MT7988_PINCTRL_REG_PAGE { -+ GPIO_BASE, -+ IOCFG_TR_BASE, -+ IOCFG_BR_BASE, -+ IOCFG_RB_BASE, -+ IOCFG_LB_BASE, -+ IOCFG_TL_BASE, -+}; -+ -+#define MT7988_TYPE0_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) -+ -+#define MT7988_TYPE1_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) -+ -+#define MT7988_TYPE2_PIN(_number, _name) \ -+ MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2) -+ -+#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ -+ _s_bit, _x_bits, 32, 0) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ -+ _s_bit, _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits) \ -+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ -+ _s_bit, _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { -+ PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { -+ PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { -+ PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { -+ PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1), -+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1), -+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { -+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { -+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3), -+ PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3), -+ PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1), -+ PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1), -+ -+ PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1), -+ PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1), -+ PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1), -+ PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1), -+ PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1), -+ PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1), -+ PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1), -+ PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1), -+ PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1), -+ PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1), -+ PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1), -+ PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1), -+ PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1), -+ PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1), -+ PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1), -+ PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1), -+ PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1), -+ PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1), -+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1), -+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1), -+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1), -+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1), -+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1), -+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1), -+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1), -+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1), -+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1), -+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1), -+ PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1), -+ PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1), -+ PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1), -+ PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1), -+ PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1), -+ -+ PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1), -+ PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1), -+ PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1), -+ PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1), -+ -+ PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1), -+ -+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1), -+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1), -+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1), -+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1), -+}; -+ -+static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7988_pins[] = { -+ MT7988_TYPE0_PIN(0, "UART2_RXD"), -+ MT7988_TYPE0_PIN(1, "UART2_TXD"), -+ MT7988_TYPE0_PIN(2, "UART2_CTS"), -+ MT7988_TYPE0_PIN(3, "UART2_RTS"), -+ MT7988_TYPE0_PIN(4, "GPIO_A"), -+ MT7988_TYPE0_PIN(5, "SMI_0_MDC"), -+ MT7988_TYPE0_PIN(6, "SMI_0_MDIO"), -+ MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"), -+ MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"), -+ MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"), -+ MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"), -+ MT7988_TYPE0_PIN(11, "GPIO_P"), -+ MT7988_TYPE0_PIN(12, "WATCHDOG"), -+ MT7988_TYPE1_PIN(13, "GPIO_RESET"), -+ MT7988_TYPE1_PIN(14, "GPIO_WPS"), -+ MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"), -+ MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"), -+ MT7988_TYPE2_PIN(17, "I2C_1_SCL"), -+ MT7988_TYPE2_PIN(18, "I2C_1_SDA"), -+ MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"), -+ MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"), -+ MT7988_TYPE0_PIN(21, "PWMD1"), -+ MT7988_TYPE0_PIN(22, "SPI0_WP"), -+ MT7988_TYPE0_PIN(23, "SPI0_HOLD"), -+ MT7988_TYPE0_PIN(24, "SPI0_CSB"), -+ MT7988_TYPE0_PIN(25, "SPI0_MISO"), -+ MT7988_TYPE0_PIN(26, "SPI0_MOSI"), -+ MT7988_TYPE0_PIN(27, "SPI0_CLK"), -+ MT7988_TYPE0_PIN(28, "SPI1_CSB"), -+ MT7988_TYPE0_PIN(29, "SPI1_MISO"), -+ MT7988_TYPE0_PIN(30, "SPI1_MOSI"), -+ MT7988_TYPE0_PIN(31, "SPI1_CLK"), -+ MT7988_TYPE0_PIN(32, "SPI2_CLK"), -+ MT7988_TYPE0_PIN(33, "SPI2_MOSI"), -+ MT7988_TYPE0_PIN(34, "SPI2_MISO"), -+ MT7988_TYPE0_PIN(35, "SPI2_CSB"), -+ MT7988_TYPE0_PIN(36, "SPI2_HOLD"), -+ MT7988_TYPE0_PIN(37, "SPI2_WP"), -+ MT7988_TYPE0_PIN(38, "EMMC_RSTB"), -+ MT7988_TYPE0_PIN(39, "EMMC_DSL"), -+ MT7988_TYPE0_PIN(40, "EMMC_CK"), -+ MT7988_TYPE0_PIN(41, "EMMC_CMD"), -+ MT7988_TYPE0_PIN(42, "EMMC_DATA_7"), -+ MT7988_TYPE0_PIN(43, "EMMC_DATA_6"), -+ MT7988_TYPE0_PIN(44, "EMMC_DATA_5"), -+ MT7988_TYPE0_PIN(45, "EMMC_DATA_4"), -+ MT7988_TYPE0_PIN(46, "EMMC_DATA_3"), -+ MT7988_TYPE0_PIN(47, "EMMC_DATA_2"), -+ MT7988_TYPE0_PIN(48, "EMMC_DATA_1"), -+ MT7988_TYPE0_PIN(49, "EMMC_DATA_0"), -+ MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"), -+ MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"), -+ MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"), -+ MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"), -+ MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"), -+ MT7988_TYPE0_PIN(55, "UART0_RXD"), -+ MT7988_TYPE0_PIN(56, "UART0_TXD"), -+ MT7988_TYPE0_PIN(57, "PWMD0"), -+ MT7988_TYPE0_PIN(58, "JTAG_JTDI"), -+ MT7988_TYPE0_PIN(59, "JTAG_JTDO"), -+ MT7988_TYPE0_PIN(60, "JTAG_JTMS"), -+ MT7988_TYPE0_PIN(61, "JTAG_JTCLK"), -+ MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"), -+ MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"), -+ MT7988_TYPE0_PIN(64, "LED_A"), -+ MT7988_TYPE0_PIN(65, "LED_B"), -+ MT7988_TYPE0_PIN(66, "LED_C"), -+ MT7988_TYPE0_PIN(67, "LED_D"), -+ MT7988_TYPE0_PIN(68, "LED_E"), -+ MT7988_TYPE0_PIN(69, "GPIO_B"), -+ MT7988_TYPE0_PIN(70, "GPIO_C"), -+ MT7988_TYPE2_PIN(71, "I2C_2_SCL"), -+ MT7988_TYPE2_PIN(72, "I2C_2_SDA"), -+ MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"), -+ MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"), -+ MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"), -+ MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"), -+ MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"), -+ MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"), -+ MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"), -+ MT7988_TYPE0_PIN(80, "UART1_RXD"), -+ MT7988_TYPE0_PIN(81, "UART1_TXD"), -+ MT7988_TYPE0_PIN(82, "UART1_CTS"), -+ MT7988_TYPE0_PIN(83, "UART1_RTS"), -+}; -+ -+/* jtag */ -+static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -+static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; -+ -+static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -+static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -+static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -+static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* int_usxgmii */ -+static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; -+static const int mt7988_int_usxgmii_funcs[] = { 3, 3 }; -+ -+/* pwm */ -+static const int mt7988_pwm0_pins[] = { 57 }; -+static const int mt7988_pwm0_funcs[] = { 1 }; -+ -+static const int mt7988_pwm1_pins[] = { 21 }; -+static const int mt7988_pwm1_funcs[] = { 1 }; -+ -+static const int mt7988_pwm2_pins[] = { 80 }; -+static const int mt7988_pwm2_funcs[] = { 2 }; -+ -+static const int mt7988_pwm3_pins[] = { 81 }; -+static const int mt7988_pwm3_funcs[] = { 2 }; -+ -+static const int mt7988_pwm4_pins[] = { 82 }; -+static const int mt7988_pwm4_funcs[] = { 2 }; -+ -+static const int mt7988_pwm5_pins[] = { 83 }; -+static const int mt7988_pwm5_funcs[] = { 2 }; -+ -+static const int mt7988_pwm6_pins[] = { 69 }; -+static const int mt7988_pwm6_funcs[] = { 3 }; -+ -+static const int mt7988_pwm7_pins[] = { 70 }; -+static const int mt7988_pwm7_funcs[] = { 3 }; -+ -+/* dfd */ -+static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -+static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* i2c */ -+static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -+static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -+static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -+static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -+static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_0_pins[] = { 5, 6 }; -+static const int mt7988_i2c0_0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -+static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; -+ -+static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -+static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -+static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c0_1_pins[] = { 15, 16 }; -+static const int mt7988_i2c0_1_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -+static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -+static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -+static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; -+ -+static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -+static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; -+ -+static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -+static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; -+ -+static const int mt7988_i2c1_0_pins[] = { 17, 18 }; -+static const int mt7988_i2c1_0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -+static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; -+ -+static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -+static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -+static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; -+ -+static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -+static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -+static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; -+ -+static const int mt7988_i2c1_2_pins[] = { 69, 70 }; -+static const int mt7988_i2c1_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_i2c2_0_pins[] = { 69, 70 }; -+static const int mt7988_i2c2_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_i2c2_1_pins[] = { 71, 72 }; -+static const int mt7988_i2c2_1_funcs[] = { 1, 1 }; -+ -+/* eth */ -+static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -+static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -+static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -+static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; -+ -+static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -+static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; -+ -+/* pcie */ -+static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -+static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -+static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -+static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -+static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -+static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -+static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; -+ -+static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -+static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -+static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; -+ -+static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -+static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -+static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; -+ -+static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -+static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -+static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -+static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -+static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -+static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; -+ -+static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -+static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -+static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -+static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -+static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -+static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -+static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; -+ -+static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -+static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; -+ -+/* pmic */ -+static const int mt7988_pmic_pins[] = { 11 }; -+static const int mt7988_pmic_funcs[] = { 1 }; -+ -+/* watchdog */ -+static const int mt7988_watchdog_pins[] = { 12 }; -+static const int mt7988_watchdog_funcs[] = { 1 }; -+ -+/* spi */ -+static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -+static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; -+ -+static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -+static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -+static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -+static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -+static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; -+ -+/* flash */ -+static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -+static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+static const int mt7988_emmc_45_pins[] = { -+ 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 }; -+static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; -+ -+static const int mt7988_emmc_51_pins[] = { -+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 }; -+static const int mt7988_emmc_51_funcs[] = { -+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* uart */ -+static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -+static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -+static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -+static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -+static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -+static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -+static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -+static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -+static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; -+ -+static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -+static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -+static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; -+ -+static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -+static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; -+ -+static const int mt7988_uart0_pins[] = { 55, 56 }; -+static const int mt7988_uart0_funcs[] = { 1, 1 }; -+ -+static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -+static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; -+ -+static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -+static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -+static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; -+ -+static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -+static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; -+ -+static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -+static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -+static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; -+ -+static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -+static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -+static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; -+ -+static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -+static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; -+ -+/* udi */ -+static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -+static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; -+ -+/* pcm */ -+static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 }; -+static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 }; -+ -+/* led */ -+static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 }; -+static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 }; -+ -+static const int mt7988_2p5gbe_led1_pins[] = { 62 }; -+static const int mt7988_2p5gbe_led1_funcs[] = { 6 }; -+ -+static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 }; -+static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 }; -+ -+static const int mt7988_2p5gbe_led0_pins[] = { 68 }; -+static const int mt7988_2p5gbe_led0_funcs[] = { 1 }; -+ -+/* usb */ -+static const int mt7988_drv_vbus_p1_pins[] = { 63 }; -+static const int mt7988_drv_vbus_p1_funcs[] = { 1 }; -+ -+static const int mt7988_drv_vbus_pins[] = { 79 }; -+static const int mt7988_drv_vbus_funcs[] = { 1 }; -+ -+static const struct mtk_group_desc mt7988_groups[] = { -+ PINCTRL_PIN_GROUP("uart2", mt7988_uart2), -+ PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), -+ PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), -+ PINCTRL_PIN_GROUP("dfd", mt7988_dfd), -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), -+ PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), -+ PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), -+ PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), -+ PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), -+ PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), -+ PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), -+ PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), -+ PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), -+ PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), -+ PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), -+ PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), -+ PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), -+ PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), -+ PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), -+ PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), -+ PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), -+ PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), -+ PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), -+ PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), -+ PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), -+ PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), -+ PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), -+ PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), -+ PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), -+ PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), -+ PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), -+ PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), -+ PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), -+ PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), -+ PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), -+ PINCTRL_PIN_GROUP("spi0", mt7988_spi0), -+ PINCTRL_PIN_GROUP("spi1", mt7988_spi1), -+ PINCTRL_PIN_GROUP("spi2", mt7988_spi2), -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), -+ PINCTRL_PIN_GROUP("snfi", mt7988_snfi), -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), -+ PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), -+ PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), -+ PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), -+ PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), -+ PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), -+ PINCTRL_PIN_GROUP("udi", mt7988_udi), -+ PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), -+ PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), -+ PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), -+ PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), -+ PINCTRL_PIN_GROUP("pcm", mt7988_pcm), -+ PINCTRL_PIN_GROUP("uart0", mt7988_uart0), -+ PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), -+ PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), -+ PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), -+ PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), -+ PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), -+ PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), -+ PINCTRL_PIN_GROUP("jtag", mt7988_jtag), -+ PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), -+ PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), -+ PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), -+ PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1), -+ PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), -+ PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0), -+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), -+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), -+ PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), -+ PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), -+ PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), -+ PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), -+ PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), -+ PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), -+ PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), -+ PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), -+ PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), -+ PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), -+ PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), -+ PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), -+ PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), -+ PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), -+ PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), -+ PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), -+ PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), -+ PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), -+ PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), -+ PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), -+ PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -+}; -+ -+static const struct mtk_io_type_desc mt7988_io_type_desc[] = { -+ [IO_TYPE_GRP0] = { -+ .name = "18OD33", -+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+ [IO_TYPE_GRP1] = { -+ .name = "18A01", -+ .bias_set = mtk_pinconf_bias_set_pu_pd, -+ .drive_set = mtk_pinconf_drive_set_v1, -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+ [IO_TYPE_GRP2] = { -+ .name = "I2C", -+ .input_enable = mtk_pinconf_input_enable_v1, -+ }, -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag", -+ "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", }; -+static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", }; -+static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3", -+ "pwm4", "pwm5", "pwm6", "pwm7" }; -+static const char *const mt7988_dfd_groups[] = { "dfd", }; -+static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0", -+ "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0", -+ "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1", -+ "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1", -+ "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1", -+ "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0", -+ "i2c2_1", }; -+static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0", -+ "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", }; -+static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0", -+ "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3", -+ "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2", -+ "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1", -+ "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1", -+ "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0", -+ "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", }; -+static const char *const mt7988_pmic_groups[] = { "pmic", }; -+static const char *const mt7988_wdt_groups[] = { "watchdog", }; -+static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold", -+ "spi1", "spi2", "spi2_wp_hold", }; -+static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi", -+ "emmc_51" }; -+static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0", -+ "uart2_0", "uart1_0", "uart2_1", -+ "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0", -+ "tops_uart1_0", "ops_uart0_1", "ops_uart1_1", -+ "uart0", "tops_uart0_2", "uart1_1", -+ "uart2_3", "uart1_2", "tops_uart1_2", -+ "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", }; -+static const char *const mt7988_udi_groups[] = { "udi", }; -+static const char *const mt7988_pcm_groups[] = { "pcm", }; -+static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1", -+ "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", }; -+static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", }; -+ -+static const struct mtk_function_desc mt7988_functions[] = { -+ {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)}, -+ {"int_usxgmii", mt7988_int_usxgmii_groups, -+ ARRAY_SIZE(mt7988_int_usxgmii_groups)}, -+ {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)}, -+ {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)}, -+ {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)}, -+ {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)}, -+ {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)}, -+ {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)}, -+ {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)}, -+ {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)}, -+ {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)}, -+ {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)}, -+ {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)}, -+ {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)}, -+ {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)}, -+ {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)}, -+}; -+ -+static const char *const mt7988_pinctrl_register_base_names[] = { -+ "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", -+ "iocfg_lb_base", "iocfg_tl_base", -+}; -+ -+static const struct mtk_pinctrl_soc mt7988_data = { -+ .name = "mt7988_pinctrl", -+ .reg_cal = mt7988_reg_cals, -+ .pins = mt7988_pins, -+ .npins = ARRAY_SIZE(mt7988_pins), -+ .grps = mt7988_groups, -+ .ngrps = ARRAY_SIZE(mt7988_groups), -+ .funcs = mt7988_functions, -+ .nfuncs = ARRAY_SIZE(mt7988_functions), -+ .io_type = mt7988_io_type_desc, -+ .ntype = ARRAY_SIZE(mt7988_io_type_desc), -+ .gpio_mode = 0, -+ .base_names = mt7988_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), -+ .base_calc = 1, -+}; -+ -+static int mtk_pinctrl_mt7988_probe(struct udevice *dev) -+{ -+ return mtk_pinctrl_common_probe(dev, &mt7988_data); -+} -+ -+static const struct udevice_id mt7988_pctrl_match[] = { -+ {.compatible = "mediatek,mt7988-pinctrl"}, -+ { /* sentinel */ } -+}; -+ -+U_BOOT_DRIVER(mt7988_pinctrl) = { -+ .name = "mt7988_pinctrl", -+ .id = UCLASS_PINCTRL, -+ .of_match = mt7988_pctrl_match, -+ .ops = &mtk_pinctrl_ops, -+ .probe = mtk_pinctrl_mt7988_probe, -+ .priv_auto = sizeof(struct mtk_pinctrl_priv), -+}; diff --git a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch b/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch deleted file mode 100644 index e3e6212742..0000000000 --- a/package/boot/uboot-mediatek/patches/101-16-net-mediatek-connect-switch-to-PSE-only-when-startin.patch +++ /dev/null @@ -1,138 +0,0 @@ -From a0405999ebecf21ed9f76f1dc9420682cd3feba0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:54 +0800 -Subject: [PATCH 16/29] net: mediatek: connect switch to PSE only when starting - eth is requested - -So far the switch is initialized in probe stage and is connected to PSE -unconditionally. This will cause all packets being flooded to PSE and may -cause PSE hang before entering linux. - -This patch changes the connection between switch and PSE: -- Still initialize switch in probe stage, but disconnect it with PSE -- Connect switch with PSE on eth start -- Disconnect on eth stop - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 44 ++++++++++++++++++++++++++++++++++++++++--- - 1 file changed, 41 insertions(+), 3 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -123,8 +123,10 @@ struct mtk_eth_priv { - - enum mtk_switch sw; - int (*switch_init)(struct mtk_eth_priv *priv); -+ void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); - u32 mt753x_smi_addr; - u32 mt753x_phy_base; -+ u32 mt753x_pmcr; - - struct gpio_desc rst_gpio; - int mcm; -@@ -613,6 +615,16 @@ static int mt7530_pad_clk_setup(struct m - return 0; - } - -+static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) -+{ -+ u32 pmcr = FORCE_MODE; -+ -+ if (enable) -+ pmcr = priv->mt753x_pmcr; -+ -+ mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ - static int mt7530_setup(struct mtk_eth_priv *priv) - { - u16 phy_addr, phy_val; -@@ -663,11 +675,14 @@ static int mt7530_setup(struct mtk_eth_p - FORCE_DPX | FORCE_LINK; - - /* MT7530 Port6: Forced 1000M/FD, FC disabled */ -- mt753x_reg_write(priv, PMCR_REG(6), val); -+ priv->mt753x_pmcr = val; - - /* MT7530 Port5: Forced link down */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); - -+ /* Keep MAC link down before starting eth */ -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); -+ - /* MT7530 Port6: Set to RGMII */ - mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); - -@@ -823,6 +838,17 @@ static void mt7531_phy_setting(struct mt - } - } - -+static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) -+{ -+ u32 pmcr = FORCE_MODE_LNK; -+ -+ if (enable) -+ pmcr = priv->mt753x_pmcr; -+ -+ mt753x_reg_write(priv, PMCR_REG(5), pmcr); -+ mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ - static int mt7531_setup(struct mtk_eth_priv *priv) - { - u16 phy_addr, phy_val; -@@ -882,8 +908,11 @@ static int mt7531_setup(struct mtk_eth_p - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | - FORCE_LINK; - -- mt753x_reg_write(priv, PMCR_REG(5), pmcr); -- mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+ priv->mt753x_pmcr = pmcr; -+ -+ /* Keep MAC link down before starting eth */ -+ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { -@@ -1227,6 +1256,9 @@ static int mtk_eth_start(struct udevice - - mtk_eth_fifo_init(priv); - -+ if (priv->switch_mac_control) -+ priv->switch_mac_control(priv, true); -+ - /* Start PHY */ - if (priv->sw == SW_NONE) { - ret = mtk_phy_start(priv); -@@ -1245,6 +1277,9 @@ static void mtk_eth_stop(struct udevice - { - struct mtk_eth_priv *priv = dev_get_priv(dev); - -+ if (priv->switch_mac_control) -+ priv->switch_mac_control(priv, false); -+ - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, - TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); - udelay(500); -@@ -1484,16 +1519,19 @@ static int mtk_eth_of_to_plat(struct ude - /* check for switch first, otherwise phy will be used */ - priv->sw = SW_NONE; - priv->switch_init = NULL; -+ priv->switch_mac_control = NULL; - str = dev_read_string(dev, "mediatek,switch"); - - if (str) { - if (!strcmp(str, "mt7530")) { - priv->sw = SW_MT7530; - priv->switch_init = mt7530_setup; -+ priv->switch_mac_control = mt7530_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - } else if (!strcmp(str, "mt7531")) { - priv->sw = SW_MT7531; - priv->switch_init = mt7531_setup; -+ priv->switch_mac_control = mt7531_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - } else { - printf("error: unsupported switch\n"); diff --git a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch b/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch deleted file mode 100644 index c8823ac545..0000000000 --- a/package/boot/uboot-mediatek/patches/101-17-net-mediatek-optimize-the-switch-reset-delay-wait-ti.patch +++ /dev/null @@ -1,56 +0,0 @@ -From d9a52701f6677889cc3332ab7a888f35cd69cc76 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:16:59 +0800 -Subject: [PATCH 17/29] net: mediatek: optimize the switch reset delay wait - time - -Not all switches requires 1 second delay after deasserting reset. -MT7531 requires only maximum 200ms. - -This patch defines dedicated reset wait time for each switch chip, and will -significantly improve the boot time for boards using MT7531. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -127,6 +127,7 @@ struct mtk_eth_priv { - u32 mt753x_smi_addr; - u32 mt753x_phy_base; - u32 mt753x_pmcr; -+ u32 mt753x_reset_wait_time; - - struct gpio_desc rst_gpio; - int mcm; -@@ -943,12 +944,12 @@ int mt753x_switch_init(struct mtk_eth_pr - reset_assert(&priv->rst_mcm); - udelay(1000); - reset_deassert(&priv->rst_mcm); -- mdelay(1000); -+ mdelay(priv->mt753x_reset_wait_time); - } else if (dm_gpio_is_valid(&priv->rst_gpio)) { - dm_gpio_set_value(&priv->rst_gpio, 0); - udelay(1000); - dm_gpio_set_value(&priv->rst_gpio, 1); -- mdelay(1000); -+ mdelay(priv->mt753x_reset_wait_time); - } - - ret = priv->switch_init(priv); -@@ -1528,11 +1529,13 @@ static int mtk_eth_of_to_plat(struct ude - priv->switch_init = mt7530_setup; - priv->switch_mac_control = mt7530_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->mt753x_reset_wait_time = 1000; - } else if (!strcmp(str, "mt7531")) { - priv->sw = SW_MT7531; - priv->switch_init = mt7531_setup; - priv->switch_mac_control = mt7531_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->mt753x_reset_wait_time = 200; - } else { - printf("error: unsupported switch\n"); - return -EINVAL; diff --git a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch b/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch deleted file mode 100644 index 5214e842c8..0000000000 --- a/package/boot/uboot-mediatek/patches/101-18-net-mediatek-fix-direct-MDIO-clause-45-access-via-So.patch +++ /dev/null @@ -1,34 +0,0 @@ -From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:03 +0800 -Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC - -The original direct MDIO clause 45 access via SoC is missing the -data output. This patch adds it back to ensure MDIO clause 45 can -work properly for external PHYs. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri - (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | - (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); - -- if (cmd == MDIO_CMD_WRITE) -+ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) - val |= data & MDIO_RW_DATA_M; - - mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); -@@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri - return ret; - } - -- if (cmd == MDIO_CMD_READ) { -+ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { - val = mtk_gmac_read(priv, GMAC_PIAC_REG); - return val & MDIO_RW_DATA_M; - } diff --git a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch b/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch deleted file mode 100644 index 9350ca04dc..0000000000 --- a/package/boot/uboot-mediatek/patches/101-19-net-mediatek-add-missing-static-qualifier.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 9d35558bedfb82860c63cc11d3426afcbd82cb5c Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:07 +0800 -Subject: [PATCH 19/29] net: mediatek: add missing static qualifier - -mt7531_mmd_ind_read and mt753x_switch_init are defined without static. -Since they're not used outside this file, we should add them back. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> - -fixup to add static qualifier ---- - drivers/net/mtk_eth.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -436,7 +436,8 @@ static int mt7531_mii_ind_write(struct m - MDIO_ST_C22); - } - --int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) -+static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, -+ u16 reg) - { - u8 phy_addr; - int ret; -@@ -934,7 +935,7 @@ static int mt7531_setup(struct mtk_eth_p - return 0; - } - --int mt753x_switch_init(struct mtk_eth_priv *priv) -+static int mt753x_switch_init(struct mtk_eth_priv *priv) - { - int ret; - int i; diff --git a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch b/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch deleted file mode 100644 index 45acbc36ac..0000000000 --- a/package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:13 +0800 -Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps - auto-negotiation mode - -Existing SGMII support of mtk-eth is actually a MediaTek-specific -2.5Gbps high-speed SGMII (HSGMII) which does not support -auto-negotiation mode. - -This patch adds SGMII 1Gbps auto-negotiation mode and rename the -existing HSGMII to 2500basex. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------ - drivers/net/mtk_eth.h | 2 ++ - 2 files changed, 42 insertions(+), 6 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p - if (!port5_sgmii) - mt7531_port_rgmii_init(priv, 5); - break; -- case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_2500BASEX: - mt7531_port_sgmii_init(priv, 6); - if (port5_sgmii) - mt7531_port_sgmii_init(priv, 5); -@@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m - (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | - MAC_MODE | FORCE_MODE | - MAC_TX_EN | MAC_RX_EN | -+ DEL_RXFIFO_CLR | - BKOFF_EN | BACKPR_EN; - - switch (priv->phydev->speed) { -@@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m - mcr |= (SPEED_100M << FORCE_SPD_S); - break; - case SPEED_1000: -+ case SPEED_2500: - mcr |= (SPEED_1000M << FORCE_SPD_S); - break; - }; -@@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_ - return 0; - } - -- mtk_phy_link_adjust(priv); -+ if (!priv->force_mode) -+ mtk_phy_link_adjust(priv); - - debug("Speed: %d, %s duplex%s\n", phydev->speed, - (phydev->duplex) ? "full" : "half", -@@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice - return 0; - } - --static void mtk_sgmii_init(struct mtk_eth_priv *priv) -+static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) -+{ -+ /* Set SGMII GEN1 speed(1G) */ -+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -+ SGMSYS_SPEED_2500, 0); -+ -+ /* Enable SGMII AN */ -+ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, -+ SGMII_AN_ENABLE); -+ -+ /* SGMII AN mode setting */ -+ writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); -+ -+ /* SGMII PN SWAP setting */ -+ if (priv->pn_swap) { -+ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, -+ SGMII_PN_SWAP_TX_RX); -+ } -+ -+ /* Release PHYA power down state */ -+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, -+ SGMII_PHYA_PWD, 0); -+} -+ -+static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) - { - /* Set SGMII GEN2 speed(2.5G) */ - setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, -@@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_ - ge_mode = GE_MODE_RGMII; - break; - case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_2500BASEX: - ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); -- mtk_sgmii_init(priv); -+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) -+ mtk_sgmii_an_init(priv); -+ else -+ mtk_sgmii_force_init(priv); - break; - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_GMII: -@@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_ - mcr |= SPEED_100M << FORCE_SPD_S; - break; - case SPEED_1000: -+ case SPEED_2500: - mcr |= SPEED_1000M << FORCE_SPD_S; - break; - } -@@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude - priv->duplex = ofnode_read_bool(subnode, "full-duplex"); - - if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && -- priv->speed != SPEED_1000) { -+ priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && -+ priv->speed != SPEED_10000) { - printf("error: no valid speed set in fixed-link\n"); - return -EINVAL; - } - } - -- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) { -+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || -+ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { - /* get corresponding sgmii phandle */ - ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", - NULL, 0, 0, &args); ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -69,6 +69,7 @@ enum mkt_eth_capabilities { - #define SGMII_AN_RESTART BIT(9) - - #define SGMSYS_SGMII_MODE 0x20 -+#define SGMII_AN_MODE 0x31120103 - #define SGMII_FORCE_MODE 0x31120019 - - #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 -@@ -168,6 +169,7 @@ enum mkt_eth_capabilities { - #define FORCE_MODE BIT(15) - #define MAC_TX_EN BIT(14) - #define MAC_RX_EN BIT(13) -+#define DEL_RXFIFO_CLR BIT(12) - #define BKOFF_EN BIT(9) - #define BACKPR_EN BIT(8) - #define FORCE_RX_FC BIT(5) diff --git a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch b/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch deleted file mode 100644 index 27612fd9e4..0000000000 --- a/package/boot/uboot-mediatek/patches/101-21-arm-dts-medaitek-convert-gmac-link-mode-to-2500base-.patch +++ /dev/null @@ -1,214 +0,0 @@ -From 64ef7e977767e3b1305fb94a5169d8b7d3b19b6c Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:18 +0800 -Subject: [PATCH 21/29] arm: dts: mediatek: convert gmac link mode to - 2500base-x - -Now that individual 2.5Gbps SGMII support has been added to -mtk-eth, all boards that use 2.5Gbps link with mt7531 must be -converted to use "2500base-x" instead of "sgmii". - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> -[also convert BPi-R3] -Signed-off-by: Daniel Golle <daniel@makrotopia.org> ---- - arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 4 ++-- - arch/arm/dts/mt7622-rfb.dts | 4 ++-- - arch/arm/dts/mt7629-rfb.dts | 4 ++-- - arch/arm/dts/mt7981-emmc-rfb.dts | 4 ++-- - arch/arm/dts/mt7981-rfb.dts | 4 ++-- - arch/arm/dts/mt7981-sd-rfb.dts | 4 ++-- - arch/arm/dts/mt7986a-bpi-r3-sd.dts | 4 ++-- - arch/arm/dts/mt7986a-rfb.dts | 4 ++-- - arch/arm/dts/mt7986a-sd-rfb.dts | 4 ++-- - arch/arm/dts/mt7986b-rfb.dts | 4 ++-- - arch/arm/dts/mt7986b-sd-rfb.dts | 4 ++-- - 11 files changed, 22 insertions(+), 22 deletions(-) - ---- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts -@@ -224,12 +224,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7622-rfb.dts -+++ b/arch/arm/dts/mt7622-rfb.dts -@@ -240,12 +240,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7629-rfb.dts -+++ b/arch/arm/dts/mt7629-rfb.dts -@@ -25,12 +25,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7981-emmc-rfb.dts -+++ b/arch/arm/dts/mt7981-emmc-rfb.dts -@@ -46,12 +46,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7981-rfb.dts -+++ b/arch/arm/dts/mt7981-rfb.dts -@@ -37,12 +37,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7981-sd-rfb.dts -+++ b/arch/arm/dts/mt7981-sd-rfb.dts -@@ -46,12 +46,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts -+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts -@@ -76,12 +76,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7986a-rfb.dts -+++ b/arch/arm/dts/mt7986a-rfb.dts -@@ -55,12 +55,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7986a-sd-rfb.dts -+++ b/arch/arm/dts/mt7986a-sd-rfb.dts -@@ -47,12 +47,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7986b-rfb.dts -+++ b/arch/arm/dts/mt7986b-rfb.dts -@@ -46,12 +46,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; ---- a/arch/arm/dts/mt7986b-sd-rfb.dts -+++ b/arch/arm/dts/mt7986b-sd-rfb.dts -@@ -47,12 +47,12 @@ - ð { - status = "okay"; - mediatek,gmac-id = <0>; -- phy-mode = "sgmii"; -+ phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - - fixed-link { -- speed = <1000>; -+ speed = <2500>; - full-duplex; - }; - }; diff --git a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch b/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch deleted file mode 100644 index c7e49ff304..0000000000 --- a/package/boot/uboot-mediatek/patches/101-22-net-mediatek-add-support-for-GMAC-USB3-PHY-mux-mode-.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:22 +0800 -Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode - for MT7981 - -MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux -register must be set to connect the SGMII phy to GMAC2. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++- - drivers/net/mtk_eth.h | 16 ++++++++++++++++ - 2 files changed, 48 insertions(+), 1 deletion(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -103,6 +103,8 @@ struct mtk_eth_priv { - - struct regmap *ethsys_regmap; - -+ struct regmap *infra_regmap; -+ - struct mii_dev *mdio_bus; - int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); - int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); -@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et - regmap_write(priv->ethsys_regmap, reg, val); - } - -+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, -+ u32 set) -+{ -+ uint val; -+ -+ regmap_read(priv->infra_regmap, reg, &val); -+ val &= ~clr; -+ val |= set; -+ regmap_write(priv->infra_regmap, reg, val); -+} -+ - /* Direct MDIO clause 22/45 access via SoC */ - static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, - u32 cmd, u32 st) -@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_ - break; - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { -+ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, -+ SGMII_QPHY_SEL); -+ } -+ - ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); -@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude - if (IS_ERR(priv->ethsys_regmap)) - return PTR_ERR(priv->ethsys_regmap); - -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { -+ /* get corresponding infracfg phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", -+ NULL, 0, 0, &args); -+ -+ if (ret) -+ return ret; -+ -+ priv->infra_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->infra_regmap)) -+ return PTR_ERR(priv->infra_regmap); -+ } -+ - /* Reset controllers */ - ret = reset_get_by_name(dev, "fe", &priv->rst_fe); - if (ret) { -@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_ - }; - - static const struct mtk_soc_data mt7981_data = { -- .caps = MT7986_CAPS, -+ .caps = MT7981_CAPS, - .ana_rgc3 = 0x128, - .pdma_base = PDMA_V2_BASE, - .txd_size = sizeof(struct mtk_tx_dma_v2), ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -15,27 +15,38 @@ - enum mkt_eth_capabilities { - MTK_TRGMII_BIT, - MTK_TRGMII_MT7621_CLK_BIT, -+ MTK_U3_COPHY_V2_BIT, -+ MTK_INFRA_BIT, - MTK_NETSYS_V2_BIT, - - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_TRGMII_BIT, -+ MTK_ETH_PATH_GMAC2_SGMII_BIT, - }; - - #define MTK_TRGMII BIT(MTK_TRGMII_BIT) - #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -+#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) -+#define MTK_INFRA BIT(MTK_INFRA_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) - - /* Supported path present on SoCs */ - #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) - -+#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) -+ - #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) - -+#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) -+ - #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) - - #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) - - #define MT7623_CAPS (MTK_GMAC1_TRGMII) - -+#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) -+ - #define MT7986_CAPS (MTK_NETSYS_V2) - - /* Frame Engine Register Bases */ -@@ -56,6 +67,11 @@ enum mkt_eth_capabilities { - #define ETHSYS_CLKCFG0_REG 0x2c - #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) - -+/* Top misc registers */ -+#define USB_PHY_SWITCH_REG 0x218 -+#define QPHY_SEL_MASK 0x3 -+#define SGMII_QPHY_SEL 0x2 -+ - /* SYSCFG0_GE_MODE: GE Modes */ - #define GE_MODE_RGMII 0 - #define GE_MODE_MII 1 diff --git a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch b/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch deleted file mode 100644 index 63c25304a0..0000000000 --- a/package/boot/uboot-mediatek/patches/101-23-arm-dts-mediatek-add-infracfg-registers-to-support-G.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 64dab5fc8405005a78bdf1e0035d8b754cdf0c7e Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:27 +0800 -Subject: [PATCH 23/29] arm: dts: mediatek: add infracfg registers to support - GMAC/USB3 Co-PHY - -This patch adds infracfg to eth node to support enabling GMAC2. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/mt7981.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/dts/mt7981.dtsi -+++ b/arch/arm/dts/mt7981.dtsi -@@ -266,6 +266,7 @@ - reset-names = "fe"; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>; -+ mediatek,infracfg = <&topmisc>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -@@ -284,6 +285,12 @@ - #clock-cells = <1>; - }; - -+ topmisc: topmisc@11d10000 { -+ compatible = "mediatek,mt7981-topmisc", "syscon"; -+ reg = <0x11d10000 0x10000>; -+ #clock-cells = <1>; -+ }; -+ - spi0: spi@1100a000 { - compatible = "mediatek,ipm-spi"; - reg = <0x1100a000 0x100>; diff --git a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch b/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch deleted file mode 100644 index 67288c749e..0000000000 --- a/package/boot/uboot-mediatek/patches/101-24-net-mediatek-add-USXGMII-support.patch +++ /dev/null @@ -1,341 +0,0 @@ -From d62b483092035bc86d1db83ea4ac29bfa7bba77d Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:31 +0800 -Subject: [PATCH 24/29] net: mediatek: add USXGMII support - -This patch adds support for USXGMII of SoC. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 230 +++++++++++++++++++++++++++++++++++++++++- - drivers/net/mtk_eth.h | 24 +++++ - 2 files changed, 251 insertions(+), 3 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -105,6 +105,11 @@ struct mtk_eth_priv { - - struct regmap *infra_regmap; - -+ struct regmap *usxgmii_regmap; -+ struct regmap *xfi_pextp_regmap; -+ struct regmap *xfi_pll_regmap; -+ struct regmap *toprgu_regmap; -+ - struct mii_dev *mdio_bus; - int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); - int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); -@@ -989,6 +994,42 @@ static int mt753x_switch_init(struct mtk - return 0; - } - -+static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) -+{ -+ u16 lcl_adv = 0, rmt_adv = 0; -+ u8 flowctrl; -+ u32 mcr; -+ -+ mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); -+ mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); -+ -+ if (priv->phydev->duplex) { -+ if (priv->phydev->pause) -+ rmt_adv = LPA_PAUSE_CAP; -+ if (priv->phydev->asym_pause) -+ rmt_adv |= LPA_PAUSE_ASYM; -+ -+ if (priv->phydev->advertising & ADVERTISED_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_CAP; -+ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) -+ lcl_adv |= ADVERTISE_PAUSE_ASYM; -+ -+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); -+ -+ if (flowctrl & FLOW_CTRL_TX) -+ mcr |= XGMAC_FORCE_TX_FC; -+ if (flowctrl & FLOW_CTRL_RX) -+ mcr |= XGMAC_FORCE_RX_FC; -+ -+ debug("rx pause %s, tx pause %s\n", -+ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", -+ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); -+ } -+ -+ mcr &= ~(XGMAC_TRX_DISABLE); -+ mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); -+} -+ - static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) - { - u16 lcl_adv = 0, rmt_adv = 0; -@@ -1063,8 +1104,12 @@ static int mtk_phy_start(struct mtk_eth_ - return 0; - } - -- if (!priv->force_mode) -- mtk_phy_link_adjust(priv); -+ if (!priv->force_mode) { -+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) -+ mtk_xphy_link_adjust(priv); -+ else -+ mtk_phy_link_adjust(priv); -+ } - - debug("Speed: %d, %s duplex%s\n", phydev->speed, - (phydev->duplex) ? "full" : "half", -@@ -1140,6 +1185,112 @@ static void mtk_sgmii_force_init(struct - SGMII_PHYA_PWD, 0); - } - -+static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) -+{ -+ u32 val = 0; -+ -+ /* Add software workaround for USXGMII PLL TCL issue */ -+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, -+ RG_XFI_PLL_ANA_SWWA); -+ -+ regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); -+ val |= RG_XFI_PLL_EN; -+ regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); -+} -+ -+static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) -+{ -+ switch (priv->gmac_id) { -+ case 1: -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -+ break; -+ case 2: -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); -+ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); -+ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); -+ break; -+ } -+ -+ mdelay(10); -+} -+ -+static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) -+{ -+ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); -+ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); -+ ndelay(1020); -+ regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); -+ -+ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); -+ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); -+ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); -+ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); -+ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); -+ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); -+ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); -+ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); -+ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); -+ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); -+ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); -+ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); -+ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); -+ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); -+ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); -+ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); -+ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); -+ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); -+ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); -+ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); -+ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); -+ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); -+ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); -+ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); -+ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); -+ udelay(150); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); -+ udelay(15); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); -+ ndelay(1020); -+ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); -+ udelay(100); -+ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); -+ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); -+ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); -+ udelay(400); -+} -+ -+static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) -+{ -+ mtk_xfi_pll_enable(priv); -+ mtk_usxgmii_reset(priv); -+ mtk_usxgmii_setup_phya_an_10000(priv); -+} -+ - static void mtk_mac_init(struct mtk_eth_priv *priv) - { - int i, ge_mode = 0; -@@ -1222,6 +1373,36 @@ static void mtk_mac_init(struct mtk_eth_ - } - } - -+static void mtk_xmac_init(struct mtk_eth_priv *priv) -+{ -+ u32 sts; -+ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ mtk_usxgmii_an_init(priv); -+ break; -+ default: -+ break; -+ } -+ -+ /* Set GMAC to the correct mode */ -+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, -+ SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), -+ 0); -+ -+ if (priv->gmac_id == 1) { -+ mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, -+ NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); -+ } else if (priv->gmac_id == 2) { -+ sts = mtk_gmac_read(priv, XGMAC_STS(priv->gmac_id)); -+ sts |= XGMAC_FORCE_LINK; -+ mtk_gmac_write(priv, XGMAC_STS(priv->gmac_id), sts); -+ } -+ -+ /* Force GMAC link down */ -+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); -+} -+ - static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) - { - char *pkt_base = priv->pkt_pool; -@@ -1463,7 +1644,10 @@ static int mtk_eth_probe(struct udevice - ARCH_DMA_MINALIGN); - - /* Set MAC mode */ -- mtk_mac_init(priv); -+ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) -+ mtk_xmac_init(priv); -+ else -+ mtk_mac_init(priv); - - /* Probe phy if switch is not specified */ - if (priv->sw == SW_NONE) -@@ -1581,6 +1765,46 @@ static int mtk_eth_of_to_plat(struct ude - } - - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap"); -+ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { -+ /* get corresponding usxgmii phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->usxgmii_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->usxgmii_regmap)) -+ return PTR_ERR(priv->usxgmii_regmap); -+ -+ /* get corresponding xfi_pextp phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->xfi_pextp_regmap)) -+ return PTR_ERR(priv->xfi_pextp_regmap); -+ -+ /* get corresponding xfi_pll phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->xfi_pll_regmap)) -+ return PTR_ERR(priv->xfi_pll_regmap); -+ -+ /* get corresponding toprgu phandle */ -+ ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", -+ NULL, 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ priv->toprgu_regmap = syscon_node_to_regmap(args.node); -+ if (IS_ERR(priv->toprgu_regmap)) -+ return PTR_ERR(priv->toprgu_regmap); - } - - /* check for switch first, otherwise phy will be used */ ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -68,6 +68,11 @@ enum mkt_eth_capabilities { - #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) - - /* Top misc registers */ -+#define TOPMISC_NETSYS_PCS_MUX 0x84 -+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) -+#define MUX_G2_USXGMII_SEL BIT(1) -+#define MUX_HSGMII1_G1_SEL BIT(0) -+ - #define USB_PHY_SWITCH_REG 0x218 - #define QPHY_SEL_MASK 0x3 - #define SGMII_QPHY_SEL 0x2 -@@ -98,6 +103,15 @@ enum mkt_eth_capabilities { - #define SGMSYS_GEN2_SPEED_V2 0x128 - #define SGMSYS_SPEED_2500 BIT(2) - -+/* USXGMII subsystem config registers */ -+/* Register to control USXGMII XFI PLL digital */ -+#define XFI_PLL_DIG_GLB8 0x08 -+#define RG_XFI_PLL_EN BIT(31) -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ - /* Frame Engine Registers */ - #define FE_GLO_MISC_REG 0x124 - #define PDMA_VER_V2 BIT(4) -@@ -221,6 +235,16 @@ enum mkt_eth_capabilities { - #define TD_DM_DRVP_S 0 - #define TD_DM_DRVP_M 0x0f - -+/* XGMAC Status Registers */ -+#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) -+#define XGMAC_FORCE_LINK BIT(15) -+ -+/* XGMAC Registers */ -+#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) -+#define XGMAC_TRX_DISABLE 0xf -+#define XGMAC_FORCE_TX_FC BIT(5) -+#define XGMAC_FORCE_RX_FC BIT(4) -+ - /* MT7530 Registers */ - - #define PCR_REG(p) (0x2004 + (p) * 0x100) diff --git a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch b/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch deleted file mode 100644 index 691b59faed..0000000000 --- a/package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch +++ /dev/null @@ -1,221 +0,0 @@ -From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:37 +0800 -Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3 - -This patch adds support for NETSYS v3 hardware. -Comparing to NETSYS v2, NETSYS v3 has three GMACs. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++----------- - drivers/net/mtk_eth.h | 7 +++++++ - 2 files changed, 44 insertions(+), 12 deletions(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -76,6 +76,7 @@ enum mtk_switch { - * @caps Flags shown the extra capability for the SoC - * @ana_rgc3: The offset for register ANA_RGC3 related to - * sgmiisys syscon -+ * @gdma_count: Number of GDMAs - * @pdma_base: Register base of PDMA block - * @txd_size: Tx DMA descriptor size. - * @rxd_size: Rx DMA descriptor size. -@@ -83,6 +84,7 @@ enum mtk_switch { - struct mtk_soc_data { - u32 caps; - u32 ana_rgc3; -+ u32 gdma_count; - u32 pdma_base; - u32 txd_size; - u32 rxd_size; -@@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et - { - u32 gdma_base; - -- if (no == 1) -+ if (no == 2) -+ gdma_base = GDMA3_BASE; -+ else if (no == 1) - gdma_base = GDMA2_BASE; - else - gdma_base = GDMA1_BASE; -@@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk - txd->txd1 = virt_to_phys(pkt_base); - txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) -+ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? -+ 15 : priv->gmac_id + 1); -+ else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) - txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); - else - txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); -@@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk - - rxd->rxd1 = virt_to_phys(pkt_base); - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); - else - rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -@@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk - static int mtk_eth_start(struct udevice *dev) - { - struct mtk_eth_priv *priv = dev_get_priv(dev); -- int ret; -+ int i, ret; - - /* Reset FE */ - reset_assert(&priv->rst_fe); -@@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice - reset_deassert(&priv->rst_fe); - mdelay(10); - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); - - /* Packets forward to PDMA */ - mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); - -- if (priv->gmac_id == 0) -- mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); -- else -- mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); -+ for (i = 0; i < priv->soc->gdma_count; i++) { -+ if (i == priv->gmac_id) -+ continue; -+ -+ mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); -+ } -+ -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, -+ GDMA_CPU_BRIDGE_EN); -+ } - - udelay(500); - -@@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice * - flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + - roundup(length, ARCH_DMA_MINALIGN)); - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); - else - txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); -@@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice * - return -EAGAIN; - } - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); - else - length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); -@@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi - - rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; - -- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) -+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || -+ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) - rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); - else - rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -@@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude - static const struct mtk_soc_data mt7986_data = { - .caps = MT7986_CAPS, - .ana_rgc3 = 0x128, -+ .gdma_count = 2, - .pdma_base = PDMA_V2_BASE, - .txd_size = sizeof(struct mtk_tx_dma_v2), - .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_ - static const struct mtk_soc_data mt7981_data = { - .caps = MT7981_CAPS, - .ana_rgc3 = 0x128, -+ .gdma_count = 2, - .pdma_base = PDMA_V2_BASE, - .txd_size = sizeof(struct mtk_tx_dma_v2), - .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_ - - static const struct mtk_soc_data mt7629_data = { - .ana_rgc3 = 0x128, -+ .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_ - - static const struct mtk_soc_data mt7623_data = { - .caps = MT7623_CAPS, -+ .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_ - - static const struct mtk_soc_data mt7622_data = { - .ana_rgc3 = 0x2028, -+ .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), -@@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_ - - static const struct mtk_soc_data mt7621_data = { - .caps = MT7621_CAPS, -+ .gdma_count = 2, - .pdma_base = PDMA_V1_BASE, - .txd_size = sizeof(struct mtk_tx_dma), - .rxd_size = sizeof(struct mtk_rx_dma), ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -18,6 +18,7 @@ enum mkt_eth_capabilities { - MTK_U3_COPHY_V2_BIT, - MTK_INFRA_BIT, - MTK_NETSYS_V2_BIT, -+ MTK_NETSYS_V3_BIT, - - /* PATH BITS */ - MTK_ETH_PATH_GMAC1_TRGMII_BIT, -@@ -29,6 +30,7 @@ enum mkt_eth_capabilities { - #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) - #define MTK_INFRA BIT(MTK_INFRA_BIT) - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) -+#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) - - /* Supported path present on SoCs */ - #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -@@ -52,8 +54,10 @@ enum mkt_eth_capabilities { - /* Frame Engine Register Bases */ - #define PDMA_V1_BASE 0x0800 - #define PDMA_V2_BASE 0x6000 -+#define PDMA_V3_BASE 0x6800 - #define GDMA1_BASE 0x0500 - #define GDMA2_BASE 0x1500 -+#define GDMA3_BASE 0x0540 - #define GMAC_BASE 0x10000 - - /* Ethernet subsystem registers */ -@@ -153,6 +157,9 @@ enum mkt_eth_capabilities { - #define UN_DP_S 0 - #define UN_DP_M 0x0f - -+#define GDMA_EG_CTRL_REG 0x004 -+#define GDMA_CPU_BRIDGE_EN BIT(31) -+ - #define GDMA_MAC_LSB_REG 0x008 - - #define GDMA_MAC_MSB_REG 0x00c diff --git a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch deleted file mode 100644 index 29e8649052..0000000000 --- a/package/boot/uboot-mediatek/patches/101-26-net-mediatek-add-support-for-MediaTek-MT7988-SoC.patch +++ /dev/null @@ -1,327 +0,0 @@ -From 59dba9d87c9caf04a5d797af46699055a53870f4 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:41 +0800 -Subject: [PATCH 26/29] net: mediatek: add support for MediaTek MT7988 SoC - -This patch adds support for MediaTek MT7988. - -MT7988 features MediaTek NETSYS v3, including three GMACs, and two -of them supports 10Gbps USXGMII. - -MT7988 embeds a MT7531 switch (not MCM) which supports accessing -internal registers through MMIO instead of MDIO. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/net/mtk_eth.c | 158 +++++++++++++++++++++++++++++++++++++++++- - drivers/net/mtk_eth.h | 20 ++++++ - 2 files changed, 177 insertions(+), 1 deletion(-) - ---- a/drivers/net/mtk_eth.c -+++ b/drivers/net/mtk_eth.c -@@ -54,6 +54,16 @@ - (DP_PDMA << MC_DP_S) | \ - (DP_PDMA << UN_DP_S)) - -+#define GDMA_BRIDGE_TO_CPU \ -+ (0xC0000000 | \ -+ GDM_ICS_EN | \ -+ GDM_TCS_EN | \ -+ GDM_UCS_EN | \ -+ (DP_PDMA << MYMAC_DP_S) | \ -+ (DP_PDMA << BC_DP_S) | \ -+ (DP_PDMA << MC_DP_S) | \ -+ (DP_PDMA << UN_DP_S)) -+ - #define GDMA_FWD_DISCARD \ - (0x20000000 | \ - GDM_ICS_EN | \ -@@ -68,7 +78,8 @@ - enum mtk_switch { - SW_NONE, - SW_MT7530, -- SW_MT7531 -+ SW_MT7531, -+ SW_MT7988, - }; - - /* struct mtk_soc_data - This is the structure holding all differences -@@ -102,6 +113,7 @@ struct mtk_eth_priv { - void __iomem *fe_base; - void __iomem *gmac_base; - void __iomem *sgmii_base; -+ void __iomem *gsw_base; - - struct regmap *ethsys_regmap; - -@@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_et - writel(val, priv->fe_base + gdma_base + reg); - } - -+static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) -+{ -+ clrsetbits_le32(priv->fe_base + reg, clr, set); -+} -+ - static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) - { - return readl(priv->gmac_base + reg); -@@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth - regmap_write(priv->infra_regmap, reg, val); - } - -+static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) -+{ -+ return readl(priv->gsw_base + reg); -+} -+ -+static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -+{ -+ writel(val, priv->gsw_base + reg); -+} -+ - /* Direct MDIO clause 22/45 access via SoC */ - static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, - u32 cmd, u32 st) -@@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_et - { - int ret, low_word, high_word; - -+ if (priv->sw == SW_MT7988) { -+ *data = mtk_gsw_read(priv, reg); -+ return 0; -+ } -+ - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) -@@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_e - { - int ret; - -+ if (priv->sw == SW_MT7988) { -+ mtk_gsw_write(priv, reg, data); -+ return 0; -+ } -+ - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) -@@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udev - priv->mmd_write = mtk_mmd_ind_write; - break; - case SW_MT7531: -+ case SW_MT7988: - priv->mii_read = mt7531_mii_ind_read; - priv->mii_write = mt7531_mii_ind_write; - priv->mmd_read = mt7531_mmd_ind_read; -@@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_p - return 0; - } - -+static void mt7988_phy_setting(struct mtk_eth_priv *priv) -+{ -+ u16 val; -+ u32 i; -+ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ /* Enable HW auto downshift */ -+ priv->mii_write(priv, i, 0x1f, 0x1); -+ val = priv->mii_read(priv, i, PHY_EXT_REG_14); -+ val |= PHY_EN_DOWN_SHFIT; -+ priv->mii_write(priv, i, PHY_EXT_REG_14, val); -+ -+ /* PHY link down power saving enable */ -+ val = priv->mii_read(priv, i, PHY_EXT_REG_17); -+ val |= PHY_LINKDOWN_POWER_SAVING_EN; -+ priv->mii_write(priv, i, PHY_EXT_REG_17, val); -+ } -+} -+ -+static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) -+{ -+ u32 pmcr = FORCE_MODE_LNK; -+ -+ if (enable) -+ pmcr = priv->mt753x_pmcr; -+ -+ mt753x_reg_write(priv, PMCR_REG(6), pmcr); -+} -+ -+static int mt7988_setup(struct mtk_eth_priv *priv) -+{ -+ u16 phy_addr, phy_val; -+ u32 pmcr; -+ int i; -+ -+ priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; -+ -+ priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & -+ MT753X_SMI_ADDR_MASK; -+ -+ /* Turn off PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -+ phy_val |= BMCR_PDOWN; -+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ switch (priv->phy_interface) { -+ case PHY_INTERFACE_MODE_USXGMII: -+ /* Use CPU bridge instead of actual USXGMII path */ -+ -+ /* Set GDM1 no drop */ -+ mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); -+ -+ /* Enable GDM1 to GSW CPU bridge */ -+ mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); -+ -+ /* XGMAC force link up */ -+ mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); -+ -+ /* Setup GSW CPU bridge IPG */ -+ mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, -+ (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); -+ break; -+ default: -+ printf("Error: MT7988 GSW does not support %s interface\n", -+ phy_string_for_interface(priv->phy_interface)); -+ break; -+ } -+ -+ pmcr = MT7988_FORCE_MODE | -+ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | -+ MAC_MODE | MAC_TX_EN | MAC_RX_EN | -+ BKOFF_EN | BACKPR_EN | -+ FORCE_RX_FC | FORCE_TX_FC | -+ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | -+ FORCE_LINK; -+ -+ priv->mt753x_pmcr = pmcr; -+ -+ /* Keep MAC link down before starting eth */ -+ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); -+ -+ /* Turn on PHYs */ -+ for (i = 0; i < MT753X_NUM_PHYS; i++) { -+ phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); -+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); -+ phy_val &= ~BMCR_PDOWN; -+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); -+ } -+ -+ mt7988_phy_setting(priv); -+ -+ return 0; -+} -+ - static int mt753x_switch_init(struct mtk_eth_priv *priv) - { - int ret; -@@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice - } - - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { -+ if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { -+ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, -+ GDMA_BRIDGE_TO_CPU); -+ } -+ - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, - GDMA_CPU_BRIDGE_EN); - } -@@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct ude - priv->switch_mac_control = mt7531_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 200; -+ } else if (!strcmp(str, "mt7988")) { -+ priv->sw = SW_MT7988; -+ priv->switch_init = mt7988_setup; -+ priv->switch_mac_control = mt7988_mac_control; -+ priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; -+ priv->mt753x_reset_wait_time = 50; - } else { - printf("error: unsupported switch\n"); - return -EINVAL; -@@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct ude - return 0; - } - -+static const struct mtk_soc_data mt7988_data = { -+ .caps = MT7988_CAPS, -+ .ana_rgc3 = 0x128, -+ .gdma_count = 3, -+ .pdma_base = PDMA_V3_BASE, -+ .txd_size = sizeof(struct mtk_tx_dma_v2), -+ .rxd_size = sizeof(struct mtk_rx_dma_v2), -+}; -+ - static const struct mtk_soc_data mt7986_data = { - .caps = MT7986_CAPS, - .ana_rgc3 = 0x128, -@@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_ - }; - - static const struct udevice_id mtk_eth_ids[] = { -+ { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, - { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, - { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, - { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, ---- a/drivers/net/mtk_eth.h -+++ b/drivers/net/mtk_eth.h -@@ -51,6 +51,8 @@ enum mkt_eth_capabilities { - - #define MT7986_CAPS (MTK_NETSYS_V2) - -+#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) -+ - /* Frame Engine Register Bases */ - #define PDMA_V1_BASE 0x0800 - #define PDMA_V2_BASE 0x6000 -@@ -59,6 +61,7 @@ enum mkt_eth_capabilities { - #define GDMA2_BASE 0x1500 - #define GDMA3_BASE 0x0540 - #define GMAC_BASE 0x10000 -+#define GSW_BASE 0x20000 - - /* Ethernet subsystem registers */ - -@@ -117,6 +120,9 @@ enum mkt_eth_capabilities { - #define RG_XFI_PLL_ANA_SWWA 0x02283248 - - /* Frame Engine Registers */ -+#define PSE_NO_DROP_CFG_REG 0x108 -+#define PSE_NO_DROP_GDM1 BIT(1) -+ - #define FE_GLO_MISC_REG 0x124 - #define PDMA_VER_V2 BIT(4) - -@@ -187,6 +193,17 @@ enum mkt_eth_capabilities { - #define MDIO_RW_DATA_S 0 - #define MDIO_RW_DATA_M 0xffff - -+#define GMAC_XGMAC_STS_REG 0x000c -+#define P1_XGMAC_FORCE_LINK BIT(15) -+ -+#define GMAC_MAC_MISC_REG 0x0010 -+ -+#define GMAC_GSW_CFG_REG 0x0080 -+#define GSWTX_IPG_M 0xF0000 -+#define GSWTX_IPG_S 16 -+#define GSWRX_IPG_M 0xF -+#define GSWRX_IPG_S 0 -+ - /* MDIO_CMD: MDIO commands */ - #define MDIO_CMD_ADDR 0 - #define MDIO_CMD_WRITE 1 -@@ -285,6 +302,9 @@ enum mkt_eth_capabilities { - FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ - FORCE_MODE_DPX | FORCE_MODE_SPD | \ - FORCE_MODE_LNK -+#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ -+ FORCE_MODE_DPX | FORCE_MODE_SPD | \ -+ FORCE_MODE_LNK - - /* MT7531 SGMII Registers */ - #define MT7531_SGMII_REG_BASE 0x5000 diff --git a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch b/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch deleted file mode 100644 index 07620f77b3..0000000000 --- a/package/boot/uboot-mediatek/patches/101-27-tools-mtk_image-use-uint32_t-for-ghf-header-magic-an.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 757b997f1f5a958e6fec3d5aee1ff5cdf5766711 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:45 +0800 -Subject: [PATCH 27/29] tools: mtk_image: use uint32_t for ghf header magic and - version - -This patch converts magic and version fields of ghf common header -to one field with the type of uint32_t to make this header flexible -for futher updates. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - tools/mtk_image.c | 10 ++++++---- - tools/mtk_image.h | 6 +++--- - 2 files changed, 9 insertions(+), 7 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -542,11 +542,13 @@ static void put_brom_layout_header(struc - hdr->type = cpu_to_le32(type); - } - --static void put_ghf_common_header(struct gfh_common_header *gfh, int size, -- int type, int ver) -+static void put_ghf_common_header(struct gfh_common_header *gfh, uint16_t size, -+ uint16_t type, uint8_t ver) - { -- memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic)); -- gfh->version = ver; -+ uint32_t magic_version = GFH_HEADER_MAGIC | -+ (uint32_t)ver << GFH_HEADER_VERSION_SHIFT; -+ -+ gfh->magic_version = cpu_to_le32(magic_version); - gfh->size = cpu_to_le16(size); - gfh->type = cpu_to_le16(type); - } ---- a/tools/mtk_image.h -+++ b/tools/mtk_image.h -@@ -63,13 +63,13 @@ struct gen_device_header { - - /* BootROM header definitions */ - struct gfh_common_header { -- uint8_t magic[3]; -- uint8_t version; -+ uint32_t magic_version; - uint16_t size; - uint16_t type; - }; - --#define GFH_HEADER_MAGIC "MMM" -+#define GFH_HEADER_MAGIC 0x4D4D4D -+#define GFH_HEADER_VERSION_SHIFT 24 - - #define GFH_TYPE_FILE_INFO 0 - #define GFH_TYPE_BL_INFO 1 diff --git a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch b/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch deleted file mode 100644 index f54a028b42..0000000000 --- a/package/boot/uboot-mediatek/patches/101-28-arm-mediatek-add-support-for-MediaTek-MT7988-SoC.patch +++ /dev/null @@ -1,606 +0,0 @@ -From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:49 +0800 -Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC - -This patch adds basic support for MediaTek MT7988 SoC. -This includes files that will initialize the SoC after boot and -its device tree. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/mt7988-u-boot.dtsi | 25 ++ - arch/arm/dts/mt7988.dtsi | 391 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 13 +- - arch/arm/mach-mediatek/Makefile | 1 + - arch/arm/mach-mediatek/mt7988/Makefile | 4 + - arch/arm/mach-mediatek/mt7988/init.c | 63 +++ - arch/arm/mach-mediatek/mt7988/lowlevel_init.S | 30 ++ - 7 files changed, 526 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi - create mode 100644 arch/arm/dts/mt7988.dtsi - create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile - create mode 100644 arch/arm/mach-mediatek/mt7988/init.c - create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S - ---- /dev/null -+++ b/arch/arm/dts/mt7988-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+&system_clk { -+ bootph-all; -+}; -+ -+&spi_clk { -+ bootph-all; -+}; -+ -+&uart0 { -+ bootph-all; -+}; -+ -+&uart1 { -+ bootph-all; -+}; -+ -+&uart2 { -+ bootph-all; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7988.dtsi -@@ -0,0 +1,391 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#include <dt-bindings/interrupt-controller/irq.h> -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+#include <dt-bindings/clock/mt7988-clk.h> -+#include <dt-bindings/reset/mt7988-reset.h> -+#include <dt-bindings/gpio/gpio.h> -+ -+/ { -+ compatible = "mediatek,mt7988-rfb"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a73"; -+ reg = <0x0>; -+ mediatek,hwver = <&hwver>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a73"; -+ reg = <0x1>; -+ mediatek,hwver = <&hwver>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a73"; -+ reg = <0x2>; -+ mediatek,hwver = <&hwver>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a73"; -+ reg = <0x3>; -+ mediatek,hwver = <&hwver>; -+ }; -+ }; -+ -+ system_clk: dummy40m { -+ compatible = "fixed-clock"; -+ clock-frequency = <40000000>; -+ #clock-cells = <0>; -+ }; -+ -+ spi_clk: dummy208m { -+ compatible = "fixed-clock"; -+ clock-frequency = <208000000>; -+ #clock-cells = <0>; -+ }; -+ -+ hwver: hwver { -+ compatible = "mediatek,hwver", "syscon"; -+ reg = <0 0x8000000 0 0x1000>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupt-parent = <&gic>; -+ clock-frequency = <13000000>; -+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, -+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, -+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, -+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; -+ }; -+ -+ watchdog: watchdog@1001c000 { -+ compatible = "mediatek,mt7622-wdt", -+ "mediatek,mt6589-wdt", -+ "syscon"; -+ reg = <0 0x1001c000 0 0x1000>; -+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; -+ #reset-cells = <1>; -+ }; -+ -+ gic: interrupt-controller@c000000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-parent = <&gic>; -+ interrupt-controller; -+ reg = <0 0x0c000000 0 0x40000>, /* GICD */ -+ <0 0x0c080000 0 0x200000>; /* GICR */ -+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ infracfg_ao_cgs: infracfg_ao_cgs@10001000 { -+ compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon"; -+ reg = <0 0x10001000 0 0x1000>; -+ clock-parent = <&infracfg_ao>; -+ #clock-cells = <1>; -+ }; -+ -+ apmixedsys: apmixedsys@1001e000 { -+ compatible = "mediatek,mt7988-fixed-plls", "syscon"; -+ reg = <0 0x1001e000 0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ -+ topckgen: topckgen@1001b000 { -+ compatible = "mediatek,mt7988-topckgen", "syscon"; -+ reg = <0 0x1001b000 0 0x1000>; -+ clock-parent = <&apmixedsys>; -+ #clock-cells = <1>; -+ }; -+ -+ pinctrl: pinctrl@1001f000 { -+ compatible = "mediatek,mt7988-pinctrl"; -+ reg = <0 0x1001f000 0 0x1000>, -+ <0 0x11c10000 0 0x1000>, -+ <0 0x11d00000 0 0x1000>, -+ <0 0x11d20000 0 0x1000>, -+ <0 0x11e00000 0 0x1000>, -+ <0 0x11f00000 0 0x1000>, -+ <0 0x1000b000 0 0x1000>; -+ reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", -+ "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -+ "eint"; -+ gpio: gpio-controller { -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ }; -+ -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7988-sgmiisys_0", "syscon"; -+ reg = <0 0x10060000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7988-sgmiisys_1", "syscon"; -+ reg = <0 0x10070000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ usxgmiisys0: syscon@10080000 { -+ compatible = "mediatek,mt7988-usxgmiisys_0", "syscon"; -+ reg = <0 0x10080000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ usxgmiisys1: syscon@10081000 { -+ compatible = "mediatek,mt7988-usxgmiisys_1", "syscon"; -+ reg = <0 0x10081000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ xfi_pextp0: syscon@11f20000 { -+ compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; -+ reg = <0 0x11f20000 0 0x10000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ xfi_pextp1: syscon@11f30000 { -+ compatible = "mediatek,mt7988-xfi_pextp_1", "syscon"; -+ reg = <0 0x11f30000 0 0x10000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ xfi_pll: syscon@11f40000 { -+ compatible = "mediatek,mt7988-xfi_pll", "syscon"; -+ reg = <0 0x11f40000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ topmisc: topmisc@11d10000 { -+ compatible = "mediatek,mt7988-topmisc", "syscon", -+ "mediatek,mt7988-power-controller"; -+ reg = <0 0x11d10000 0 0x10000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ infracfg_ao: infracfg@10001000 { -+ compatible = "mediatek,mt7988-infracfg", "syscon"; -+ reg = <0 0x10001000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ }; -+ -+ uart0: serial@11000000 { -+ compatible = "mediatek,hsuart"; -+ reg = <0 0x11000000 0 0x100>; -+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_MUX_UART0_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg_ao CK_INFRA_UART_O0>; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@11000100 { -+ compatible = "mediatek,hsuart"; -+ reg = <0 0x11000100 0 0x100>; -+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_MUX_UART1_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg_ao CK_INFRA_UART_O1>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@11000200 { -+ compatible = "mediatek,hsuart"; -+ reg = <0 0x11000200 0 0x100>; -+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>; -+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, -+ <&infracfg_ao CK_INFRA_MUX_UART2_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, -+ <&infracfg_ao CK_INFRA_UART_O2>; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@11003000 { -+ compatible = "mediatek,mt7988-i2c", -+ "mediatek,mt7981-i2c"; -+ reg = <0 0x11003000 0 0x1000>, -+ <0 0x10217080 0 0x80>; -+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; -+ clock-div = <1>; -+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, -+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@11004000 { -+ compatible = "mediatek,mt7988-i2c", -+ "mediatek,mt7981-i2c"; -+ reg = <0 0x11004000 0 0x1000>, -+ <0 0x10217100 0 0x80>; -+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; -+ clock-div = <1>; -+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, -+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@11005000 { -+ compatible = "mediatek,mt7988-i2c", -+ "mediatek,mt7981-i2c"; -+ reg = <0 0x11005000 0 0x1000>, -+ <0 0x10217180 0 0x80>; -+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; -+ clock-div = <1>; -+ clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, -+ <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7988-pwm"; -+ reg = <0 0x10048000 0 0x1000>; -+ #pwm-cells = <2>; -+ clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>, -+ <&infracfg_ao CK_INFRA_66M_PWM_HCK>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK1>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK2>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK3>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK4>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK5>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK6>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK7>, -+ <&infracfg_ao CK_INFRA_66M_PWM_CK8>; -+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", -+ "pwm4","pwm5","pwm6","pwm7","pwm8"; -+ status = "disabled"; -+ }; -+ -+ snand: snand@11001000 { -+ compatible = "mediatek,mt7988-snand", -+ "mediatek,mt7986-snand"; -+ reg = <0 0x11001000 0 0x1000>, -+ <0 0x11002000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&infracfg_ao CK_INFRA_SPINFI>, -+ <&infracfg_ao CK_INFRA_NFI>, -+ <&infracfg_ao CK_INFRA_66M_NFI_HCK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, -+ <&topckgen CK_TOP_NFI1X_SEL>; -+ assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, -+ <&topckgen CK_TOP_CB_M_D8>; -+ status = "disabled"; -+ }; -+ -+ spi0: spi@1100a000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0 0x11007000 0 0x100>; -+ clocks = <&spi_clk>, -+ <&spi_clk>; -+ clock-names = "sel-clk", "spi-clk"; -+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0 0x11008000 0 0x100>; -+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ spi2: spi@11009000 { -+ compatible = "mediatek,ipm-spi"; -+ reg = <0 0x11009000 0 0x100>; -+ clocks = <&spi_clk>, -+ <&spi_clk>; -+ clock-names = "sel-clk", "spi-clk"; -+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7988-mmc", -+ "mediatek,mt7986-mmc"; -+ reg = <0 0x11230000 0 0x1000>; -+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>, -+ <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>, -+ <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>, -+ <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>; -+ clock-names = "source", "hclk", "source_cg", "axi_cg"; -+ status = "disabled"; -+ }; -+ -+ ethdma: syscon@15000000 { -+ compatible = "mediatek,mt7988-ethdma", "syscon"; -+ reg = <0 0x15000000 0 0x20000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ ethwarp: syscon@15031000 { -+ compatible = "mediatek,mt7988-ethwarp", "syscon"; -+ reg = <0 0x15031000 0 0x1000>; -+ clock-parent = <&topckgen>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ eth: ethernet@15100000 { -+ compatible = "mediatek,mt7988-eth", "syscon"; -+ reg = <0 0x15100000 0 0x20000>; -+ mediatek,ethsys = <ðdma>; -+ mediatek,sgmiisys = <&sgmiisys0>; -+ mediatek,usxgmiisys = <&usxgmiisys0>; -+ mediatek,xfi_pextp = <&xfi_pextp0>; -+ mediatek,xfi_pll = <&xfi_pll>; -+ mediatek,infracfg = <&topmisc>; -+ mediatek,toprgu = <&watchdog>; -+ resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>; -+ reset-names = "fe", "mcm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mediatek,mcm; -+ status = "disabled"; -+ }; -+}; ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -58,6 +58,15 @@ config TARGET_MT7986 - including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, - Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. - -+config TARGET_MT7988 -+ bool "MediaTek MT7988 SoC" -+ select ARM64 -+ select CPU -+ help -+ The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73. -+ including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, -+ 10 Gigabit Ethernet , I2C, and PCIe. -+ - config TARGET_MT8183 - bool "MediaTek MT8183 SoC" - select ARM64 -@@ -104,6 +113,7 @@ config SYS_BOARD - default "mt7629" if TARGET_MT7629 - default "mt7981" if TARGET_MT7981 - default "mt7986" if TARGET_MT7986 -+ default "mt7988" if TARGET_MT7988 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 - default "mt8516" if TARGET_MT8516 -@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME - default "mt7629" if TARGET_MT7629 - default "mt7981" if TARGET_MT7981 - default "mt7986" if TARGET_MT7986 -+ default "mt7988" if TARGET_MT7988 - default "mt8183" if TARGET_MT8183 - default "mt8512" if TARGET_MT8512 - default "mt8516" if TARGET_MT8516 -@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO - string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 -- default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 -+ default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 - default "lk=1" if TARGET_MT7623 - - source "board/mediatek/mt7629/Kconfig" ---- a/arch/arm/mach-mediatek/Makefile -+++ b/arch/arm/mach-mediatek/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/ - obj-$(CONFIG_TARGET_MT7629) += mt7629/ - obj-$(CONFIG_TARGET_MT7981) += mt7981/ - obj-$(CONFIG_TARGET_MT7986) += mt7986/ -+obj-$(CONFIG_TARGET_MT7988) += mt7988/ - obj-$(CONFIG_TARGET_MT8183) += mt8183/ - obj-$(CONFIG_TARGET_MT8516) += mt8516/ - obj-$(CONFIG_TARGET_MT8518) += mt8518/ ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7988/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += init.o -+obj-y += lowlevel_init.o ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7988/init.c -@@ -0,0 +1,63 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#include <fdtdec.h> -+#include <init.h> -+#include <asm/armv8/mmu.h> -+#include <asm/global_data.h> -+#include <asm/u-boot.h> -+#include <asm/system.h> -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define SZ_8G _AC(0x200000000, ULL) -+ -+int dram_init(void) -+{ -+ int ret; -+ -+ ret = fdtdec_setup_mem_size_base(); -+ if (ret) -+ return ret; -+ -+ gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G); -+ -+ return 0; -+} -+ -+int dram_init_banksize(void) -+{ -+ gd->bd->bi_dram[0].start = gd->ram_base; -+ gd->bd->bi_dram[0].size = gd->ram_size; -+ -+ return 0; -+} -+ -+void reset_cpu(ulong addr) -+{ -+ psci_system_reset(); -+} -+ -+static struct mm_region mt7988_mem_map[] = { -+ { -+ /* DDR */ -+ .virt = 0x40000000UL, -+ .phys = 0x40000000UL, -+ .size = 0x200000000ULL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, -+ }, { -+ .virt = 0x00000000UL, -+ .phys = 0x00000000UL, -+ .size = 0x40000000UL, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ 0, -+ } -+}; -+ -+struct mm_region *mem_map = mt7988_mem_map; ---- /dev/null -+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S -@@ -0,0 +1,30 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+/* -+ * Switch from AArch64 EL2 to AArch32 EL2 -+ * @param inputs: -+ * x0: argument, zero -+ * x1: machine nr -+ * x2: fdt address -+ * x3: input argument -+ * x4: kernel entry point -+ * @param outputs for secure firmware: -+ * x0: function id -+ * x1: kernel entry point -+ * x2: machine nr -+ * x3: fdt address -+*/ -+ -+.global armv8_el2_to_aarch32 -+armv8_el2_to_aarch32: -+ mov x3, x2 -+ mov x2, x1 -+ mov x1, x4 -+ mov x4, #0 -+ ldr x0, =0x82000200 -+ SMC #0 -+ ret diff --git a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch b/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch deleted file mode 100644 index ef41f4d56a..0000000000 --- a/package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch +++ /dev/null @@ -1,575 +0,0 @@ -From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 19 Jul 2023 17:17:54 +0800 -Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards - -This patch adds general board files based on MT7988 SoCs. - -MT7988 uses one mmc controller for booting from both SD and eMMC, -and the pins of mmc controller booting from SD are also shared with -one of spi controllers. -So two configs are need for these boot types: - -1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC -2. mt7988_sd_rfb_defconfig - SPI-NAND and SD - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/Makefile | 2 + - arch/arm/dts/mt7988-rfb.dts | 182 +++++++++++++++++++++++++++++ - arch/arm/dts/mt7988-sd-rfb.dts | 134 +++++++++++++++++++++ - board/mediatek/mt7988/MAINTAINERS | 7 ++ - board/mediatek/mt7988/Makefile | 3 + - board/mediatek/mt7988/mt7988_rfb.c | 10 ++ - configs/mt7988_rfb_defconfig | 83 +++++++++++++ - configs/mt7988_sd_rfb_defconfig | 71 +++++++++++ - include/configs/mt7988.h | 14 +++ - 9 files changed, 506 insertions(+) - create mode 100644 arch/arm/dts/mt7988-rfb.dts - create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts - create mode 100644 board/mediatek/mt7988/MAINTAINERS - create mode 100644 board/mediatek/mt7988/Makefile - create mode 100644 board/mediatek/mt7988/mt7988_rfb.c - create mode 100644 configs/mt7988_rfb_defconfig - create mode 100644 configs/mt7988_sd_rfb_defconfig - create mode 100644 include/configs/mt7988.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt7986b-sd-rfb.dtb \ - mt7986a-emmc-rfb.dtb \ - mt7986b-emmc-rfb.dtb \ -+ mt7988-rfb.dtb \ -+ mt7988-sd-rfb.dtb \ - mt8183-pumpkin.dtb \ - mt8512-bm1-emmc.dtb \ - mt8516-pumpkin.dtb \ ---- /dev/null -+++ b/arch/arm/dts/mt7988-rfb.dts -@@ -0,0 +1,182 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+/dts-v1/; -+#include "mt7988.dtsi" -+#include <dt-bindings/gpio/gpio.h> -+ -+/ { -+ model = "mt7988-rfb"; -+ compatible = "mediatek,mt7988-rfb"; -+ -+ chosen { -+ stdout-path = &uart0; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0 0x40000000 0 0x10000000>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "usxgmii"; -+ mediatek,switch = "mt7988"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+}; -+ -+&pinctrl { -+ i2c1_pins: i2c1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ pwm_pins: pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", -+ "pwm5", "pwm6", "pwm7"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spi2_pins: spi2-pins { -+ mux { -+ function = "spi"; -+ groups = "spi2", "spi2_wp_hold"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0default { -+ mux { -+ function = "flash"; -+ groups = "emmc_51"; -+ }; -+ -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ }; -+ -+ conf-clk { -+ pins = "EMMC_CK"; -+ }; -+ -+ conf-dsl { -+ pins = "EMMC_DSL"; -+ }; -+ -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ }; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&spi2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nor@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ max-frequency = <52000000>; -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ cap-mmc-hw-reset; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/mt7988-sd-rfb.dts -@@ -0,0 +1,134 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+/dts-v1/; -+#include "mt7988.dtsi" -+#include <dt-bindings/gpio/gpio.h> -+ -+/ { -+ model = "mt7988-rfb"; -+ compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb"; -+ -+ chosen { -+ stdout-path = &uart0; -+ }; -+ -+ memory@40000000 { -+ device_type = "memory"; -+ reg = <0 0x40000000 0 0x10000000>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ mediatek,gmac-id = <0>; -+ phy-mode = "usxgmii"; -+ mediatek,switch = "mt7988"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+}; -+ -+&pinctrl { -+ i2c1_pins: i2c1-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c1_0"; -+ }; -+ }; -+ -+ pwm_pins: pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", -+ "pwm5", "pwm6", "pwm7"; -+ }; -+ }; -+ -+ spi0_pins: spi0-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ mmc1_pins_default: mmc1default { -+ mux { -+ function = "flash"; -+ groups = "emmc_45"; -+ }; -+ -+ conf-cmd-dat { -+ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", -+ "SPI2_CLK", "SPI2_HOLD"; -+ input-enable; -+ }; -+ -+ conf-clk { -+ pins = "SPI2_WP"; -+ }; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ must_tx; -+ enhance_timing; -+ dma_ext; -+ ipm_design; -+ support_quad; -+ tick_dly = <2>; -+ sample_sel = <0>; -+ -+ spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <52000000>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins_default>; -+ max-frequency = <52000000>; -+ bus-width = <4>; -+ cap-sd-highspeed; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/board/mediatek/mt7988/MAINTAINERS -@@ -0,0 +1,7 @@ -+MT7988 -+M: Sam Shih <sam.shih@mediatek.com> -+S: Maintained -+F: board/mediatek/mt7988 -+F: include/configs/mt7988.h -+F: configs/mt7988_rfb_defconfig -+F: configs/mt7988_sd_rfb_defconfig ---- /dev/null -+++ b/board/mediatek/mt7988/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+obj-y += mt7988_rfb.o ---- /dev/null -+++ b/board/mediatek/mt7988/mt7988_rfb.c -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+int board_init(void) -+{ -+ return 0; -+} ---- /dev/null -+++ b/configs/mt7988_rfb_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" -+CONFIG_SYS_PROMPT="MT7988> " -+CONFIG_TARGET_MT7988=y -+CONFIG_DEBUG_UART_BASE=0x11000000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_DOS_PARTITION=y -+CONFIG_EFI_PARTITION=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_NETMASK=y -+CONFIG_NETMASK="255.255.255.0" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.2" -+CONFIG_PROT_TCP=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MTD=y -+CONFIG_DM_MTD=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_ISSI=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_PHY_FIXED=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPIM=y -+CONFIG_LZO=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/configs/mt7988_sd_rfb_defconfig -@@ -0,0 +1,71 @@ -+CONFIG_ARM=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_POSITION_INDEPENDENT=y -+CONFIG_ARCH_MEDIATEK=y -+CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb" -+CONFIG_SYS_PROMPT="MT7988> " -+CONFIG_TARGET_MT7988=y -+CONFIG_DEBUG_UART_BASE=0x11000000 -+CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 -+CONFIG_DEBUG_UART=y -+# CONFIG_AUTOBOOT is not set -+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_CMD_ELF is not set -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_SMC=y -+CONFIG_DOS_PARTITION=y -+CONFIG_EFI_PARTITION=y -+CONFIG_PARTITION_TYPE_GUID=y -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_NETMASK=y -+CONFIG_NETMASK="255.255.255.0" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.2" -+CONFIG_PROT_TCP=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MTD=y -+CONFIG_DM_MTD=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_PHY_FIXED=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPIM=y -+CONFIG_LZO=y -+CONFIG_HEXDUMP=y -+# CONFIG_EFI_LOADER is not set ---- /dev/null -+++ b/include/configs/mt7988.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Configuration for MediaTek MT7988 SoC -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Sam Shih <sam.shih@mediatek.com> -+ */ -+ -+#ifndef __MT7988_H -+#define __MT7988_H -+ -+#define CFG_MAX_MEM_MAPPED 0xC0000000 -+ -+#endif diff --git a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch b/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch deleted file mode 100644 index 3cfc684956..0000000000 --- a/package/boot/uboot-mediatek/patches/102-ram-mediatek-include-linux-sizes.h-for-SZ_-macros.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7 Mon Sep 17 00:00:00 2001 -Message-ID: <4bd66fd5b69eda41b4320fd6f8db50a7b7fa7bf7.1690828424.git.daniel@makrotopia.org> -From: Daniel Golle <daniel@makrotopia.org> -Date: Mon, 31 Jul 2023 19:25:04 +0100 -Subject: [PATCH] ram: mediatek: include <linux/sizes.h> for SZ_* macros -To: Ryder Lee <ryder.lee@mediatek.com>, - Weijie Gao <weijie.gao@mediatek.com>, - Chunfeng Yun <chunfeng.yun@mediatek.com>, - GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>, - u-boot@lists.denx.de - -Something between U-Boot 2023.04 and 2023.07.02 resulted in no longer -implicitely including <linux/sizes.h> in the DDR3 RAM driver for the -MT7929 SoC. The result is a build failure: -drivers/ram/mediatek/ddr3-mt7629.c: In function 'mtk_ddr3_get_info': -drivers/ram/mediatek/ddr3-mt7629.c:734:30: error: 'SZ_128M' undeclared (first use in this function) - 734 | info->size = SZ_128M; - | ^~~~~~~ -drivers/ram/mediatek/ddr3-mt7629.c:734:30: note: each undeclared identifier is reported only once for each function it appears in -drivers/ram/mediatek/ddr3-mt7629.c:737:30: error: 'SZ_256M' undeclared (first use in this function) - 737 | info->size = SZ_256M; - | ^~~~~~~ -drivers/ram/mediatek/ddr3-mt7629.c:740:30: error: 'SZ_512M' undeclared (first use in this function) - 740 | info->size = SZ_512M; - | ^~~~~~~ -drivers/ram/mediatek/ddr3-mt7629.c:743:30: error: 'SZ_1G' undeclared (first use in this function) - 743 | info->size = SZ_1G; - | ^~~~~ - -Include <linux/sizes.h> so SZ_* is defined. - -Reported-by: Tianling Shen <cnsztl@immortalwrt.org> -Signed-off-by: Daniel Golle <daniel@makrotopia.org> ---- - drivers/ram/mediatek/ddr3-mt7629.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/ram/mediatek/ddr3-mt7629.c -+++ b/drivers/ram/mediatek/ddr3-mt7629.c -@@ -14,6 +14,7 @@ - #include <asm/io.h> - #include <linux/bitops.h> - #include <linux/delay.h> -+#include <linux/sizes.h> - - /* EMI */ - #define EMI_CONA 0x000 diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch index a34dcddd71..747aa2e5da 100644 --- a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi -@@ -61,6 +61,30 @@ +@@ -62,6 +62,30 @@ #clock-cells = <0>; }; diff --git a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch b/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch deleted file mode 100644 index f047518852..0000000000 --- a/package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch +++ /dev/null @@ -1,69 +0,0 @@ -From patchwork Mon Aug 21 19:38:23 2023 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org> -X-Patchwork-Id: 1823742 -X-Patchwork-Delegate: trini@ti.com -Return-Path: <u-boot-bounces@lists.denx.de> -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@legolas.ozlabs.org -Date: Mon, 21 Aug 2023 20:38:23 +0100 -From: Daniel Golle <daniel@makrotopia.org> -To: Sam Shih <sam.shih@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>, - Lorenzo Bianconi <lorenzo@kernel.org>, u-boot@lists.denx.de -Subject: [PATCH] configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards -Message-ID: - <568a8030acf9056266b5c96055cea54f810496c9.1692646620.git.daniel@makrotopia.org> -MIME-Version: 1.0 -Content-Disposition: inline -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.39 -Precedence: list -List-Id: U-Boot discussion <u-boot.lists.denx.de> -List-Unsubscribe: <https://lists.denx.de/options/u-boot>, - <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> -List-Archive: <https://lists.denx.de/pipermail/u-boot/> -List-Post: <mailto:u-boot@lists.denx.de> -List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> -List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, - <mailto:u-boot-request@lists.denx.de?subject=subscribe> -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" <u-boot-bounces@lists.denx.de> - -Similar to MT7981 and MT7986 also MT7988 can have a high number of -reserved-memory regions used by the various hardware offloading -subsystems. - -Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot -Linux with more then 6 reserved regions: - -ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4) -ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4) -ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4) -ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4) -ERROR: Failed to allocate 0xb161 bytes below 0x80000000. -device tree - allocation error - -Fixes: bc4adc97cfb ("board: mediatek: add MT7988 reference boards") -Reported-by: Lorenzo Bianconi <lorenzo@kernel.org> -Signed-off-by: Daniel Golle <daniel@makrotopia.org> ---- - configs/mt7988_rfb_defconfig | 1 + - configs/mt7988_sd_rfb_defconfig | 1 + - 2 files changed, 2 insertions(+) - ---- a/configs/mt7988_rfb_defconfig -+++ b/configs/mt7988_rfb_defconfig -@@ -81,3 +81,4 @@ CONFIG_MTK_SPIM=y - CONFIG_LZO=y - CONFIG_HEXDUMP=y - # CONFIG_EFI_LOADER is not set -+CONFIG_LMB_MAX_REGIONS=64 ---- a/configs/mt7988_sd_rfb_defconfig -+++ b/configs/mt7988_sd_rfb_defconfig -@@ -69,3 +69,4 @@ CONFIG_MTK_SPIM=y - CONFIG_LZO=y - CONFIG_HEXDUMP=y - # CONFIG_EFI_LOADER is not set -+CONFIG_LMB_MAX_REGIONS=64 diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch index c7dcf9a1ba..da1d985688 100644 --- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch +++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch @@ -1,8 +1,8 @@ --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig -@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 +@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_PRODUCT_NAME="" @@ -157,9 +157,9 @@ CONFIG_MTD=y --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig -@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 +@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x50000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_PRODUCT_NAME="" diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch index f5234ea085..bd4c6b55f0 100644 --- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch +++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch @@ -1,6 +1,6 @@ --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig -@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y @@ -87,7 +87,7 @@ CONFIG_CLK=y --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig -@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y @@ -191,7 +191,7 @@ CONFIG_MTD_SPI_NAND=y --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig -@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch index 2d61d6f4a7..3bf033f814 100644 --- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch +++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch @@ -5,6 +5,6 @@ imx8image.o \ imx8mimage.o \ - kwbimage.o \ - lib/md5.o \ + generated/lib/md5.o \ lpc32xximage.o \ mxsimage.o \ diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch index 411f99467b..9a9224963d 100644 --- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch +++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -1070,7 +1070,7 @@ quiet_cmd_pad_cat = CAT $@ +@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; } quiet_cmd_lzma = LZMA $@ diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch index cd65c1321f..86a424e8b7 100644 --- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch +++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d +@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1178,6 +1179,13 @@ err_cert: +@@ -1190,6 +1191,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch b/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch deleted file mode 100644 index c4e0fff921..0000000000 --- a/package/boot/uboot-mediatek/patches/131-spi-mtk_spim-prevent-global-pll-clock-override.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 41f225dae30ea6ddcff10f120a9e732f994d3a07 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= <nicveronese@gmail.com> -Date: Tue, 3 Oct 2023 23:46:52 +0200 -Subject: [PATCH] spi: mtk_spim: prevent global pll clock override -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -With commit 793e6230118032a099ec42a1ea67f434721edcc0 - a new system to calculate the SPI clocks has been added. - -Unfortunately, the do_div macro overrides the global - priv->pll_clk_rate field. This will cause to have a reduced - clock rate on each subsequent SPI call. - -Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu> -Signed-off-by: Nicolò Veronese <nicveronese@gmail.com> ---- - drivers/spi/mtk_spim.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/drivers/spi/mtk_spim.c -+++ b/drivers/spi/mtk_spim.c -@@ -409,7 +409,7 @@ static int mtk_spim_transfer_wait(struct - { - struct udevice *bus = dev_get_parent(slave->dev); - struct mtk_spim_priv *priv = dev_get_priv(bus); -- u32 sck_l, sck_h, clk_count, reg; -+ u32 pll_clk, sck_l, sck_h, clk_count, reg; - ulong us = 1; - int ret = 0; - -@@ -418,11 +418,12 @@ static int mtk_spim_transfer_wait(struct - else - clk_count = op->data.nbytes; - -+ pll_clk = priv->pll_clk_rate; - sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET; - sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK; -- do_div(priv->pll_clk_rate, sck_l + sck_h + 2); -+ do_div(pll_clk, sck_l + sck_h + 2); - -- us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8); -+ us = CLK_TO_US(pll_clk, clk_count * 8); - us += 1000 * 1000; /* 1s tolerance */ - - if (us > UINT_MAX) diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index ae7623086e..28175e02e8 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -1,6 +1,6 @@ --- a/cmd/bootm.c +++ b/cmd/bootm.c -@@ -259,6 +259,67 @@ U_BOOT_CMD( +@@ -245,6 +245,67 @@ U_BOOT_CMD( /* iminfo - print header info for a requested image */ /*******************************************************************/ #if defined(CONFIG_CMD_IMI) @@ -120,7 +120,7 @@ int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -1047,6 +1047,7 @@ int fit_parse_subimage(const char *spec, +@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index d91b9904cb..7bf87ef7b5 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -602,6 +602,12 @@ config CMD_ENV_EXISTS +@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. @@ -15,7 +15,7 @@ help --- a/cmd/nvedit.c +++ b/cmd/nvedit.c -@@ -408,6 +408,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in +@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in } #endif @@ -76,7 +76,7 @@ #if defined(CONFIG_CMD_ENV_CALLBACK) static int print_static_binding(const char *var_name, const char *callback_name, void *priv) -@@ -1228,6 +1282,9 @@ static struct cmd_tbl cmd_env_sub[] = { +@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = { U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""), #endif U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), @@ -86,7 +86,7 @@ #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -@@ -1319,6 +1376,9 @@ static char env_help_text[] = +@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env, #if defined(CONFIG_CMD_NVEDIT_EFI) "env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n" #endif @@ -96,7 +96,7 @@ #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -@@ -1428,6 +1488,17 @@ U_BOOT_CMD( +@@ -1392,6 +1452,17 @@ U_BOOT_CMD( ); #endif diff --git a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch index d0abcb1acc..48556937bd 100644 --- a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch +++ b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch @@ -67,7 +67,7 @@ U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""), U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""), }; -@@ -560,6 +613,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore, +@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore, " 'pmsg-size' is the size of the user space logs record.\n" " 'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n" " bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n" diff --git a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch index ec9fa6f3a0..fd5fdd814b 100644 --- a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch +++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch @@ -1,8 +1,6 @@ -diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c -index a6f93380dd0..5c573fe5c4c 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c -@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) +@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_ u32 start_rem, blkcnt_rem, erase_args = 0; struct mmc *mmc = find_mmc_device(dev_num); lbaint_t blk = 0, blk_r = 0; diff --git a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch index f6654731cb..28d7e0a3f6 100644 --- a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch +++ b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch @@ -1,6 +1,6 @@ --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c -@@ -11,6 +11,8 @@ +@@ -11,7 +11,9 @@ #include <env.h> #include <init.h> #include <asm/global_data.h> @@ -9,7 +9,8 @@ +#include <linux/libfdt.h> #ifndef CONFIG_RESET_BUTTON_LABEL -@@ -44,3 +50,54 @@ int board_late_init(void) + #define CONFIG_RESET_BUTTON_LABEL "reset" +@@ -44,3 +46,54 @@ int board_late_init(void) env_relocate(); return 0; } diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch index 7ebe5c0fc7..ca011aeca9 100644 --- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch @@ -1,6 +1,6 @@ --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig -@@ -7,35 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 +@@ -7,34 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 @@ -8,13 +8,10 @@ +CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" --CONFIG_SYS_PROMPT="U-Boot> " -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_SYS_PROMPT="MT7623> " CONFIG_TARGET_MT7623=y CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_FIT=y --CONFIG_FIT_VERBOSE=y + CONFIG_FIT_VERBOSE=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y @@ -38,6 +35,9 @@ +CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_CMD_ENV_FLAGS=y # CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_SYS_PROMPT="U-Boot> " ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_SYS_PROMPT="MT7623> " CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -70,7 +70,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_READ=y -# CONFIG_CMD_SETEXPR is not set - # CONFIG_CMD_NFS is not set +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y @@ -111,7 +110,7 @@ CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y -@@ -47,6 +117,12 @@ CONFIG_CLK=y +@@ -46,6 +117,12 @@ CONFIG_CLK=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y @@ -124,7 +123,7 @@ CONFIG_PHY_FIXED=y CONFIG_MEDIATEK_ETH=y CONFIG_PINCTRL=y -@@ -56,10 +132,13 @@ CONFIG_POWER_DOMAIN=y +@@ -55,10 +132,13 @@ CONFIG_POWER_DOMAIN=y CONFIG_MTK_POWER_DOMAIN=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch index 453456c94f..6528b165f5 100644 --- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch @@ -1,6 +1,6 @@ --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig -@@ -7,34 +7,110 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 +@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 @@ -8,13 +8,10 @@ +CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" --CONFIG_SYS_PROMPT="U-Boot> " -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_SYS_PROMPT="MT7623> " CONFIG_TARGET_MT7623=y CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_FIT=y --CONFIG_FIT_VERBOSE=y + CONFIG_FIT_VERBOSE=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y @@ -38,6 +35,9 @@ +CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_CMD_ENV_FLAGS=y # CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_SYS_PROMPT="U-Boot> " ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_SYS_PROMPT="MT7623> " CONFIG_SYS_MAXARGS=8 CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -71,7 +71,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_READ=y -# CONFIG_CMD_SETEXPR is not set - # CONFIG_CMD_NFS is not set +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y @@ -110,13 +109,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y -@@ -46,6 +122,11 @@ CONFIG_CLK=y +@@ -45,6 +121,11 @@ CONFIG_CLK=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y @@ -128,7 +126,7 @@ CONFIG_PHY_FIXED=y CONFIG_MEDIATEK_ETH=y CONFIG_PINCTRL=y -@@ -55,9 +136,12 @@ CONFIG_POWER_DOMAIN=y +@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y CONFIG_MTK_POWER_DOMAIN=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index 363509efc1..359fddf103 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -344,7 +344,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1305,6 +1305,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index aad6c53b9b..bbd05fe41f 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -841,7 +841,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1306,6 +1306,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1423,6 +1423,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ @@ -1019,7 +1019,7 @@ DECLARE_GLOBAL_DATA_PTR; -@@ -412,6 +413,20 @@ static int initr_onenand(void) +@@ -397,6 +398,20 @@ static int initr_onenand(void) } #endif @@ -1040,7 +1040,7 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -713,6 +728,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -692,6 +707,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_NMBM_MTD initr_nmbm, #endif diff --git a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch index 3cd4d1b2df..4ee87ce3d2 100644 --- a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch +++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch @@ -22,7 +22,7 @@ Subject: [PATCH] add support for RAVPower RP-WD009 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile -@@ -25,6 +25,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m +@@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb |