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| author | Lech Perczak <lech.perczak@gmail.com> | 2023-12-12 00:22:04 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2024-01-02 21:56:52 +0100 |
| commit | c5a399f372535886582f89f3da624ae7465c8ff4 (patch) | |
| tree | ac344c3f9e530f964ab68ea0de20280085702f8e | |
| parent | 8d75b1de0ff7b9e9e0138f822a5475bb8ad7fedf (diff) | |
| download | openwrt-c5a399f372535886582f89f3da624ae7465c8ff4.tar.gz openwrt-c5a399f372535886582f89f3da624ae7465c8ff4.tar.bz2 openwrt-c5a399f372535886582f89f3da624ae7465c8ff4.zip | |
ramips: dts: rt3050: reset FE and ESW cores together
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
| -rw-r--r-- | target/linux/ramips/dts/rt3050.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ramips/dts/rt3050.dtsi b/target/linux/ramips/dts/rt3050.dtsi index 4d70773ed1..d23303964f 100644 --- a/target/linux/ramips/dts/rt3050.dtsi +++ b/target/linux/ramips/dts/rt3050.dtsi @@ -301,8 +301,8 @@ clocks = <&sysc 11>; - resets = <&sysc 21>; - reset-names = "fe"; + resets = <&sysc 21>, <&sysc 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -314,8 +314,8 @@ compatible = "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&sysc 23>, <&sysc 24>; - reset-names = "esw", "ephy"; + resets = <&sysc 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; |