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| author | Chuanhong Guo <gch981213@gmail.com> | 2019-07-13 17:59:03 +0800 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2019-07-16 09:50:16 +0800 |
| commit | fae125781eefcbc60e233c39b39a3c62120ae194 (patch) | |
| tree | d844fdde0c99faf5f2b07894ae417b26ca1a25ed | |
| parent | 4a06d62f0e638a5edfc859bd8f3a58ab59f9790e (diff) | |
| download | openwrt-fae125781eefcbc60e233c39b39a3c62120ae194.tar.gz openwrt-fae125781eefcbc60e233c39b39a3c62120ae194.tar.bz2 openwrt-fae125781eefcbc60e233c39b39a3c62120ae194.zip | |
ramips: mtk-mmc: mt76x8: check ESD_MODE before applying AGPIO_CFG
Since mt76x8an ver1 eco2, SDXC pins can be switched to the
following pinmap:
sd_d1 -> PAD_I2S_SDI
sd_d0 -> PAD_I2S_WS
sd_cmd -> PAD_I2S_CLK
sd_d3 -> PAD_I2C_SCLK
sd_d2 -> PAD_I2C_SD
sd_clk -> PAD_GPIO0
sd_wp -> PAD_TXD1
sd_cd -> PAD_RXD1
To use this pinmap, one would need to set ESD_MODE bit (bit 15)
to 1 in GPIO1_MODE and switch other used pads into GPIO mode.
In this mode, we don't need to switch ethernet pins to digital
pad.
Check ESD_MODE bit before applying AGPIO_CFG and use rt_sysc_m32
to set it.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
| -rw-r--r-- | target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c index 4ced4b6605..cb0aa4231a 100644 --- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c +++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c @@ -2205,16 +2205,12 @@ static int msdc_drv_probe(struct platform_device *pdev) struct msdc_host *host; struct msdc_hw *hw; int ret; - u32 reg; //FIXME: this should be done by pinconf and not by the sd driver - if (ralink_soc == MT762X_SOC_MT7688 || - ralink_soc == MT762X_SOC_MT7628AN) { - /* set EPHY pads to digital mode */ - reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c)); - reg |= 0x1e << 16; - sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c), reg); - } + if ((ralink_soc == MT762X_SOC_MT7688 || + ralink_soc == MT762X_SOC_MT7628AN) && + (!(rt_sysc_r32(0x60) & BIT(15)))) + rt_sysc_m32(0xf << 17, 0xf << 17, 0x3c); hw = &msdc0_hw; |