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| author | Robert Marko <robimarko@gmail.com> | 2024-03-26 12:36:27 +0100 |
|---|---|---|
| committer | Robert Marko <robimarko@gmail.com> | 2024-03-26 18:10:50 +0100 |
| commit | 1d33ee019f62021dfd4911ce8b5a7537a545ede8 (patch) | |
| tree | c1f2db334b19b9f621fe23f8a3215686676c8649 /package/boot | |
| parent | 80b2288ea3234958e78761cc4720c03d4072d830 (diff) | |
| download | openwrt-1d33ee019f62021dfd4911ce8b5a7537a545ede8.tar.gz openwrt-1d33ee019f62021dfd4911ce8b5a7537a545ede8.tar.bz2 openwrt-1d33ee019f62021dfd4911ce8b5a7537a545ede8.zip | |
kernel: qca-ssdk: fix C45 MDIO support on kernel 6.6
Kernel 6.3 has introduced separate C45 read/write operations, and thus
split them out of the C22 operations completely so the old way of marking
C45 reads and writes via the register value does not work anymore.
This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones:
[ 22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match
[ 22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match
This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY
autoneg will time out, causing the 10G ports not to work:
[ 37.292784] uniphy autoneg time out!
So, lets detect C45 reads and writes by the magic BIT(30) in the register
argument and if so call separate C45 mdiobus read/write functions.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Diffstat (limited to 'package/boot')
0 files changed, 0 insertions, 0 deletions