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author | Glen Lee <g2lee@yahoo.com> | 2023-06-29 15:58:05 -0400 |
---|---|---|
committer | Christian Marangi <ansuelsmth@gmail.com> | 2023-10-05 00:56:57 +0200 |
commit | 3aef61060e3f51aa43fe494d5ff173e81dd43003 (patch) | |
tree | 831f3ef4097bfda082f0b0755a9aa483ba9b7a90 /target/linux/ipq806x/files/arch/arm/boot/dts | |
parent | 89895937dd4a24446b7bfd067398b4f7e73dc7b5 (diff) | |
download | openwrt-3aef61060e3f51aa43fe494d5ff173e81dd43003.tar.gz openwrt-3aef61060e3f51aa43fe494d5ff173e81dd43003.tar.bz2 openwrt-3aef61060e3f51aa43fe494d5ff173e81dd43003.zip |
ipq806x: add support for Extreme Networks AP3935
Extreme Networks AP3935i/e -
https://www.extremenetworks.com/support/documentation/access-points-ap3935i-e/
SoC: IPQ8068 QYY AT46279K45060I
RAM: NANYA 1527 NT5CC256M16DP-DI 515073W0EF 7 TW
FLASH: NOR - S25FL256S1 - 32MB
NAND - Macronix MX30UF4G28AB - 512MB
LAN: Atheros AR8035-A J5150WL 1515 CN - RGMII
LAN2: Atheros AR8033-AL1A SKCSR.AJ1 1444 China - SGMII
WLAN2: QCA9990 OVV FNPV209 K451406
WLAN5: QCA9990 OVV FNPV209 K451406
SERIAL: RS232 Port (115200 8n1) Cisco console cable and
4pin Serial Header | 3.3 | GND | RX | TX
MAC address for LAN1/LAN2/WLAN 2G/WLAN 5G in uboot env
* Installation via either RJ45 console or on-board 4 PIN header
Install Method
--------------
1) Setup TFTP server, and place
openwrt-ipq806x-generic-extreme_ap3935-initramfs-uImage image
in /srv/tftp or similar
2) Connect to console on router and connect ethernet port "LAN1" to
your LAN
3) Interupt the boot with any character
4) Login with admin/new2day for default password
(use reset/FactoryDefault if password needs to be reset)
5) Set serverip to TFTP IP: set serverip 192.168.1.2
6) Set ipaddr to another IP: set ipaddr 192.168.1.101
7) Make uboot ping something to activate eth0 on boot:
set bootcmd 'ping 192.168.1.1; run boot_flash'
saveenv
8) TFTP image to RAM:
tftpboot 0x42000000
openwrt-ipq806x-generic-extreme_ap3935i-initramfs-uImage
9) Boot image: bootm 0x42000000
In OpenWRT, "LAN1" is LAN, "LAN2" is WAN
10) SFTP openwrt-ipq806x-generic-extreme_ap3935-squashfs-nand-sysupgrade.bin
image to /tmp
11) sysupgrade /tmp/openwrt-*-nand-sysupgrade.bin
Signed-off-by: Glen Lee <g2lee@yahoo.com>
Diffstat (limited to 'target/linux/ipq806x/files/arch/arm/boot/dts')
-rw-r--r-- | target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts | 351 |
1 files changed, 351 insertions, 0 deletions
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts new file mode 100644 index 0000000000..5c75de8f8d --- /dev/null +++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include <dt-bindings/input/input.h> +#include <dt-bindings/soc/qcom,tcsr.h> + +/ { + model = "Extreme Networks AP3935"; + compatible = "extreme,ap3935", "qcom,ipq8064"; + + memory@0 { + reg = <0x41400000 0x3ec00000>; + device_type = "memory"; + }; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi2_serial; + mdio-gpio0 = &mdio0; + ethernet0 = &gmac0; + ethernet1 = &gmac2; + + led-boot = &led_power_green; + led-failsafe = &led_power_orange; + led-running = &led_power_green; + led-upgrade = &led_power_green; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-override = "ubi.block=0,0 root=/dev/ubiblock0_0"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + }; + + led_power_orange: power_orange { + label = "orange:power"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + led_wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led_wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_lan1_green { + label = "green:lan1"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_lan1_orange { + label = "orange:lan1"; + gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + led_lan2_green { + label = "green:lan2"; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + led_lan2_orange { + label = "orange:lan2"; + gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27", "gpio28", "gpio29"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + }; +}; + +&gsbi2 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; + + gsbi2_serial: serial@12490000 { + status = "okay"; + }; +}; + +&gsbi4 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; + + serial@16340000 { + status = "disabled"; + }; +}; + +&gsbi7 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; + + gsbi7_serial: serial@16640000 { + status = "okay"; + }; +}; + +&gsbi5 { + qcom,mode = <GSBI_PROT_SPI>; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + + cfg1@02a0000 { + compatible = "u-boot,env-redundant-bool"; + label = "CFG1"; + reg = <0x02a0000 0x0010000>; + + ethaddr: ethaddr { + }; + }; + + bootpri@02b0000 { + label = "BootPRI"; + reg = <0x02b0000 0x0080000>; + }; + + cfg2@0330000 { + label = "CFG2"; + reg = <0x0330000 0x0010000>; + }; + + fs@0340000 { + label = "FS"; + reg = <0x0340000 0x0080000>; + }; + + priimg@03c0000 { + label = "PriImg"; + reg = <0x03c0000 0x0e10000>; + }; + + secimg@11d0000 { + label = "SecImg"; + reg = <0x11d0000 0x0e10000>; + }; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&nand { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <8>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubi@0 { + label = "ubi"; + reg = <0x0000000 0x20000000>; + }; + }; + }; +}; + +&soc { + mdio1: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; +}; + +&gmac0 { + status = "okay"; + + qcom,id = <0>; + mdiobus = <&mdio1>; + + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + nvmem-cells = <ðaddr>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio1>; + + phy-mode = "sgmii"; + phy-handle = <&phy2>; +}; + +&adm_dma { + status = "okay"; +}; |