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author | Robert Marko <robimarko@gmail.com> | 2024-03-22 10:01:17 +0100 |
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committer | Robert Marko <robimarko@gmail.com> | 2024-03-22 21:19:21 +0100 |
commit | e28492c81ac57c200798d62c60af4a288b076cfb (patch) | |
tree | 6d1a7272964dd89f501984eb6cd6bad6432bb95d /target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch | |
parent | 6bdea8c7bd85a43e0490107613a60c4f805e093f (diff) | |
download | openwrt-e28492c81ac57c200798d62c60af4a288b076cfb.tar.gz openwrt-e28492c81ac57c200798d62c60af4a288b076cfb.tar.bz2 openwrt-e28492c81ac57c200798d62c60af4a288b076cfb.zip |
kernel/qualcommax: Create kernel files for v6.6 (from v6.1)
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Diffstat (limited to 'target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch')
-rw-r--r-- | target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch b/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch new file mode 100644 index 0000000000..ca3c896047 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch @@ -0,0 +1,81 @@ +From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001 +From: Chukun Pan <amadeus@jmu.edu.cn> +Date: Sun, 3 Dec 2023 23:39:14 +0800 +Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node + +Add node to support all the QUP UART node controller inside of IPQ6018. +Some routers use these bus to connect Bluetooth chips. + +Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> +Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn +Signed-off-by: Bjorn Andersson <andersson@kernel.org> +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -458,6 +458,26 @@ + qcom,ee = <0>; + }; + ++ blsp1_uart1: serial@78af000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78af000 0x0 0x200>; ++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart2: serial@78b0000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78b0000 0x0 0x200>; ++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x0 0x078b1000 0x0 0x200>; +@@ -466,6 +486,36 @@ + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; ++ }; ++ ++ blsp1_uart4: serial@78b2000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x078b2000 0x0 0x200>; ++ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart5: serial@78b3000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x78b3000 0x0 0x200>; ++ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart6: serial@78b4000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x0 0x078b4000 0x0 0x200>; ++ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { |