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| author | Chuanhong Guo <gch981213@gmail.com> | 2020-04-12 20:58:29 +0800 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2020-04-12 22:29:17 +0800 |
| commit | b756ea2a909a36d7e931b96edf0d15539421c733 (patch) | |
| tree | fcdf71be66cce8bb5a588d1fd972cf4d77c3595f /target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch | |
| parent | 8f6334eb947a2594da8a2b58cf7afdabb83fb5a0 (diff) | |
| download | openwrt-b756ea2a909a36d7e931b96edf0d15539421c733.tar.gz openwrt-b756ea2a909a36d7e931b96edf0d15539421c733.tar.bz2 openwrt-b756ea2a909a36d7e931b96edf0d15539421c733.zip | |
ramips: replace pinctrl property names
Upstream pinctrl driver in drivers/staging uses
groups/function/ralink,num-gpios instead of
ralink,group/ralink,function/ralink,nr-gpio
Replace these properties in dts as well as the pinctrl driver in
patches-4.14.
This commit is created using:
sed -i 's/ralink,group/groups/g'
sed -i 's/ralink,function/function/g'
sed -i 's/ralink,nr-gpio/ralink,num-gpios/g'
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch')
| -rw-r--r-- | target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch index 0bce0b433a..7d5f98f647 100644 --- a/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch +++ b/target/linux/ramips/patches-5.4/0026-DT-Add-documentation-for-gpio-ralink.patch @@ -29,7 +29,7 @@ Cc: linux-gpio@vger.kernel.org +- reg : Physical base address and length of the controller's registers +- interrupt-parent: phandle to the INTC device node +- interrupts : Specify the INTC interrupt number -+- ralink,nr-gpio : Specify the number of GPIOs ++- ralink,num-gpios : Specify the number of GPIOs +- ralink,register-map : The register layout depends on the GPIO bank and actual + SoC type. Register offsets need to be in this order. + [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ] @@ -51,7 +51,7 @@ Cc: linux-gpio@vger.kernel.org + interrupts = <6>; + + ralink,gpio-base = <0>; -+ ralink,nr-gpio = <24>; ++ ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; |