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author | Daniel Golle <daniel@makrotopia.org> | 2024-01-24 19:10:36 +0000 |
---|---|---|
committer | Daniel Golle <daniel@makrotopia.org> | 2024-02-15 19:30:08 +0000 |
commit | ada3b2190a86fe329d0e45b6a03dbd37e3911611 (patch) | |
tree | 0728acc94ac8362d810a28a8d6135970deed82f8 /target | |
parent | 1e58ce7652c38580ef719cc8a8a795b87c531bcc (diff) | |
download | openwrt-ada3b2190a86fe329d0e45b6a03dbd37e3911611.tar.gz openwrt-ada3b2190a86fe329d0e45b6a03dbd37e3911611.tar.bz2 openwrt-ada3b2190a86fe329d0e45b6a03dbd37e3911611.zip |
mediatek: update driver for MT7988 built-in 2.5G Ethernet PHY
Sync driver for built-in 2.5G Ethernet PHY with MediaTek SDK.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 5 | ||||
-rw-r--r-- | target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c | 216 |
2 files changed, 137 insertions, 84 deletions
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 76278281df..904339335f 100644 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -218,9 +218,8 @@ phyfw: phy-firmware@f000000 { compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f000000 0 0x8000>, - <0 0x0f100000 0 0x20000>, - <0 0x0f0f0000 0 0x200>; + reg = <0 0x0f100000 0 0x20000>, + <0 0x0f0f0018 0 0x20>; }; infracfg: infracfg@10001000 { diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c index c12e6b8eb6..e2e06d1eca 100644 --- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c +++ b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c @@ -7,37 +7,50 @@ #include <linux/of_platform.h> #include <linux/pinctrl/consumer.h> #include <linux/phy.h> +#include <linux/pm_domain.h> +#include <linux/pm_runtime.h> -#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" -#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" +#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin" -#define MD32_EN_CFG 0x18 -#define MD32_EN BIT(0) +#define MD32_EN BIT(0) +#define PMEM_PRIORITY BIT(8) +#define DMEM_PRIORITY BIT(16) -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 +#define BASE100T_STATUS_EXTEND 0x10 +#define BASE1000T_STATUS_EXTEND 0x11 +#define EXTEND_CTRL_AND_STATUS 0x16 -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) +#define PHY_AUX_CTRL_STATUS 0x1d +#define PHY_AUX_DPX_MASK GENMASK(5, 5) +#define PHY_AUX_SPEED_MASK GENMASK(4, 2) /* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) +#define MTK_PHY_LINK_STATUS_MISC 0xa2 +#define MTK_PHY_FDX_ENABLE BIT(5) + +#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) /* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED0_ON_LINK1000 BIT(0) +#define MTK_PHY_LED0_ON_LINK100 BIT(1) +#define MTK_PHY_LED0_ON_LINK10 BIT(2) +#define MTK_PHY_LED0_ON_LINK2500 BIT(7) +#define MTK_PHY_LED0_POLARITY BIT(14) + +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_PHY_LED1_ON_FDX BIT(4) +#define MTK_PHY_LED1_ON_HDX BIT(5) +#define MTK_PHY_LED1_POLARITY BIT(14) + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +struct mtk_i2p5ge_phy_priv { + bool fw_loaded; +}; enum { PHY_AUX_SPD_10 = 0, @@ -46,67 +59,89 @@ enum { PHY_AUX_SPD_2500, }; -static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) +static int mtk_2p5ge_phy_read_page(struct phy_device *phydev) { - int ret; - int i; + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +static int mt7988_2p5ge_phy_probe(struct phy_device *phydev) +{ + struct mtk_i2p5ge_phy_priv *phy_priv; + + phy_priv = devm_kzalloc(&phydev->mdio.dev, + sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); + if (!phy_priv) + return -ENOMEM; + + phydev->priv = phy_priv; + + return 0; +} + +static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev) +{ + int ret, i; const struct firmware *fw; struct device *dev = &phydev->mdio.dev; struct device_node *np; - void __iomem *dmb_addr; void __iomem *pmb_addr; - void __iomem *mcucsr_base; + void __iomem *md32_en_cfg_base; + struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv; u16 reg; struct pinctrl *pinctrl; - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; + if (!phy_priv->fw_loaded) { + np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); + if (!np) + return -ENOENT; + pmb_addr = of_iomap(np, 0); + if (!pmb_addr) + return -ENOMEM; + md32_en_cfg_base = of_iomap(np, 1); + if (!md32_en_cfg_base) + return -ENOMEM; + + ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev); + if (ret) { + dev_err(dev, "failed to load firmware: %s, ret: %d\n", + MT7988_2P5GE_PMB, ret); + return ret; + } + + reg = readw(md32_en_cfg_base); + if (reg & MD32_EN) { + phy_set_bits(phydev, 0, BIT(15)); + usleep_range(10000, 11000); + } + phy_set_bits(phydev, 0, BIT(11)); - dmb_addr = of_iomap(np, 0); - if (!dmb_addr) - return -ENOMEM; - pmb_addr = of_iomap(np, 1); - if (!pmb_addr) - return -ENOMEM; - mcucsr_base = of_iomap(np, 2); - if (!mcucsr_base) - return -ENOMEM; + /* Write magic number to safely stall MCU */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df); - ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDAITEK_2P5GE_PHY_DMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); - release_firmware(fw); - - ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDIATEK_2P5GE_PHY_PMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); + for (i = 0; i < fw->size - 1; i += 4) + writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); + release_firmware(fw); - reg = readw(mcucsr_base + MD32_EN_CFG); - writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); - dev_dbg(dev, "Firmware loading/trigger ok.\n"); + writew(reg & ~MD32_EN, md32_en_cfg_base); + writew(reg | MD32_EN, md32_en_cfg_base); + phy_set_bits(phydev, 0, BIT(15)); + dev_info(dev, "Firmware loading/trigger ok.\n"); - /* Setup LED */ - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); + phy_priv->fw_loaded = true; + } + /* Setup LED */ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000 | MTK_PHY_LED0_ON_LINK2500); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); @@ -116,10 +151,20 @@ static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) return PTR_ERR(pinctrl); } + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, + MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); + + /* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __phy_write(phydev, 0x11, 0xfbfa); + __phy_write(phydev, 0x12, 0xc3); + __phy_write(phydev, 0x10, 0x87f8); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + return 0; } -static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) +static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev) { bool changed = false; u32 adv; @@ -152,7 +197,7 @@ static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) return genphy_c45_check_and_restart_aneg(phydev, changed); } -static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) +static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev) { int ret; @@ -160,7 +205,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) if (ret) return ret; - /* We don't support HDX at MAC layer on mt798x. + /* We don't support HDX at MAC layer on mt7988. * So mask phy's HDX capabilities, too. */ linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, @@ -176,7 +221,7 @@ static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) return 0; } -static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) +static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev) { int ret; @@ -189,9 +234,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) phydev->pause = 0; phydev->asym_pause = 0; - if (!phydev->link) - return 0; - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { ret = genphy_c45_read_lpa(phydev); if (ret < 0) @@ -222,7 +264,6 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) break; case PHY_AUX_SPD_2500: phydev->speed = SPEED_2500; - phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ break; } @@ -231,18 +272,32 @@ static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) return ret; phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; + /* FIXME: The current firmware always enables rate adaptation mode. */ + phydev->rate_matching = RATE_MATCH_PAUSE; return 0; } +static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) +{ + return RATE_MATCH_PAUSE; +} + static struct phy_driver mtk_gephy_driver[] = { { - PHY_ID_MATCH_EXACT(0x00339c11), + PHY_ID_MATCH_MODEL(0x00339c11), .name = "MediaTek MT798x 2.5GbE PHY", - .config_init = mt798x_2p5ge_phy_config_init, - .config_aneg = mt798x_2p5ge_phy_config_aneg, - .get_features = mt798x_2p5ge_phy_get_features, - .read_status = mt798x_2p5ge_phy_read_status, + .probe = mt7988_2p5ge_phy_probe, + .config_init = mt7988_2p5ge_phy_config_init, + .config_aneg = mt7988_2p5ge_phy_config_aneg, + .get_features = mt7988_2p5ge_phy_get_features, + .read_status = mt7988_2p5ge_phy_read_status, + .get_rate_matching = mt7988_2p5ge_phy_get_rate_matching, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_page = mtk_2p5ge_phy_read_page, + .write_page = mtk_2p5ge_phy_write_page, }, }; @@ -258,5 +313,4 @@ MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); -MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); +MODULE_FIRMWARE(MT7988_2P5GE_PMB); |