diff options
Diffstat (limited to 'target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch b/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch deleted file mode 100644 index 9032f11794..0000000000 --- a/target/linux/bcm27xx/patches-5.15/950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 671b5b9af51bd5296d4fe76155b3ba75c99000b9 Mon Sep 17 00:00:00 2001 -From: Dave Stevenson <dave.stevenson@raspberrypi.com> -Date: Mon, 13 Sep 2021 17:30:18 +0100 -Subject: [PATCH] drm/vc4: Reset HDMI MISC_CONTROL register. - -The HDMI block can repeat pixels for double clocked modes, -and the firmware is now configuring the block to do this as -the PV is doing it incorrectly when at 2pixels/clock. -If the kernel doesn't reset it then we end up with strange -modes. - -Reset MISC_CONTROL. - -Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> ---- - drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++++++ - drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 +++ - 2 files changed, 11 insertions(+) - ---- a/drivers/gpu/drm/vc4/vc4_hdmi.c -+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c -@@ -79,6 +79,9 @@ - #define VC5_HDMI_VERTB_VSPO_SHIFT 16 - #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) - -+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 -+#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) -+ - #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) - - #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 -@@ -963,6 +966,11 @@ static void vc5_hdmi_set_timings(struct - reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; - HDMI_WRITE(HDMI_GCP_CONFIG, reg); - -+ reg = HDMI_READ(HDMI_MISC_CONTROL); -+ reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; -+ reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP); -+ HDMI_WRITE(HDMI_MISC_CONTROL, reg); -+ - HDMI_WRITE(HDMI_CLOCK_STOP, 0); - - spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); ---- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h -+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h -@@ -125,6 +125,7 @@ enum vc4_hdmi_field { - HDMI_VERTB0, - HDMI_VERTB1, - HDMI_VID_CTL, -+ HDMI_MISC_CONTROL, - }; - - struct vc4_hdmi_register { -@@ -235,6 +236,7 @@ static const struct vc4_hdmi_register __ - VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), - VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), - VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), -+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100), - VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), - VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), - VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), -@@ -315,6 +317,7 @@ static const struct vc4_hdmi_register __ - VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), - VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), - VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), -+ VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100), - VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), - VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), - VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), |