1 files changed, 267 insertions, 128 deletions

diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
index a0717e1d9a..e0832c42b8 100644
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
@@ -10,29 +10,6 @@
 extern struct rtl83xx_soc_info soc_info;
 
 
-static void rtl83xx_print_matrix(void)
-{
-	unsigned volatile int *ptr8;
-	volatile u64 *ptr9;
-	int i;
-
-	if (soc_info.family == RTL8380_FAMILY_ID) {
-		ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
-		for (i = 0; i < 28; i += 8)
-			pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
-				ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
-				ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
-		pr_debug("CPU_PORT> %8x\n", ptr8[28]);
-	} else {
-		ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
-		for (i = 0; i < 52; i += 4)
-			pr_debug("> %16llx %16llx %16llx %16llx\n",
-				ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
-		pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
-	}
-
-}
-
 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
 {
 	mutex_lock(&priv->reg_mutex);
@@ -66,10 +43,17 @@ static void rtl83xx_write_cam(int idx, u32 *r)
 
 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
 {
-	if (priv->family_id == RTL8380_FAMILY_ID)
+	switch (priv->family_id) {
+	case RTL8380_FAMILY_ID:
 		return rtl838x_hash(priv, mac << 12 | vid);
-	else
+	case RTL8390_FAMILY_ID:
 		return rtl839x_hash(priv, mac << 12 | vid);
+	case RTL9300_FAMILY_ID:
+		return rtl930x_hash(priv, ((u64)vid) << 48 | mac);
+	default:
+		pr_err("Hash not implemented\n");
+	}
+	return 0;
 }
 
 static void rtl83xx_write_hash(int idx, u32 *r)
@@ -101,10 +85,10 @@ static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
 	pr_debug("%s: %16llx\n", __func__, v);
 	priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
 
-	/* PHY update complete */
+	/* PHY update complete, there is no global PHY polling enable bit on the 9300 */
 	if (priv->family_id == RTL8390_FAMILY_ID)
 		sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
-	else
+	else if(priv->family_id == RTL9300_FAMILY_ID)
 		sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
 }
 
@@ -197,7 +181,10 @@ static int rtl83xx_setup(struct dsa_switch *ds)
 	}
 	priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
 
-	rtl83xx_print_matrix();
+	if (priv->family_id == RTL8380_FAMILY_ID)
+		rtl838x_print_matrix();
+	else
+		rtl839x_print_matrix();
 
 	rtl83xx_init_stats(priv);
 
@@ -210,6 +197,44 @@ static int rtl83xx_setup(struct dsa_switch *ds)
 	return 0;
 }
 
+static int rtl930x_setup(struct dsa_switch *ds)
+{
+	int i;
+	struct rtl838x_switch_priv *priv = ds->priv;
+	u32 port_bitmap = BIT(priv->cpu_port);
+
+	pr_info("%s called\n", __func__);
+
+	// Enable CSTI STP mode
+//	sw_w32(1, RTL930X_ST_CTRL);
+
+	/* Disable MAC polling the PHY so that we can start configuration */
+	sw_w32(0, RTL930X_SMI_POLL_CTRL);
+
+	// Disable all ports except CPU port
+	for (i = 0; i < ds->num_ports; i++)
+		priv->ports[i].enable = false;
+	priv->ports[priv->cpu_port].enable = true;
+
+	for (i = 0; i < priv->cpu_port; i++) {
+		if (priv->ports[i].phy) {
+			priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i));
+			port_bitmap |= 1ULL << i;
+		}
+	}
+	priv->r->traffic_set(priv->cpu_port, port_bitmap);
+
+	rtl930x_print_matrix();
+
+	// TODO: Initialize statistics
+
+	ds->configure_vlan_while_not_filtering = true;
+
+	rtl83xx_enable_phy_polling(priv);
+
+	return 0;
+}
+
 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
 				     unsigned long *supported,
 				     struct phylink_link_state *state)
@@ -269,13 +294,24 @@ static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
 	u64 speed;
+	u64 link;
 
 	if (port < 0 || port > priv->cpu_port)
 		return -EINVAL;
 
+	/*
+	 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
+	 * state needs to be read twice in order to read a correct result.
+	 * This would not be necessary for ports connected e.g. to RTL8218D
+	 * PHYs.
+	 */
 	state->link = 0;
-	if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port))
+	link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
+	link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
+	if (link & BIT_ULL(port))
 		state->link = 1;
+	pr_info("%s: link state: %llx\n", __func__, link & BIT_ULL(port));
+
 	state->duplex = 0;
 	if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
 		state->duplex = 1;
@@ -317,6 +353,10 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
 
 	pr_debug("%s port %d, mode %x\n", __func__, port, mode);
 
+	// BUG: Make this work on RTL93XX
+	if (priv->family_id >= RTL9300_FAMILY_ID)
+		return;
+
 	if (port == priv->cpu_port) {
 		/* Set Speed, duplex, flow control
 		 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
@@ -422,15 +462,15 @@ static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
 	struct rtl838x_switch_priv *priv = ds->priv;
 	const struct rtl83xx_mib_desc *mib;
 	int i;
-	u64 high;
+	u64 h;
 
 	for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
 		mib = &rtl83xx_mib[i];
 
-		data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
+		data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
 		if (mib->size == 2) {
-			high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
-			data[i] |= high << 32;
+			h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
+			data[i] |= h << 32;
 		}
 	}
 }
@@ -447,21 +487,30 @@ static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
 				struct phy_device *phydev)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 v;
 
 	pr_debug("%s: %x %d", __func__, (u32) priv, port);
 	priv->ports[port].enable = true;
 
 	/* enable inner tagging on egress, do not keep any tags */
-	sw_w32(1, priv->r->vlan_port_tag_sts_ctrl(port));
+	if (priv->family_id == RTL9310_FAMILY_ID)
+		sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
+	else
+		sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
 
 	if (dsa_is_cpu_port(ds, port))
 		return 0;
 
 	/* add port to switch mask of CPU_PORT */
-	priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port));
+	priv->r->traffic_enable(priv->cpu_port, port);
 
 	/* add all other ports in the same bridge to switch mask of port */
-	priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
+	v = priv->r->traffic_get(port);
+	v |= priv->ports[port].pm;
+	priv->r->traffic_set(port, v);
+
+	sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
+	sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
 
 	return 0;
 }
@@ -469,17 +518,21 @@ static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
+	u64 v;
 
 	pr_debug("%s %x: %d", __func__, (u32)priv, port);
 	/* you can only disable user ports */
 	if (!dsa_is_user_port(ds, port))
 		return;
 
+	// BUG: This does not work on RTL931X
 	/* remove port from switch mask of CPU_PORT */
-	priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port));
+	priv->r->traffic_disable(priv->cpu_port, port);
 
 	/* remove all other ports in the same bridge from switch mask of port */
-	priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
+	v = priv->r->traffic_get(port);
+	v &= ~priv->ports[port].pm;
+	priv->r->traffic_set(port, v);
 
 	priv->ports[port].enable = false;
 }
@@ -565,7 +618,7 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
 					struct net_device *bridge)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 port_bitmap = BIT_ULL(priv->cpu_port);
+	u64 port_bitmap = 1ULL << priv->cpu_port, v;
 	int i;
 
 	pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
@@ -579,20 +632,19 @@ static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
 			if (dsa_to_port(ds, i)->bridge_dev != bridge)
 				continue;
 			if (priv->ports[i].enable)
-				priv->r->mask_port_reg_be(0, BIT_ULL(port),
-						       priv->r->port_iso_ctrl(i));
-			priv->ports[i].pm |= BIT_ULL(port);
+				priv->r->traffic_enable(i, port);
 
-			port_bitmap |= BIT_ULL(i);
+			priv->ports[i].pm |= 1ULL << port;
+			port_bitmap |= 1ULL << i;
 		}
 	}
 
 	/* Add all other ports to this port matrix. */
 	if (priv->ports[port].enable) {
-		priv->r->mask_port_reg_be(0, BIT_ULL(port),
-					priv->r->port_iso_ctrl(priv->cpu_port));
-		priv->r->mask_port_reg_be(0, port_bitmap,
-					priv->r->port_iso_ctrl(port));
+		priv->r->traffic_enable(priv->cpu_port, port);
+		v = priv->r->traffic_get(port);
+		v |= port_bitmap;
+		priv->r->traffic_set(port, v);
 	}
 	priv->ports[port].pm |= port_bitmap;
 	mutex_unlock(&priv->reg_mutex);
@@ -604,7 +656,7 @@ static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
 					struct net_device *bridge)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
-	u64 port_bitmap = BIT_ULL(priv->cpu_port);
+	u64 port_bitmap = 1ULL << priv->cpu_port, v;
 	int i;
 
 	pr_debug("%s %x: %d", __func__, (u32)priv, port);
@@ -620,62 +672,53 @@ static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
 			if (dsa_to_port(ds, i)->bridge_dev != bridge)
 				continue;
 			if (priv->ports[i].enable)
-				priv->r->mask_port_reg_be(BIT_ULL(port), 0,
-						       priv->r->port_iso_ctrl(i));
-			priv->ports[i].pm &= ~BIT_ULL(port);
+				priv->r->traffic_disable(i, port);
 
+			priv->ports[i].pm |= 1ULL << port;
 			port_bitmap &= ~BIT_ULL(i);
 		}
 	}
 
 	/* Add all other ports to this port matrix. */
-	if (priv->ports[port].enable)
-		priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port));
+	if (priv->ports[port].enable) {
+		v = priv->r->traffic_get(port);
+		v |= port_bitmap;
+		priv->r->traffic_set(port, v);
+	}
 	priv->ports[port].pm &= ~port_bitmap;
 
 	mutex_unlock(&priv->reg_mutex);
 }
 
-static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port,
-				       u8 state)
+void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
 {
-	u32 cmd, msti = 0;
+	u32 msti = 0;
 	u32 port_state[4];
-	int index, bit, i;
+	int index, bit;
 	int pos = port;
 	struct rtl838x_switch_priv *priv = ds->priv;
-	int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
+	int n = priv->port_width << 1;
 
-	pr_debug("%s: port %d state %2x\n", __func__, port, state);
-
-	/* CPU PORT can only be configured on RTL838x */
-	if (port >= priv->cpu_port || port > 51)
+	/* Ports above or equal CPU port can never be configured */
+	if (port >= priv->cpu_port)
 		return;
 
 	mutex_lock(&priv->reg_mutex);
 
-	/* For the RTL839x, the bits are left-aligned in the 128 bit field */
+	/* For the RTL839x and following, the bits are left-aligned, 838x and 930x
+	 * have 64 bit fields, 839x and 931x have 128 bit fields
+	 */
 	if (priv->family_id == RTL8390_FAMILY_ID)
 		pos += 12;
+	if (priv->family_id == RTL9300_FAMILY_ID)
+		pos += 3;
+	if (priv->family_id == RTL9310_FAMILY_ID)
+		pos += 8;
 
 	index = n - (pos >> 4) - 1;
 	bit = (pos << 1) % 32;
 
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		cmd = BIT(15) /* Execute cmd */
-			| BIT(14) /* Read */
-			| 2 << 12 /* Table type 0b10 */
-			| (msti & 0xfff);
-	} else {
-		cmd = BIT(16) /* Execute cmd */
-			| 0 << 15 /* Read */
-			| 5 << 12 /* Table type 0b101 */
-			| (msti & 0xfff);
-	}
-	priv->r->exec_tbl0_cmd(cmd);
-
-	for (i = 0; i < n; i++)
-		port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
+	priv->r->stp_get(priv, msti, port_state);
 
 	pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
 	port_state[index] &= ~(3 << bit);
@@ -697,25 +740,12 @@ static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port,
 		break;
 	}
 
-	if (priv->family_id == RTL8380_FAMILY_ID) {
-		cmd = BIT(15) /* Execute cmd */
-			| 0 << 14 /* Write */
-			| 2 << 12 /* Table type 0b10 */
-			| (msti & 0xfff);
-	} else {
-		cmd = 1 << 16 /* Execute cmd */
-			| BIT(15) /* Write */
-			| 5 << 12 /* Table type 0b101 */
-			| (msti & 0xfff);
-	}
-	for (i = 0; i < n; i++)
-		sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
-	priv->r->exec_tbl0_cmd(cmd);
+	priv->r->stp_set(priv, msti, port_state);
 
 	mutex_unlock(&priv->reg_mutex);
 }
 
-static void rtl83xx_fast_age(struct dsa_switch *ds, int port)
+void rtl83xx_fast_age(struct dsa_switch *ds, int port)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
 	int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
@@ -735,7 +765,22 @@ static void rtl83xx_fast_age(struct dsa_switch *ds, int port)
 	 */
 	sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
 
-	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
+	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+void rtl930x_fast_age(struct dsa_switch *ds, int port)
+{
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	pr_debug("FAST AGE port %d\n", port);
+	mutex_lock(&priv->reg_mutex);
+	sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
+
+	sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
+
+	do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
 
 	mutex_unlock(&priv->reg_mutex);
 }
@@ -749,17 +794,24 @@ static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
 	mutex_lock(&priv->reg_mutex);
 
 	if (vlan_filtering) {
-		/* Enable ingress and egress filtering */
+		/* Enable ingress and egress filtering
+		 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
+		 * the filter action:
+		 * 0: Always Forward
+		 * 1: Drop packet
+		 * 2: Trap packet to CPU port
+		 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
+		 */
 		if (port != priv->cpu_port)
 			sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
-				    priv->r->vlan_port_igr_filter(port));
-		sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port));
+				    priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
+		sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
 	} else {
 		/* Disable ingress and egress filtering */
 		if (port != priv->cpu_port)
 			sw_w32_mask(0b11 << ((port % 16) << 1), 0,
-				    priv->r->vlan_port_igr_filter(port));
-		sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port));
+				    priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
+		sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
 	}
 
 	/* Do we need to do something to the CPU-Port, too? */
@@ -774,21 +826,23 @@ static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
 	struct rtl838x_vlan_info info;
 	struct rtl838x_switch_priv *priv = ds->priv;
 
-	pr_debug("%s: port %d\n", __func__, port);
+	pr_info("%s: port %d\n", __func__, port);
 
 	mutex_lock(&priv->reg_mutex);
 
-	if (priv->family_id == RTL8380_FAMILY_ID)
-		rtl838x_vlan_profile_dump(0);
-	else
-		rtl839x_vlan_profile_dump(0);
-
-	priv->r->vlan_tables_read(0, &info);
+	priv->r->vlan_profile_dump(1);
+	priv->r->vlan_tables_read(1, &info);
 
-	pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
+	pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
 		info.tagged_ports, info.untagged_ports, info.profile_id,
 		info.hash_mc_fid, info.hash_uc_fid, info.fid);
 
+	priv->r->vlan_set_untagged(1, info.untagged_ports);
+	pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
+
+	priv->r->vlan_set_tagged(1, &info);
+	pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
+
 	mutex_unlock(&priv->reg_mutex);
 	return 0;
 }
@@ -796,11 +850,11 @@ static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
 			    const struct switchdev_obj_port_vlan *vlan)
 {
-	struct rtl838x_vlan_info info = {};
+	struct rtl838x_vlan_info info;
 	struct rtl838x_switch_priv *priv = ds->priv;
 	int v;
 
-	pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
+	pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
 		port, vlan->vid_begin, vlan->vid_end, vlan->flags);
 
 	if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
@@ -812,12 +866,19 @@ static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
 	mutex_lock(&priv->reg_mutex);
 
 	if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
-		/* Set both inner and outer PVID of the port */
-		sw_w32((vlan->vid_end << 16) | vlan->vid_end << 2, priv->r->vlan_port_pb(port));
-		priv->ports[port].pvid = vlan->vid_end;
+		for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
+			if (!v)
+				continue;
+			/* Set both inner and outer PVID of the port */
+			sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
+			priv->ports[port].pvid = vlan->vid_end;
+		}
 	}
 
 	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
+		if (!v)
+			continue;
+
 		/* Get port memberships of this vlan */
 		priv->r->vlan_tables_read(v, &info);
 
@@ -838,10 +899,10 @@ static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
 			info.untagged_ports |= BIT_ULL(port);
 
 		priv->r->vlan_set_untagged(v, info.untagged_ports);
-		pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
+		pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
 
 		priv->r->vlan_set_tagged(v, &info);
-		pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
+		pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
 	}
 
 	mutex_unlock(&priv->reg_mutex);
@@ -870,7 +931,7 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
 	for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
 		/* Reset to default if removing the current PVID */
 		if (v == pvid)
-			sw_w32(0, priv->r->vlan_port_pb(port));
+			sw_w32(0, priv->r->vlan_port_pb + (port << 2));
 
 		/* Get port memberships of this vlan */
 		priv->r->vlan_tables_read(v, &info);
@@ -962,7 +1023,7 @@ static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
 	u64 entry;
 	int idx = -1, err = 0, i;
 
-	pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
+	pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key);
 	mutex_lock(&priv->reg_mutex);
 	for (i = 0; i < 4; i++) {
 		entry = priv->r->read_l2_entry_using_hash(key, i, &e);
@@ -1048,6 +1109,7 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
 	/* We support 4 mirror groups, one destination port per group */
 	int group;
 	struct rtl838x_switch_priv *priv = ds->priv;
+	int ctrl_reg, dpm_reg, spm_reg;	
 
 	pr_debug("In %s\n", __func__);
 
@@ -1065,30 +1127,34 @@ static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
 	if (group >= 4)
 		return -ENOSPC;
 
+	ctrl_reg = priv->r->mir_ctrl + group * 4;
+	dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
+	spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
+
 	pr_debug("Using group %d\n", group);
 	mutex_lock(&priv->reg_mutex);
 
 	if (priv->family_id == RTL8380_FAMILY_ID) {
 		/* Enable mirroring to port across VLANs (bit 11) */
-		sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
+		sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
 	} else {
 		/* Enable mirroring to destination port */
-		sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group));
+		sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
 	}
 
-	if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) {
+	if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
 		mutex_unlock(&priv->reg_mutex);
 		return -EEXIST;
 	}
-	if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) {
+	if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
 		mutex_unlock(&priv->reg_mutex);
 		return -EEXIST;
 	}
 
 	if (ingress)
-		priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group));
+		priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
 	else
-		priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group));
+		priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
 
 	priv->mirror_group_ports[group] = mirror->to_local_port;
 	mutex_unlock(&priv->reg_mutex);
@@ -1100,6 +1166,7 @@ static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
 {
 	int group = 0;
 	struct rtl838x_switch_priv *priv = ds->priv;
+	int ctrl_reg, dpm_reg, spm_reg;
 
 	pr_debug("In %s\n", __func__);
 	for (group = 0; group < 4; group++) {
@@ -1109,29 +1176,66 @@ static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
 	if (group >= 4)
 		return;
 
+	ctrl_reg = priv->r->mir_ctrl + group * 4;
+	dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
+	spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
+
 	mutex_lock(&priv->reg_mutex);
 	if (mirror->ingress) {
 		/* Ingress, clear source port matrix */
-		priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group));
+		priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
 	} else {
 		/* Egress, clear destination port matrix */
-		priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group));
+		priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
 	}
 
-	if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) {
+	if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
 		priv->mirror_group_ports[group] = -1;
-		sw_w32(0, priv->r->mir_ctrl(group));
+		sw_w32(0, ctrl_reg);
 	}
 
 	mutex_unlock(&priv->reg_mutex);
 }
 
+int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
+{
+	u32 val;
+	u32 offset = 0;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	if (phy_addr >= 24 && phy_addr <= 27
+		&& priv->ports[24].phy == PHY_RTL838X_SDS) {
+		if (phy_addr == 26)
+			offset = 0x100;
+		val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
+		return val;
+	}
+
+	read_phy(phy_addr, 0, phy_reg, &val);
+	return val;
+}
+
+int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
+{
+	u32 offset = 0;
+	struct rtl838x_switch_priv *priv = ds->priv;
+
+	if (phy_addr >= 24 && phy_addr <= 27
+	     && priv->ports[24].phy == PHY_RTL838X_SDS) {
+		if (phy_addr == 26)
+			offset = 0x100;
+		sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
+		return 0;
+	}
+	return write_phy(phy_addr, 0, phy_reg, val);
+}
+
 const struct dsa_switch_ops rtl83xx_switch_ops = {
 	.get_tag_protocol	= rtl83xx_get_tag_protocol,
 	.setup			= rtl83xx_setup,
 
-	.phy_read		= rtl83xx_dsa_phy_read,
-	.phy_write		= rtl83xx_dsa_phy_write,
+	.phy_read		= dsa_phy_read,
+	.phy_write		= dsa_phy_write,
 
 	.phylink_validate	= rtl83xx_phylink_validate,
 	.phylink_mac_link_state	= rtl83xx_phylink_mac_link_state,
@@ -1168,3 +1272,38 @@ const struct dsa_switch_ops rtl83xx_switch_ops = {
 	.port_mirror_del	= rtl83xx_port_mirror_del,
 };
 
+const struct dsa_switch_ops rtl930x_switch_ops = {
+	.get_tag_protocol	= rtl83xx_get_tag_protocol,
+	.setup			= rtl930x_setup,
+
+	.phy_read		= dsa_phy_read,
+	.phy_write		= dsa_phy_write,
+
+	.phylink_validate	= rtl83xx_phylink_validate,
+	.phylink_mac_link_state	= rtl83xx_phylink_mac_link_state,
+	.phylink_mac_config	= rtl83xx_phylink_mac_config,
+	.phylink_mac_link_down	= rtl83xx_phylink_mac_link_down,
+	.phylink_mac_link_up	= rtl83xx_phylink_mac_link_up,
+
+	.get_strings		= rtl83xx_get_strings,
+	.get_ethtool_stats	= rtl83xx_get_ethtool_stats,
+	.get_sset_count		= rtl83xx_get_sset_count,
+
+	.port_enable		= rtl83xx_port_enable,
+	.port_disable		= rtl83xx_port_disable,
+
+	.set_ageing_time	= rtl83xx_set_l2aging,
+	.port_bridge_join	= rtl83xx_port_bridge_join,
+	.port_bridge_leave	= rtl83xx_port_bridge_leave,
+	.port_stp_state_set	= rtl83xx_port_stp_state_set,
+	.port_fast_age		= rtl930x_fast_age,
+
+	.port_vlan_filtering	= rtl83xx_vlan_filtering,
+	.port_vlan_prepare	= rtl83xx_vlan_prepare,
+	.port_vlan_add		= rtl83xx_vlan_add,
+	.port_vlan_del		= rtl83xx_vlan_del,
+
+	.port_fdb_add		= rtl83xx_port_fdb_add,
+	.port_fdb_del		= rtl83xx_port_fdb_del,
+	.port_fdb_dump		= rtl83xx_port_fdb_dump,
+};