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-rw-r--r--target/linux/starfive/patches-6.1/0074-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch88
1 files changed, 88 insertions, 0 deletions
diff --git a/target/linux/starfive/patches-6.1/0074-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch b/target/linux/starfive/patches-6.1/0074-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch
new file mode 100644
index 0000000000..6368e53d84
--- /dev/null
+++ b/target/linux/starfive/patches-6.1/0074-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch
@@ -0,0 +1,88 @@
+From 7492ebbdd926da258f9abea5c41a9f8c4ec48631 Mon Sep 17 00:00:00 2001
+From: Changhuang Liang <changhuang.liang@starfivetech.com>
+Date: Mon, 29 May 2023 05:15:01 -0700
+Subject: [PATCH 074/122] dt-bindings: phy: Add starfive,jh7110-dphy-rx
+
+StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
+a M31 IP. Add a binding for it.
+
+Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
+---
+ .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++
+ 1 file changed, 71 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
+@@ -0,0 +1,71 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive SoC MIPI D-PHY Rx Controller
++
++maintainers:
++ - Jack Zhu <jack.zhu@starfivetech.com>
++ - Changhuang Liang <changhuang.liang@starfivetech.com>
++
++description:
++ The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer
++ CSI camera data.
++
++properties:
++ compatible:
++ const: starfive,jh7110-dphy-rx
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: config clock
++ - description: reference clock
++ - description: escape mode transmit clock
++
++ clock-names:
++ items:
++ - const: cfg
++ - const: ref
++ - const: tx
++
++ resets:
++ items:
++ - description: DPHY_HW reset
++ - description: DPHY_B09_ALWAYS_ON reset
++
++ power-domains:
++ maxItems: 1
++
++ "#phy-cells":
++ const: 0
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - clock-names
++ - resets
++ - power-domains
++ - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ phy@19820000 {
++ compatible = "starfive,jh7110-dphy-rx";
++ reg = <0x19820000 0x10000>;
++ clocks = <&ispcrg 3>,
++ <&ispcrg 4>,
++ <&ispcrg 5>;
++ clock-names = "cfg", "ref", "tx";
++ resets = <&ispcrg 2>,
++ <&ispcrg 3>;
++ power-domains = <&dphy_pwrc 1>;
++ #phy-cells = <0>;
++ };