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path: root/target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch
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Diffstat (limited to 'target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch')
-rw-r--r--target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch536
1 files changed, 536 insertions, 0 deletions
diff --git a/target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch b/target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch
new file mode 100644
index 0000000000..75dd965c94
--- /dev/null
+++ b/target/linux/starfive/patches-6.6/0048-riscv-dts-starfive-Add-full-support-except-VIN-and-V.patch
@@ -0,0 +1,536 @@
+From a3d3f611f31fa2dca3deefa7cd443abca02e03fa Mon Sep 17 00:00:00 2001
+From: Hal Feng <hal.feng@starfivetech.com>
+Date: Tue, 11 Apr 2023 16:31:15 +0800
+Subject: [PATCH 048/116] riscv: dts: starfive: Add full support (except VIN
+ and VOUT) for JH7110 and VisionFive 2 board
+
+Merge all StarFive dts patches together except VIN and VOUT.
+
+Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
+---
+ .../jh7110-starfive-visionfive-2.dtsi | 199 +++++++++++++++
+ arch/riscv/boot/dts/starfive/jh7110.dtsi | 233 ++++++++++++++++++
+ 2 files changed, 432 insertions(+)
+
+--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+@@ -19,6 +19,8 @@
+ i2c6 = &i2c6;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
++ pcie0 = &pcie0;
++ pcie1 = &pcie1;
+ serial0 = &uart0;
+ };
+
+@@ -40,6 +42,33 @@
+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
++
++ pwmdac_codec: pwmdac-codec {
++ compatible = "linux,spdif-dit";
++ #sound-dai-cells = <0>;
++ };
++
++ sound-pwmdac {
++ compatible = "simple-audio-card";
++ simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ simple-audio-card,dai-link@0 {
++ reg = <0>;
++ format = "left_j";
++ bitclock-master = <&sndcpu0>;
++ frame-master = <&sndcpu0>;
++
++ sndcpu0: cpu {
++ sound-dai = <&pwmdac>;
++ };
++
++ codec {
++ sound-dai = <&pwmdac_codec>;
++ };
++ };
++ };
+ };
+
+ &dvp_clk {
+@@ -202,6 +231,24 @@
+ status = "okay";
+ };
+
++&i2srx {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2srx_pins>;
++ status = "okay";
++};
++
++&i2stx0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mclk_ext_pins>;
++ status = "okay";
++};
++
++&i2stx1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2stx1_pins>;
++ status = "okay";
++};
++
+ &mmc0 {
+ max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+@@ -235,6 +282,34 @@
+ status = "okay";
+ };
+
++&pcie0 {
++ perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
++ phys = <&pciephy0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie0_pins>;
++ status = "okay";
++};
++
++&pcie1 {
++ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
++ phys = <&pciephy1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
++};
++
++&pwm {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm_pins>;
++ status = "okay";
++};
++
++&pwmdac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwmdac_pins>;
++ status = "okay";
++};
++
+ &qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -340,6 +415,46 @@
+ };
+ };
+
++ i2srx_pins: i2srx-0 {
++ clk-sd-pins {
++ pinmux = <GPIOMUX(38, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_I2SRX_BCLK)>,
++ <GPIOMUX(63, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_I2SRX_LRCK)>,
++ <GPIOMUX(38, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_I2STX1_BCLK)>,
++ <GPIOMUX(63, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_I2STX1_LRCK)>,
++ <GPIOMUX(61, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_I2SRX_SDIN0)>;
++ input-enable;
++ };
++ };
++
++ i2stx1_pins: i2stx1-0 {
++ sd-pins {
++ pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
++ GPOEN_ENABLE,
++ GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ };
++ };
++
++ mclk_ext_pins: mclk-ext-0 {
++ mclk-ext-pins {
++ pinmux = <GPIOMUX(4, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_SYS_MCLK_EXT)>;
++ input-enable;
++ };
++ };
++
+ mmc0_pins: mmc0-0 {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+@@ -404,6 +519,86 @@
+ slew-rate = <0>;
+ };
+ };
++
++ pcie0_pins: pcie0-0 {
++ clkreq-pins {
++ pinmux = <GPIOMUX(27, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_NONE)>;
++ bias-pull-down;
++ drive-strength = <2>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++
++ wake-pins {
++ pinmux = <GPIOMUX(32, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_NONE)>;
++ bias-pull-up;
++ drive-strength = <2>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++
++ pcie1_pins: pcie1-0 {
++ clkreq-pins {
++ pinmux = <GPIOMUX(29, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_NONE)>;
++ bias-pull-down;
++ drive-strength = <2>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++
++ wake-pins {
++ pinmux = <GPIOMUX(21, GPOUT_LOW,
++ GPOEN_DISABLE,
++ GPI_NONE)>;
++ bias-pull-up;
++ drive-strength = <2>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm_pins: pwm-0 {
++ pwm-pins {
++ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
++ GPOEN_SYS_PWM0_CHANNEL0,
++ GPI_NONE)>,
++ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
++ GPOEN_SYS_PWM0_CHANNEL1,
++ GPI_NONE)>;
++ bias-disable;
++ drive-strength = <12>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++
++ pwmdac_pins: pwmdac-0 {
++ pwmdac-pins {
++ pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
++ GPOEN_ENABLE,
++ GPI_NONE)>,
++ <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
++ GPOEN_ENABLE,
++ GPI_NONE)>;
++ bias-disable;
++ drive-strength = <2>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
+
+ spi0_pins: spi0-0 {
+ mosi-pins {
+--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
+@@ -244,6 +244,7 @@
+ clock-output-names = "dvp_clk";
+ #clock-cells = <0>;
+ };
++
+ gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac0_rgmii_rxin";
+@@ -512,6 +513,43 @@
+ status = "disabled";
+ };
+
++ pwmdac: pwmdac@100b0000 {
++ compatible = "starfive,jh7110-pwmdac";
++ reg = <0x0 0x100b0000 0x0 0x1000>;
++ clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
++ <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
++ clock-names = "apb", "core";
++ resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
++ dmas = <&dma 22>;
++ dma-names = "tx";
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
++ i2srx: i2s@100e0000 {
++ compatible = "starfive,jh7110-i2srx";
++ reg = <0x0 0x100e0000 0x0 0x1000>;
++ clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
++ <&syscrg JH7110_SYSCLK_I2SRX_APB>,
++ <&syscrg JH7110_SYSCLK_MCLK>,
++ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
++ <&mclk_ext>,
++ <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
++ <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
++ <&i2srx_bclk_ext>,
++ <&i2srx_lrck_ext>;
++ clock-names = "i2sclk", "apb", "mclk",
++ "mclk_inner", "mclk_ext", "bclk",
++ "lrck", "bclk_ext", "lrck_ext";
++ resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
++ <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
++ dmas = <0>, <&dma 24>;
++ dma-names = "tx", "rx";
++ starfive,syscon = <&sys_syscon 0x18 0x2>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
+ usb0: usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ ranges = <0x0 0x0 0x10100000 0x100000>;
+@@ -736,6 +774,56 @@
+ status = "disabled";
+ };
+
++ i2stx0: i2s@120b0000 {
++ compatible = "starfive,jh7110-i2stx0";
++ reg = <0x0 0x120b0000 0x0 0x1000>;
++ clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
++ <&syscrg JH7110_SYSCLK_I2STX0_APB>,
++ <&syscrg JH7110_SYSCLK_MCLK>,
++ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
++ <&mclk_ext>;
++ clock-names = "i2sclk", "apb", "mclk",
++ "mclk_inner","mclk_ext";
++ resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
++ <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
++ dmas = <&dma 47>;
++ dma-names = "tx";
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
++ i2stx1: i2s@120c0000 {
++ compatible = "starfive,jh7110-i2stx1";
++ reg = <0x0 0x120c0000 0x0 0x1000>;
++ clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
++ <&syscrg JH7110_SYSCLK_I2STX1_APB>,
++ <&syscrg JH7110_SYSCLK_MCLK>,
++ <&syscrg JH7110_SYSCLK_MCLK_INNER>,
++ <&mclk_ext>,
++ <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
++ <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
++ <&i2stx_bclk_ext>,
++ <&i2stx_lrck_ext>;
++ clock-names = "i2sclk", "apb", "mclk",
++ "mclk_inner", "mclk_ext", "bclk",
++ "lrck", "bclk_ext", "lrck_ext";
++ resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
++ <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
++ dmas = <&dma 48>;
++ dma-names = "tx";
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
++ pwm: pwm@120d0000 {
++ compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
++ reg = <0x0 0x120d0000 0x0 0x10000>;
++ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
++ resets = <&syscrg JH7110_SYSRST_PWM_APB>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
+ sfctemp: temperature-sensor@120e0000 {
+ compatible = "starfive,jh7110-temp";
+ reg = <0x0 0x120e0000 0x0 0x10000>;
+@@ -811,6 +899,26 @@
+ #gpio-cells = <2>;
+ };
+
++ timer@13050000 {
++ compatible = "starfive,jh7110-timer";
++ reg = <0x0 0x13050000 0x0 0x10000>;
++ interrupts = <69>, <70>, <71>, <72>;
++ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
++ <&syscrg JH7110_SYSCLK_TIMER0>,
++ <&syscrg JH7110_SYSCLK_TIMER1>,
++ <&syscrg JH7110_SYSCLK_TIMER2>,
++ <&syscrg JH7110_SYSCLK_TIMER3>;
++ clock-names = "apb", "ch0", "ch1",
++ "ch2", "ch3";
++ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
++ <&syscrg JH7110_SYSRST_TIMER0>,
++ <&syscrg JH7110_SYSRST_TIMER1>,
++ <&syscrg JH7110_SYSRST_TIMER2>,
++ <&syscrg JH7110_SYSRST_TIMER3>;
++ reset-names = "apb", "ch0", "ch1",
++ "ch2", "ch3";
++ };
++
+ watchdog@13070000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+@@ -1011,6 +1119,32 @@
+ #power-domain-cells = <1>;
+ };
+
++ csi2rx: csi-bridge@19800000 {
++ compatible = "starfive,jh7110-csi2rx";
++ reg = <0x0 0x19800000 0x0 0x10000>;
++ clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
++ <&ispcrg JH7110_ISPCLK_VIN_APB>,
++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
++ clock-names = "sys_clk", "p_clk",
++ "pixel_if0_clk", "pixel_if1_clk",
++ "pixel_if2_clk", "pixel_if3_clk";
++ resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
++ <&ispcrg JH7110_ISPRST_VIN_APB>,
++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
++ reset-names = "sys", "reg_bank",
++ "pixel_if0", "pixel_if1",
++ "pixel_if2", "pixel_if3";
++ phys = <&csi_phy>;
++ phy-names = "dphy";
++ status = "disabled";
++ };
++
+ ispcrg: clock-controller@19810000 {
+ compatible = "starfive,jh7110-ispcrg";
+ reg = <0x0 0x19810000 0x0 0x10000>;
+@@ -1028,6 +1162,19 @@
+ power-domains = <&pwrc JH7110_PD_ISP>;
+ };
+
++ csi_phy: phy@19820000 {
++ compatible = "starfive,jh7110-dphy-rx";
++ reg = <0x0 0x19820000 0x0 0x10000>;
++ clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
++ <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
++ <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
++ clock-names = "cfg", "ref", "tx";
++ resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
++ <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
++ power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
++ #phy-cells = <0>;
++ };
++
+ voutcrg: clock-controller@295c0000 {
+ compatible = "starfive,jh7110-voutcrg";
+ reg = <0x0 0x295c0000 0x0 0x10000>;
+@@ -1045,5 +1192,91 @@
+ #reset-cells = <1>;
+ power-domains = <&pwrc JH7110_PD_VOUT>;
+ };
++
++ pcie0: pcie@940000000 {
++ compatible = "starfive,jh7110-pcie";
++ reg = <0x9 0x40000000 0x0 0x1000000>,
++ <0x0 0x2b000000 0x0 0x100000>;
++ reg-names = "cfg", "apb";
++ linux,pci-domain = <0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
++ interrupts = <56>;
++ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
++ msi-controller;
++ device_type = "pci";
++ starfive,stg-syscon = <&stg_syscon>;
++ bus-range = <0x0 0xff>;
++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
++ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
++ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
++ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
++ clock-names = "noc", "tl", "axi_mst0", "apb";
++ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
++ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
++ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
++ <&stgcrg JH7110_STGRST_PCIE0_APB>;
++ reset-names = "mst0", "slv0", "slv", "brg",
++ "core", "apb";
++ status = "disabled";
++
++ pcie_intc0: interrupt-controller {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ };
++ };
++
++ pcie1: pcie@9c0000000 {
++ compatible = "starfive,jh7110-pcie";
++ reg = <0x9 0xc0000000 0x0 0x1000000>,
++ <0x0 0x2c000000 0x0 0x100000>;
++ reg-names = "cfg", "apb";
++ linux,pci-domain = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
++ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
++ interrupts = <57>;
++ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
++ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
++ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
++ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
++ msi-controller;
++ device_type = "pci";
++ starfive,stg-syscon = <&stg_syscon>;
++ bus-range = <0x0 0xff>;
++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
++ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
++ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
++ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
++ clock-names = "noc", "tl", "axi_mst0", "apb";
++ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
++ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
++ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
++ <&stgcrg JH7110_STGRST_PCIE1_APB>;
++ reset-names = "mst0", "slv0", "slv", "brg",
++ "core", "apb";
++ status = "disabled";
++
++ pcie_intc1: interrupt-controller {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ };
++ };
+ };
+ };
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