1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
|
From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 5 Aug 2020 14:19:23 +0200
Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
scale the Cache frequency when the CPU frequency is changed. This
devfreq driver register with the cpu notifier and scale the Cache
based on the max Freq across all core as the CPU cache is shared across
all of them. If provided this also scale the voltage of the regulator
attached to the CPU cache. The scaling logic is based on the CPU freq
and the 3 scaling interval are set by the device dts.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/devfreq/Kconfig | 11 ++
drivers/devfreq/Makefile | 1 +
drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/devfreq/krait-cache-devfreq.c
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
This adds the DEVFREQ driver for the MBUS controller in some
Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
+config ARM_KRAIT_CACHE_DEVFREQ
+ tristate "Scaling support for Krait CPU Cache Devfreq"
+ depends on ARCH_QCOM || COMPILE_TEST
+ select DEVFREQ_GOV_PASSIVE
+ help
+ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
+
+ The driver register with the cpufreq notifier and find the right frequency
+ based on the max frequency across all core and the range set in the device
+ dts. If provided this scale also the regulator attached to the l2 cache.
+
source "drivers/devfreq/event/Kconfig"
endif # PM_DEVFREQ
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
# DEVFREQ Event Drivers
obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
--- /dev/null
+++ b/drivers/devfreq/krait-cache-devfreq.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cpufreq.h>
+#include <linux/devfreq.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_opp.h>
+
+#include "governor.h"
+
+struct krait_cache_data {
+ struct clk *clk;
+ unsigned long idle_freq;
+ int token;
+};
+
+static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
+ struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
+ void *data, bool scaling_down)
+{
+ struct krait_cache_data *kdata;
+ unsigned long old_freq, freq;
+ unsigned long idle_freq;
+ struct clk *clk;
+ int ret;
+
+ kdata = dev_get_drvdata(dev);
+ idle_freq = kdata->idle_freq;
+ clk = kdata->clk;
+
+ old_freq = dev_pm_opp_get_freq(old_opp);
+ freq = dev_pm_opp_get_freq(opp);
+
+ /*
+ * Set to idle bin if switching from normal to high bin
+ * or vice versa. It has been notice that a bug is triggered
+ * in cache scaling when more than one bin is scaled, to fix
+ * this we first need to transition to the base rate and then
+ * to target rate
+ */
+ if (likely(freq != idle_freq && old_freq != idle_freq)) {
+ ret = clk_set_rate(clk, idle_freq);
+ if (ret)
+ return ret;
+ }
+
+ return clk_set_rate(clk, freq);
+};
+
+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+ struct krait_cache_data *data = dev_get_drvdata(dev);
+
+ *freq = clk_get_rate(data->clk);
+
+ return 0;
+};
+
+static int krait_cache_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct dev_pm_opp *opp;
+
+ opp = dev_pm_opp_find_freq_ceil(dev, freq);
+ if (unlikely(IS_ERR(opp)))
+ return PTR_ERR(opp);
+
+ dev_pm_opp_put(opp);
+
+ return dev_pm_opp_set_rate(dev, *freq);
+};
+
+static int krait_cache_get_dev_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct krait_cache_data *data = dev_get_drvdata(dev);
+
+ stat->busy_time = 0;
+ stat->total_time = 0;
+ stat->current_frequency = clk_get_rate(data->clk);
+
+ return 0;
+};
+
+static struct devfreq_dev_profile krait_cache_devfreq_profile = {
+ .target = krait_cache_target,
+ .get_dev_status = krait_cache_get_dev_status,
+ .get_cur_freq = krait_cache_get_cur_freq
+};
+
+static struct devfreq_passive_data devfreq_gov_data = {
+ .parent_type = CPUFREQ_PARENT_DEV,
+};
+
+static int krait_cache_probe(struct platform_device *pdev)
+{
+ struct dev_pm_opp_config config = { };
+ struct device *dev = &pdev->dev;
+ struct krait_cache_data *data;
+ struct devfreq *devfreq;
+ struct dev_pm_opp *opp;
+ struct clk *clk;
+ int ret, token;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ clk = devm_clk_get(dev, "l2");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ config.regulator_names = (const char *[]){ "l2", NULL };
+ config.clk_names = (const char *[]){ "l2", NULL };
+ config.config_clks = krait_cache_config_clk;
+
+ token = dev_pm_opp_set_config(dev, &config);
+ if (token < 0)
+ return token;
+
+ ret = devm_pm_opp_of_add_table(dev);
+ if (ret)
+ goto free_opp;
+
+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
+ if (IS_ERR(opp)) {
+ ret = PTR_ERR(opp);
+ goto free_opp;
+ }
+ dev_pm_opp_put(opp);
+
+ data->token = token;
+ data->clk = clk;
+ dev_set_drvdata(dev, data);
+ devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
+ if (IS_ERR(devfreq)) {
+ ret = PTR_ERR(devfreq);
+ goto free_opp;
+ }
+
+ return 0;
+
+free_opp:
+ dev_pm_opp_clear_config(token);
+ return ret;
+};
+
+static int krait_cache_remove(struct platform_device *pdev)
+{
+ struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
+
+ dev_pm_opp_clear_config(data->token);
+
+ return 0;
+};
+
+static const struct of_device_id krait_cache_match_table[] = {
+ { .compatible = "qcom,krait-cache" },
+ {}
+};
+
+static struct platform_driver krait_cache_driver = {
+ .probe = krait_cache_probe,
+ .remove = krait_cache_remove,
+ .driver = {
+ .name = "krait-cache-scaling",
+ .of_match_table = krait_cache_match_table,
+ },
+};
+module_platform_driver(krait_cache_driver);
+
+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL v2");
|
