soc/intel/adl/chip.h: Convert all camel case variables to snake case

coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.

By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.

During renaming process, this patch also removes unused variables
listed below:
-> SataEnable   // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used

Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.

Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

42 files changed, 297 insertions, 292 deletions

diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 2f79831fe625..97fa9905e4b4 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -30,8 +30,8 @@ chip soc/intel/alderlake
 		},
 	}"
 
-	register "SaGv" = "SaGv_Enabled"
-	register "TcssAuxOri" = "1"
+	register "sagv" = "SaGv_Enabled"
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2_C1
@@ -43,7 +43,7 @@ chip soc/intel/alderlake
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Disable M.2 WWAN
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
@@ -52,7 +52,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
                 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
                 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
         }"
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 9934dee8e3a9..67b9f95b14a6 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -22,13 +22,13 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index 0d36ddf6c825..20defe7505ab 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -22,13 +22,13 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb
index 08550d254240..8729b3a59929 100644
--- a/src/mainboard/google/brya/variants/banshee/overridetree.cb
+++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb
@@ -36,7 +36,7 @@ chip soc/intel/alderlake
 	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)"
 
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
@@ -45,7 +45,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 	}"
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 9eb8bb2adbf1..a57289b46a9b 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/alderlake
 	register "tcc_offset" = "10"     # TCC of 90
 
 	# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
@@ -41,7 +41,7 @@ chip soc/intel/alderlake
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
@@ -50,12 +50,12 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
@@ -68,13 +68,13 @@ chip soc/intel/alderlake
 	register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
-        # FIVR RFI Spread Spectrum 1.5%
-        register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+	# FIVR RFI Spread Spectrum 1.5%
+	register "fivr_spread_spectrum" = "FIVR_SS_1_5"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
index 9628b447b025..4d30b8e23738 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c
@@ -146,7 +146,7 @@ void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
 
 	/* voltage unit is milliVolts and current is in milliAmps */
 	soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000);
-	conf->PsysPmax = soc_config->psys_pmax;
+	conf->platform_pmax = soc_config->psys_pmax;
 
 	soc_config->tdp_pl2_override = pl2;
 	soc_config->tdp_psyspl2 = psyspl2;
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index d67fd4b7a212..9ceda11873d9 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/alderlake
 	register "tcc_offset" = "10"     # TCC of 90
 
 	# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
@@ -37,7 +37,7 @@ chip soc/intel/alderlake
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
@@ -46,12 +46,12 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
@@ -64,13 +64,13 @@ chip soc/intel/alderlake
 	register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
 	# FIVR RFI Spread Spectrum 1.5%
-	register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+	register "fivr_spread_spectrum" = "FIVR_SS_1_5"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index d85e230e5d35..c4c4fb3c58c1 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/alderlake
 	register "s0ix_enable" = "1"
 
 	# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	# eMMC HS400
 	register "emmc_enable_hs400_mode" = "1"
@@ -32,7 +32,7 @@ chip soc/intel/alderlake
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
@@ -41,22 +41,22 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/brask/variant.c b/src/mainboard/google/brya/variants/brask/variant.c
index 8e3578c84b65..04105db2ea71 100644
--- a/src/mainboard/google/brya/variants/brask/variant.c
+++ b/src/mainboard/google/brya/variants/brask/variant.c
@@ -6,5 +6,6 @@
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S));
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							NAU88L25B_I2S));
 }
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index f621b127aa67..63ffe2f4cb44 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -35,9 +35,9 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
-	register "PsysPmax" = "145"
+	register "platform_pmax" = "145"
 
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port
 
diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c
index 8d4471ba2ea2..e9ae51ea0feb 100644
--- a/src/mainboard/google/brya/variants/brya0/variant.c
+++ b/src/mainboard/google/brya/variants/brya0/variant.c
@@ -6,5 +6,6 @@
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW));
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98373_ALC5682_SNDW));
 }
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
index e6a2d7e54cec..6a12c704d856 100644
--- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -35,9 +35,9 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
-	register "PsysPmax" = "145"
+	register "platform_pmax" = "145"
 
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A MLB Port
 
diff --git a/src/mainboard/google/brya/variants/brya4es/variant.c b/src/mainboard/google/brya/variants/brya4es/variant.c
index 8d4471ba2ea2..e9ae51ea0feb 100644
--- a/src/mainboard/google/brya/variants/brya4es/variant.c
+++ b/src/mainboard/google/brya/variants/brya4es/variant.c
@@ -6,5 +6,6 @@
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW));
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98373_ALC5682_SNDW));
 }
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index acd96dd6b44d..a89ad952439b 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -16,7 +16,7 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
 	# bypass rails implemented.
@@ -30,7 +30,7 @@ chip soc/intel/alderlake
 
 	register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
@@ -39,7 +39,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 	}"
diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c
index 8b270de04e2b..b0bf99ac560c 100644
--- a/src/mainboard/google/brya/variants/felwinter/variant.c
+++ b/src/mainboard/google/brya/variants/felwinter/variant.c
@@ -15,6 +15,6 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 	if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) {
 		config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19;
 		config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20;
-		config->TcssAuxOri = 0x10;
+		config->tcss_aux_ori = 0x10;
 	}
 }
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 0d8b49b47e71..07458e9a8d63 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -21,15 +21,15 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "PsysPmax" = "143"
-	register "TcssAuxOri" = "1"
+	register "sagv" = "SaGv_Enabled"
+	register "platform_pmax" = "143"
+	register "tcss_aux_ori" = "1"
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 	register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram
diff --git a/src/mainboard/google/brya/variants/gimble/variant.c b/src/mainboard/google/brya/variants/gimble/variant.c
index 96ccf88ae7b6..48a3f21909a0 100644
--- a/src/mainboard/google/brya/variants/gimble/variant.c
+++ b/src/mainboard/google/brya/variants/gimble/variant.c
@@ -12,6 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO,
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
 							MAX98390_ALC5682I_I2S_SSP1));
 }
diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
index 1ab9a7e6bef5..3df3e024a756 100644
--- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
@@ -21,15 +21,15 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "PsysPmax" = "143"
-	register "TcssAuxOri" = "1"
+	register "sagv" = "SaGv_Enabled"
+	register "platform_pmax" = "143"
+	register "tcss_aux_ori" = "1"
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 	register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram
diff --git a/src/mainboard/google/brya/variants/gimble4es/variant.c b/src/mainboard/google/brya/variants/gimble4es/variant.c
index 96ccf88ae7b6..48a3f21909a0 100644
--- a/src/mainboard/google/brya/variants/gimble4es/variant.c
+++ b/src/mainboard/google/brya/variants/gimble4es/variant.c
@@ -12,6 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO,
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
 							MAX98390_ALC5682I_I2S_SSP1));
 }
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb
index 39cca42b4fbc..41c3cf2c8b28 100644
--- a/src/mainboard/google/brya/variants/kano/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kano/overridetree.cb
@@ -17,7 +17,7 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# GPE configuration
 	register "pmc_gpe0_dw1" = "GPP_D"
diff --git a/src/mainboard/google/brya/variants/kano/variant.c b/src/mainboard/google/brya/variants/kano/variant.c
index 0db43aa06d8a..86c65c7ea7d2 100644
--- a/src/mainboard/google/brya/variants/kano/variant.c
+++ b/src/mainboard/google/brya/variants/kano/variant.c
@@ -12,5 +12,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S));
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98373_NAU88L25B_I2S));
 }
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb
index f850d11fe9a8..4168c4f7ef2b 100644
--- a/src/mainboard/google/brya/variants/kinox/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb
@@ -31,7 +31,7 @@ chip soc/intel/alderlake
 	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"            # Disable Port2
 
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
@@ -40,7 +40,7 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 	}"
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index 9cb27e88d798..50c98ceed76b 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -7,7 +7,7 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
index d5d062103c0e..c2eac2d97a93 100644
--- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb
@@ -7,7 +7,7 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 6b8882224860..88323813f886 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -23,14 +23,15 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "MaxDramSpeed" = "3733"
+	register "sagv" = "SaGv_Enabled"
+	register "max_dram_speed" = "3733"
+
 	# Acoustic settings
-  	register "AcousticNoiseMitigation" = "1"
-  	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-  	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-  	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-  	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
index d6400c2462c1..940c63f0053a 100644
--- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
@@ -23,14 +23,15 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "MaxDramSpeed" = "3733"
+	register "sagv" = "SaGv_Enabled"
+	register "max_dram_speed" = "3733"
+
 	# Acoustic settings
-  	register "AcousticNoiseMitigation" = "1"
-  	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-  	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-  	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-  	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 3f9c81d4dd94..a44cb40521bf 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -31,17 +31,17 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "CnviBtAudioOffload" = "true"
+	register "sagv" = "SaGv_Enabled"
+	register "cnvi_bt_audio_offload" = "true"
 	# FIVR RFI Spread Spectrum 6%
-	register "FivrSpreadSpectrum" = "FIVR_SS_6"
+	register "fivr_spread_spectrum" = "FIVR_SS_6"
 
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 0c9c174fa3e8..9c51512c57ea 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -31,17 +31,17 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
-	register "CnviBtAudioOffload" = "true"
+	register "sagv" = "SaGv_Enabled"
+	register "cnvi_bt_audio_offload" = "true"
 	# FIVR RFI Spread Spectrum 6%
-	register "FivrSpreadSpectrum" = "FIVR_SS_6"
+	register "fivr_spread_spectrum" = "FIVR_SS_6"
 
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index ac83e583afcf..75672ae362b5 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -41,11 +41,11 @@ fw_config
 end
 chip soc/intel/alderlake
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
@@ -59,9 +59,9 @@ chip soc/intel/alderlake
 		.v1p05_icc_max_ma = 500,
 		.vnn_sx_voltage_mv = 1250,
 	}"
-	register "TcssAuxOri" = "1"
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable Port 1
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# DB USB2_C1
@@ -115,7 +115,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index 11d572f96f5a..0de40448c5c2 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -40,11 +40,12 @@ fw_config
 end
 chip soc/intel/alderlake
 	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
-	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
-	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "acoustic_noise_mitigation" = "1"
+	register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
+	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
+
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
@@ -58,9 +59,10 @@ chip soc/intel/alderlake
 		.v1p05_icc_max_ma = 500,
 		.vnn_sx_voltage_mv = 1250,
 	}"
-	register "TcssAuxOri" = "1"
+
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable Port 1
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# DB USB2_C1
@@ -107,7 +109,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb
index f80f5d67fcb7..ddafa15dff9a 100644
--- a/src/mainboard/google/brya/variants/taniks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb
@@ -49,11 +49,11 @@ chip soc/intel/alderlake
 		.v1p05_icc_max_ma = 500,
 		.vnn_sx_voltage_mv = 1250,
 	}"
-	register "TcssAuxOri" = "1"
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
-	register "PsysPmax" = "145"
+	register "platform_pmax" = "145"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable Port 1
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# DB USB2_C1
@@ -94,7 +94,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 5f2780e16159..4199cec6a63f 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -51,10 +51,10 @@ chip soc/intel/alderlake
 	}"
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)"  # USB2_C3
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# I2C Port Config
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index f54753b7afd7..d8bcdbdc7297 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -21,9 +21,9 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
-	register "TcssAuxOri" = "1"
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
 
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2_C1
diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c
index fef03f2b3ee5..e21ab5a91ce1 100644
--- a/src/mainboard/google/brya/variants/volmar/variant.c
+++ b/src/mainboard/google/brya/variants/volmar/variant.c
@@ -6,5 +6,6 @@
 
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
-	config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S));
+	config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
+							MAX98373_NAU88L25B_I2S));
 }
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 9bd99b18f762..a4f85947a9c9 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -11,10 +11,10 @@ chip soc/intel/alderlake
 	# FSP configuration
 
 	# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	# Sagv Configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
@@ -72,7 +72,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Hybrid storage mode
-	register "HybridStorageMode" = "1"
+	register "hybrid_storage_mode" = "1"
 
 	# Enable CPU PCIE RP 1 using CLK 0
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{
@@ -95,16 +95,16 @@ chip soc/intel/alderlake
 		.flags = PCIE_RP_LTR | PCIE_RP_AER,
 	}"
 
-	register "SataSalpSupport" = "1"
+	register "sata_salp_support" = "1"
 
-	register "SataPortsEnable" = "{
+	register "sata_ports_enable" = "{
 		[0] = 1,
 		[1] = 1,
 		[2] = 1,
 		[3] = 1,
 	}"
 
-	register "SataPortsDevSlp" = "{
+	register "sata_ports_dev_slp" = "{
 		[0] = 1,
 		[1] = 1,
 		[2] = 1,
@@ -112,19 +112,19 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable EDP in PortA
-	register "DdiPortAConfig" = "1"
+	register "ddi_portA_config" = "1"
 	# Enable HDMI in Port B
 	register "ddi_ports_config" = "{
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
 	# TCSS USB3
-	register "TcssAuxOri" = "0"
+	register "tcss_aux_ori" = "0"
 
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
@@ -133,40 +133,40 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiCsMode" = "{
+	register "serial_io_gspi_cs_mode" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 0,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoGSpiCsState" = "{
+	register "serial_io_gspi_cs_state" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 0,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
-	register "CnviBtAudioOffload" = "true"
+	register "cnvi_bt_audio_offload" = "true"
 
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index c637ec3d5499..4a41df61f76b 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -36,10 +36,10 @@ chip soc/intel/alderlake
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
 
 	# Sagv Configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# Enable CNVi Bluetooth
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"
@@ -80,7 +80,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Hybrid storage mode
-	register "HybridStorageMode" = "1"
+	register "hybrid_storage_mode" = "1"
 
 	# Enable CPU PCIE RP 1 using CLK 0
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{
@@ -90,18 +90,18 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable EDP in PortA
-	register "DdiPortAConfig" = "1"
+	register "ddi_portA_config" = "1"
 	# Enable HDMI in Port B
 	register "ddi_ports_config" = "{
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
 	# TCSS USB3
-	register "TcssAuxOri" = "0"
+	register "tcss_aux_ori" = "0"
 
 	register "s0ix_enable" = "1"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
@@ -110,38 +110,38 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiCsMode" = "{
+	register "serial_io_gspi_cs_mode" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 1,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoGSpiCsState" = "{
+	register "serial_io_gspi_cs_state" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 0,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index f7da2d16c885..d38c010704b9 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -11,10 +11,10 @@ chip soc/intel/alderlake
 	# FSP configuration
 
 	# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	# Sagv Configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# eMMC HS400
 	register "emmc_enable_hs400_mode" = "1"
@@ -54,16 +54,16 @@ chip soc/intel/alderlake
 		.flags = PCIE_RP_CLK_REQ_DETECT,
 	}"
 
-	register "SataSalpSupport" = "1"
+	register "sata_salp_support" = "1"
 
-	register "SataPortsEnable" = "{
+	register "sata_ports_enable" = "{
 		[0] = 1,
 		[1] = 1,
 		[2] = 1,
 		[3] = 1,
 	}"
 
-	register "SataPortsDevSlp" = "{
+	register "sata_ports_dev_slp" = "{
 		[0] = 1,
 		[1] = 1,
 		[2] = 1,
@@ -71,19 +71,19 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable EDP in PortA
-	register "DdiPortAConfig" = "1"
+	register "ddi_portA_config" = "1"
 	# Enable HDMI in Port B
 	register "ddi_ports_config" = "{
 		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 	}"
 
 	# TCSS USB3
-	register "TcssAuxOri" = "4"
+	register "tcss_aux_ori" = "4"
 	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
 
 	register "s0ix_enable" = "1"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci,
 		[PchSerialIoIndexI2C1] = PchSerialIoPci,
 		[PchSerialIoIndexI2C2] = PchSerialIoPci,
@@ -92,40 +92,40 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiCsMode" = "{
+	register "serial_io_gspi_cs_mode" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 0,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoGSpiCsState" = "{
+	register "serial_io_gspi_cs_state" = "{
 		[PchSerialIoIndexGSPI0] = 0,
 		[PchSerialIoIndexGSPI1] = 0,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
-	register "CnviBtAudioOffload" = "true"
+	register "cnvi_bt_audio_offload" = "true"
 
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 63d3da423b35..e68afe24f38d 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -13,14 +13,14 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# TCSS
-	register "TcssAuxOri" = "1"
+	register "tcss_aux_ori" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
 
 	# Enable CNVi Bluetooth
-	register "CnviBtCore" = "true"
+	register "cnvi_bt_core" = "true"
 
 	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "sagv" = "SaGv_Enabled"
 
 	# S0ix enable
 	register "s0ix_enable" = "1"
@@ -65,16 +65,15 @@ chip soc/intel/alderlake
 	}"
 
 	# Enable SATA
-	register "SataEnable" = "1"
-	register "SataMode" = "0"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "0"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsDevSlp[0]" = "0"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsEnableDitoConfig[1]" = "1"
+	register "sata_mode" = "0"
+	register "sata_salp_support" = "1"
+	register "sata_ports_enable[0]" = "0"
+	register "sata_ports_enable[1]" = "1"
+	register "sata_ports_dev_slp[0]" = "0"
+	register "sata_ports_dev_slp[1]" = "1"
+	register "sata_ports_enable_dito_config[1]" = "1"
 
-	register "SerialIoI2cMode" = "{
+	register "serial_io_i2c_mode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
@@ -83,36 +82,36 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 	}"
 
-	register "SerialIoGSpiMode" = "{
+	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
-	register "SerialIoGSpiCsMode" = "{
+	register "serial_io_gspi_cs_mode" = "{
 		[PchSerialIoIndexGSPI0] = 1,
 	}"
 
-	register "SerialIoGSpiCsState" = "{
+	register "serial_io_gspi_cs_state" = "{
 		[PchSerialIoIndexGSPI0] = 1,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
 	# HD Audio
-	register "PchHdaDspEnable" = "1"
-	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
-	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
-	register "PchHdaIDispCodecEnable" = "1"
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
 
 	# DP port
-	register "DdiPortAConfig" = "1"	# eDP
-	register "DdiPortBConfig" = "0"
+	register "ddi_portA_config" = "1"	# eDP
+	register "ddi_portB_config" = "0"
 
 	# Enable Display Port Configuration
 	register "ddi_ports_config" = "{
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index 7b094e4fc03f..8476c482ebe1 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -23,19 +23,19 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
 
-	register "SataSalpSupport" = "1"
+	register "sata_salp_support" = "1"
 
-	register "SataPortsEnable" = "{
+	register "sata_ports_enable" = "{
 		[0] = 1,
 		[1] = 1,
 	}"
 
-	register "SataPortsDevSlp" = "{
+	register "sata_ports_dev_slp" = "{
 		[0] = 1,
 		[1] = 1,
 	}"
 
-	register "SerialIoUartMode" = "{
+	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index e77a3dc114c2..e7e2f208058b 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -195,9 +195,9 @@ struct soc_intel_alderlake_config {
 	/* Enable S0iX support */
 	int s0ix_enable;
 	/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
-	uint8_t TcssD3HotDisable;
+	uint8_t tcss_d3_hot_disable;
 	/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
-	uint8_t TcssD3ColdDisable;
+	uint8_t tcss_d3_cold_disable;
 	/* Enable DPTF support */
 	int dptf_enable;
 
@@ -227,7 +227,7 @@ struct soc_intel_alderlake_config {
 		SaGv_FixedPoint2,
 		SaGv_FixedPoint3,
 		SaGv_Enabled,
-	} SaGv;
+	} sagv;
 
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
@@ -243,31 +243,31 @@ struct soc_intel_alderlake_config {
 	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 
 	/* SATA related */
-	uint8_t SataEnable;
-	uint8_t SataMode;
-	uint8_t SataSalpSupport;
-	uint8_t SataPortsEnable[8];
-	uint8_t SataPortsDevSlp[8];
+	uint8_t sata_mode;
+	uint8_t sata_salp_support;
+	uint8_t sata_ports_enable[8];
+	uint8_t sata_ports_dev_slp[8];
 
 	/*
 	 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
 	 * Default 0. Setting this to 1 disables the SATA Power Optimizer.
 	 */
-	uint8_t SataPwrOptimizeDisable;
+	uint8_t sata_pwr_optimize_disable;
 
 	/*
 	 * SATA Port Enable Dito Config.
 	 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
 	 */
-	uint8_t SataPortsEnableDitoConfig[8];
+	uint8_t sata_ports_enable_dito_config[8];
 
 	/* SataPortsDmVal is the DITO multiplier. Default is 15. */
-	uint8_t SataPortsDmVal[8];
+	uint8_t sata_ports_dm_val[8];
+
 	/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
-	uint16_t SataPortsDitoVal[8];
+	uint16_t sata_ports_dito_val[8];
 
 	/* Audio related */
-	uint8_t PchHdaDspEnable;
+	uint8_t pch_hda_dsp_enable;
 
 	/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
 	enum {
@@ -275,15 +275,15 @@ struct soc_intel_alderlake_config {
 		HDA_TMODE_4T = 2,
 		HDA_TMODE_8T = 3,
 		HDA_TMODE_16T = 4,
-	} PchHdaIDispLinkTmode;
+	} pch_hda_idisp_link_tmode;
 
 	/* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
 	enum {
 		HDA_LINKFREQ_48MHZ = 3,
 		HDA_LINKFREQ_96MHZ = 4,
-	} PchHdaIDispLinkFrequency;
+	} pch_hda_idisp_link_frequency;
 
-	bool PchHdaIDispCodecEnable;
+	bool pch_hda_idisp_codec_enable;
 
 	struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
 	struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
@@ -311,8 +311,8 @@ struct soc_intel_alderlake_config {
 		IGD_SM_52MB = 0xFC,
 		IGD_SM_56MB = 0xFD,
 		IGD_SM_60MB = 0xFE,
-	} IgdDvmt50PreAlloc;
-	uint8_t SkipExtGfxScan;
+	} igd_dvmt50_pre_alloc;
+	uint8_t skip_ext_gfx_scan;
 
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
@@ -328,21 +328,21 @@ struct soc_intel_alderlake_config {
 	 * PchSerialIoLegacyUart,
 	 * PchSerialIoSkipInit
 	 */
-	uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
-	uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
-	uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+	uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+	uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+	uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
 	/*
 	 * GSPIn Default Chip Select Mode:
 	 * 0:Hardware Mode,
 	 * 1:Software Mode
 	 */
-	uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+	uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 	/*
 	 * GSPIn Default Chip Select State:
 	 * 0: Low,
 	 * 1: High
 	 */
-	uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+	uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 
 	/* Debug interface selection */
 	enum {
@@ -357,10 +357,10 @@ struct soc_intel_alderlake_config {
 	uint8_t pch_isclk;
 
 	/* CNVi BT Core Enable/Disable */
-	bool CnviBtCore;
+	bool cnvi_bt_core;
 
 	/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
-	bool CnviBtAudioOffload;
+	bool cnvi_bt_audio_offload;
 
 	/*
 	 * These GPIOs will be programmed by the IOM to handle biasing of the
@@ -379,10 +379,7 @@ struct soc_intel_alderlake_config {
 	 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
 	 * on the motherboard.
 	 */
-	uint16_t TcssAuxOri;
-
-	/* Connect Topology Command timeout value */
-	uint16_t ITbtConnectTopologyTimeoutInMs;
+	uint16_t tcss_aux_ori;
 
 	/*
 	 * Override GPIO PM configuration:
@@ -408,8 +405,8 @@ struct soc_intel_alderlake_config {
 	 * Port config
 	 * 0:Disabled, 1:eDP, 2:MIPI DSI
 	 */
-	uint8_t DdiPortAConfig;
-	uint8_t DdiPortBConfig;
+	uint8_t ddi_portA_config;
+	uint8_t ddi_portB_config;
 
 	/* Enable(1)/Disable(0) HPD/DDC */
 	uint8_t ddi_ports_config[DDI_PORT_COUNT];
@@ -417,7 +414,7 @@ struct soc_intel_alderlake_config {
 	/* Hybrid storage mode enable (1) / disable (0)
 	 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
 	 * accordingly */
-	uint8_t HybridStorageMode;
+	uint8_t hybrid_storage_mode;
 
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 	/* eMMC HS400 mode */
@@ -441,19 +438,19 @@ struct soc_intel_alderlake_config {
 	 * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
 	 * Default 0. Setting this to 1 disables the DMI Power Optimizer.
 	 */
-	uint8_t DmiPwrOptimizeDisable;
+	uint8_t dmi_power_optimize_disable;
 
 	/*
 	 * Enable(1)/Disable(0) CPU Replacement check.
 	 * Default 0. Setting this to 1 to check CPU replacement.
 	 */
-	uint8_t CpuReplacementCheck;
+	uint8_t cpu_replacement_check;
 
 	/* ISA Serial Base selection. */
 	enum {
 		ISA_SERIAL_BASE_ADDR_3F8,
 		ISA_SERIAL_BASE_ADDR_2F8,
-	} IsaSerialUartBase;
+	} isa_serial_uart_base;
 
 	/* structure containing various settings for PCH FIVRs */
 	struct {
@@ -480,7 +477,7 @@ struct soc_intel_alderlake_config {
 	*/
 	struct vr_config domain_vr_config[NUM_VR_DOMAINS];
 
-	uint16_t MaxDramSpeed;
+	uint16_t max_dram_speed;
 
 	enum {
 		SLP_S3_ASSERTION_DEFAULT,
@@ -532,7 +529,7 @@ struct soc_intel_alderlake_config {
 	} pch_reset_power_cycle_duration;
 
 	/* Platform Power Pmax */
-	uint16_t PsysPmax;
+	uint16_t platform_pmax;
 	/*
 	 * FivrRfiFrequency
 	 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
@@ -541,7 +538,7 @@ struct soc_intel_alderlake_config {
 	 *   0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock
 	 *   0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock
 	 */
-	uint32_t FivrRfiFrequency;
+	uint32_t fivr_rfi_frequency;
 	/*
 	 * FivrSpreadSpectrum
 	 * Set the Spread Spectrum Range.
@@ -549,16 +546,16 @@ struct soc_intel_alderlake_config {
 	 *   Each Range is translated to an encoded value for FIVR register.
 	 *   0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
 	 */
-	uint8_t FivrSpreadSpectrum;
+	uint8_t fivr_spread_spectrum;
 	/* Enable or Disable Acoustic Noise Mitigation feature */
-	uint8_t AcousticNoiseMitigation;
+	uint8_t acoustic_noise_mitigation;
 	/* Disable Fast Slew Rate for Deep Package C States for VR domains */
-	uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS];
+	uint8_t fast_pkg_c_ramp_disable[NUM_VR_DOMAINS];
 	/*
 	 * Slew Rate configuration for Deep Package C States for VR domains
 	 * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values
 	 */
-	uint8_t SlowSlewRate[NUM_VR_DOMAINS];
+	uint8_t slow_slew_rate[NUM_VR_DOMAINS];
 
 	/* Energy-Performance Preference (HWP feature) */
 	bool enable_energy_perf_pref;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b4e833bf55ea..90ecf86d050e 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -337,16 +337,16 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
 	for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
-		s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+		s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i];
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
-		s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
-		s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
-		s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+		s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i];
+		s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i];
+		s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i];
 	}
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
-		s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+		s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i];
 }
 
 static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
@@ -393,7 +393,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 		DEV_PTR(tcss_usb3_port4),
 	};
 
-	s_cfg->TcssAuxOri = config->TcssAuxOri;
+	s_cfg->TcssAuxOri = config->tcss_aux_ori;
 
 	/* Explicitly clear this field to avoid using defaults */
 	memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
@@ -406,8 +406,8 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
 
 	/* D3Hot and D3Cold for TCSS */
-	s_cfg->D3HotEnable = !config->TcssD3HotDisable;
-	s_cfg->D3ColdEnable = !config->TcssD3ColdDisable;
+	s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
+	s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable;
 
 	s_cfg->UsbTcPortEn = 0;
 	for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
@@ -497,11 +497,11 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
 	/* SATA */
 	s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 	if (s_cfg->SataEnable) {
-		s_cfg->SataMode = config->SataMode;
-		s_cfg->SataSalpSupport = config->SataSalpSupport;
-		memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable,
+		s_cfg->SataMode = config->sata_mode;
+		s_cfg->SataSalpSupport = config->sata_salp_support;
+		memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable,
 			sizeof(s_cfg->SataPortsEnable));
-		memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp,
+		memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp,
 			sizeof(s_cfg->SataPortsDevSlp));
 	}
 
@@ -511,17 +511,17 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
 	 * Boards not needing the optimizers explicitly disables them by setting
 	 * these disable variables to 1 in devicetree overrides.
 	 */
-	s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+	s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
 	/*
 	 *  Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
 	 *  SataPortsDmVal is the DITO multiplier. Default is 15.
 	 *  SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
 	 *  The default values can be changed from devicetree.
 	 */
-	for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
-		if (config->SataPortsEnableDitoConfig[i]) {
-			s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i];
-			s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
+	for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) {
+		if (config->sata_ports_enable_dito_config[i]) {
+			s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i];
+			s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i];
 		}
 	}
 }
@@ -548,8 +548,8 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 {
 	/* CNVi */
 	s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
-	s_cfg->CnviBtCore = config->CnviBtCore;
-	s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload;
+	s_cfg->CnviBtCore = config->cnvi_bt_core;
+	s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload;
 	/* Assert if CNVi BT is enabled without CNVi being enabled. */
 	assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);
 	/* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
@@ -611,7 +611,7 @@ static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode;
 #endif
 	/* Enable Hybrid storage auto detection */
-	s_cfg->HybridStorageMode = config->HybridStorageMode;
+	s_cfg->HybridStorageMode = config->hybrid_storage_mode;
 }
 
 static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
@@ -663,7 +663,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 	 * Boards not needing the optimizers explicitly disables them by setting
 	 * these disable variables to 1 in devicetree overrides.
 	 */
-	s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
+	s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable);
 	s_cfg->PmSupport = 1;
 	s_cfg->Hwp = 1;
 	s_cfg->Cx = 1;
@@ -712,10 +712,10 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
 						   power_cycle_duration);
 
 	/* Set PsysPmax if it is available from DT */
-	if (config->PsysPmax) {
-		printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
+	if (config->platform_pmax) {
+		printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax);
 		/* PsysPmax is in unit of 1/8 Watt */
-		s_cfg->PsysPmax = config->PsysPmax * 8;
+		s_cfg->PsysPmax = config->platform_pmax * 8;
 	}
 }
 
@@ -776,19 +776,19 @@ static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
 	/* transform from Hz to 100 KHz */
-	s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz);
-	s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+	s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz);
+	s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum;
 }
 
 static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
-	s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
+	s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation;
 
 	if (s_cfg->AcousticNoiseMitigation) {
 		for (int i = 0; i < NUM_VR_DOMAINS; i++) {
-			s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i];
-			s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i];
+			s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i];
+			s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i];
 		}
 	}
 }
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 3483abddd732..2a02c21d22b5 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -115,8 +115,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 		/* IGD is enabled, set IGD stolen size to 60MB. */
 		m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
 		/* DP port config */
-		m_cfg->DdiPortAConfig = config->DdiPortAConfig;
-		m_cfg->DdiPortBConfig = config->DdiPortBConfig;
+		m_cfg->DdiPortAConfig = config->ddi_portA_config;
+		m_cfg->DdiPortBConfig = config->ddi_portB_config;
 		for  (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
 			*ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] &
 								DDI_ENABLE_DDC);
@@ -138,10 +138,10 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
-	m_cfg->SaGv = config->SaGv;
+	m_cfg->SaGv = config->sagv;
 	m_cfg->RMT = config->RMT;
-	if (config->MaxDramSpeed)
-		m_cfg->DdrFreqLimit = config->MaxDramSpeed;
+	if (config->max_dram_speed)
+		m_cfg->DdrFreqLimit = config->max_dram_speed;
 }
 
 static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
@@ -203,7 +203,7 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->LockPTMregs = 0;
 
 	/* Skip CPU replacement check */
-	m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
+	m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check;
 
 	/* Skip GPIO configuration from FSP */
 	m_cfg->GpioOverride = 0x1;
@@ -223,10 +223,10 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 {
 	/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
 	m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
-	m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
-	m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
-	m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
-	m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
+	m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable;
+	m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
+	m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
+	m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
 	/*
 	 * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
 	 * configure GPIO pads for audio. Mainboard is expected to perform all GPIO