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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-06-15 21:42:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-19 00:30:32 +0000 |
| commit | 56fa67c15157628abd182edfc6370f9e63c0360b (patch) | |
| tree | c06a8c6d9aec580da4bcc3875f94c8bfb24c9fac | |
| parent | 18c997f439038a08f24d066283ee1d871027fdef (diff) | |
| download | coreboot-56fa67c15157628abd182edfc6370f9e63c0360b.tar.gz coreboot-56fa67c15157628abd182edfc6370f9e63c0360b.tar.bz2 coreboot-56fa67c15157628abd182edfc6370f9e63c0360b.zip | |
soc/amd/sabrina/fsp_m_params: add UPD pointer parameter to mb callback
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/skyrim/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/fsp_m_params.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/platform_descriptors.h | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/skyrim/romstage.c b/src/mainboard/google/skyrim/romstage.c index bd7af6a9cd1c..fe5b6760e41b 100644 --- a/src/mainboard/google/skyrim/romstage.c +++ b/src/mainboard/google/skyrim/romstage.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <soc/platform_descriptors.h> -void mb_pre_fspm(void) +void mb_pre_fspm(FSP_M_CONFIG *mcfg) { size_t base_num_gpios; const struct soc_amd_gpio *base_gpios; diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c index 1a2f23bd5171..70ebc7772a95 100644 --- a/src/soc/amd/sabrina/fsp_m_params.c +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -16,7 +16,7 @@ #include <vendorcode/amd/fsp/sabrina/FspUsb.h> #include "chip.h" -__weak void mb_pre_fspm(void) +__weak void mb_pre_fspm(FSP_M_CONFIG *mcfg) { } @@ -156,5 +156,5 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); - mb_pre_fspm(); + mb_pre_fspm(mcfg); } diff --git a/src/soc/amd/sabrina/include/soc/platform_descriptors.h b/src/soc/amd/sabrina/include/soc/platform_descriptors.h index c8e0fd048606..faa81e755533 100644 --- a/src/soc/amd/sabrina/include/soc/platform_descriptors.h +++ b/src/soc/amd/sabrina/include/soc/platform_descriptors.h @@ -14,6 +14,6 @@ void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); -void mb_pre_fspm(void); +void mb_pre_fspm(FSP_M_CONFIG *mcfg); #endif /* AMD_SABRINA_PLATFORM_DESCRIPTORS_H */ |