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| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2022-01-12 13:31:21 +0900 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-17 15:51:27 +0000 |
| commit | 9341920453a4538f83d3e707fc457e0038a121d6 (patch) | |
| tree | f5daeb2f18b425297ffca39d5deec1f02c6efe89 | |
| parent | 2a81cab066e72f18fa269c505b417036a1091ea4 (diff) | |
| download | coreboot-9341920453a4538f83d3e707fc457e0038a121d6.tar.gz coreboot-9341920453a4538f83d3e707fc457e0038a121d6.tar.bz2 coreboot-9341920453a4538f83d3e707fc457e0038a121d6.zip | |
mb/google/dedede/var/bugzzy: Set core display clock to 172.8 MHz
When using the default initial core display clock frequency (648MHz),
Jasper Lake board might have a rare stability issue where the startup
of Chrome OS in secure mode may hang during re-initializing display in
kernel graphic driver.
Bugzzy didn't show this problem so far, but Intel recommends slowing
the initial core display clock frequency down to 172.8 MHz to prevent
this potential problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for bugzzy.
BUG=None
BRANCH=dedede
TEST=Build firmware and check the DUTs can boot up in secure mode well.
Change-Id: I592b2d7c814881074bd2fef9906f2450326c1fcd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/mainboard/google/dedede/variants/bugzzy/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index b56fb30fbacd..49f1e651f1ce 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,6 +2,9 @@ chip soc/intel/jasperlake # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + # Enable Acoustic noise mitigation and set slew rate to 1/8 # Rest of the parameters are 0 by default. register "AcousticNoiseMitigation" = "1" |