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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-08-11 21:09:45 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-13 18:04:55 +0000 |
| commit | e7f3e6a0558e6783916335bacb69655f7ac1493f (patch) | |
| tree | 5af0e6624e5dd7df6d360005d838bfa1a978bab6 | |
| parent | 13bf4dde29d9ac0b3142a5558d9663f9734fc2c1 (diff) | |
| download | coreboot-e7f3e6a0558e6783916335bacb69655f7ac1493f.tar.gz coreboot-e7f3e6a0558e6783916335bacb69655f7ac1493f.tar.bz2 coreboot-e7f3e6a0558e6783916335bacb69655f7ac1493f.zip | |
mb/google/brya/variants/brya0: add PL4 values for different SKUs
Add PL4 values for brya0 board for different CPU SKUs.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 with below messages,
On brya (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000)
On brya (482):
Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000)
Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/ramstage.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 0da8eb101dfd..9a4fc2825d99 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -4,11 +4,11 @@ #include <device/pci_ids.h> const struct cpu_power_limits limits[] = { - /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ - /* PL2 values are for baseline config as per bug:191906315 comment #10 */ - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000 }, + /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000, 100000}, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000, 105000}, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000, 159000}, }; void variant_devtree_update(void) |