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| author | Edward O'Callaghan <quasisec@google.com> | 2020-01-23 10:45:00 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-30 11:46:32 +0000 |
| commit | 38f7db79b59dcc45b353e1c28943588309ac9571 (patch) | |
| tree | 36af0fa19ec0712b2b2d39b6df5cf1747cb2188e /AUTHORS | |
| parent | b765fa6e4789a160cd3fc543e6f659c333a17110 (diff) | |
| download | coreboot-38f7db79b59dcc45b353e1c28943588309ac9571.tar.gz coreboot-38f7db79b59dcc45b353e1c28943588309ac9571.tar.bz2 coreboot-38f7db79b59dcc45b353e1c28943588309ac9571.zip | |
mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for
the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH.
Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become
lively again.
BUG=b:147026979
BRANCH=none
TEST=Boot puff and do 1500 cycles of S0ix.
Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions