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| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2022-06-18 11:53:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-20 12:01:41 +0000 |
| commit | 3b0303dbe8c4883b329cab151de33d952baea02a (patch) | |
| tree | 658c76aa0cd6d4f4d0c6a1afe82ced87b6b5ef9e /Documentation | |
| parent | 6ddcbb6f0bf9721b5ae936dff5373f9dd2b6c204 (diff) | |
| download | coreboot-3b0303dbe8c4883b329cab151de33d952baea02a.tar.gz coreboot-3b0303dbe8c4883b329cab151de33d952baea02a.tar.bz2 coreboot-3b0303dbe8c4883b329cab151de33d952baea02a.zip | |
Doc/soc/intel/mp_init: Mark up Reference section title as title
It’s a section title, so mark it up as a title as it’s done similarily
in other documents.
Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/soc/intel/mp_init/mp_init.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md index 7284e8a1c55e..f7776e511eb7 100644 --- a/Documentation/soc/intel/mp_init/mp_init.md +++ b/Documentation/soc/intel/mp_init/mp_init.md @@ -51,6 +51,6 @@ option in order to perform SGX and C6DRAM enabling. Typically all platforms supported by FSP 2.1 specification will have external PPI service feature implemented. -[References] +## References - [PPI](../fsp/ppi/ppi.md) - [MP Service PPI](../fsp/ppi/mp_service_ppi.md) |