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| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2022-01-11 17:59:15 +0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-14 17:54:27 +0000 |
| commit | c98df1478b7a00e1a56b421ced001f6876da07dd (patch) | |
| tree | 47916e01b6b408247e828e9f28ccfc7dd6759887 /MAINTAINERS | |
| parent | a99355376b47aac2beca75c7e9c6ed7b74629452 (diff) | |
| download | coreboot-c98df1478b7a00e1a56b421ced001f6876da07dd.tar.gz coreboot-c98df1478b7a00e1a56b421ced001f6876da07dd.tar.bz2 coreboot-c98df1478b7a00e1a56b421ced001f6876da07dd.zip | |
mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3
The anahera thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.
BUG=b:214088543
TEST=build and verified by thermal team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions