Add UCB RISCV support for architecture, soc, and emulation mainboard..

Works in the RISCV version of QEMU.

Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.

We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.

Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

1 files changed, 9 insertions, 0 deletions

diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c
new file mode 100644
index 000000000000..6e64028777dd
--- /dev/null
+++ b/src/arch/riscv/misc.c
@@ -0,0 +1,9 @@
+#include <delay.h>
+
+void init_timer(void)
+{
+}
+
+void udelay(unsigned int n)
+{
+}