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| author | Xiang Wang <wxjstz@126.com> | 2019-03-28 12:19:30 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:17:24 +0000 |
| commit | a6f9eab44ab0590ca7da33da0b042a8fce8da0f1 (patch) | |
| tree | da04d80fb1c25357e757e3baa2e4480fdc026dd2 /src/arch/riscv/tables.c | |
| parent | c989e0bd56ae19770af91e30cbbf9dc5c9717da8 (diff) | |
| download | coreboot-a6f9eab44ab0590ca7da33da0b042a8fce8da0f1.tar.gz coreboot-a6f9eab44ab0590ca7da33da0b042a8fce8da0f1.tar.bz2 coreboot-a6f9eab44ab0590ca7da33da0b042a8fce8da0f1.zip | |
riscv: add support for OpenSBI
Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the
platform. It will also jump to the specified payload when done.
This behaviour is similar to BL31 on aarch31.
The payload is 41KiB in size on qemu.
Tested on qemu-riscv:
Required to boot a kernel as OpenSBI's instruction emulation feature
is required on that virtual machine.
Tested on SiFive/unleashed:
The earlycon is working. No console after regular serial driver
should take over, which might be related to kernel config.
Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/arch/riscv/tables.c')
| -rw-r--r-- | src/arch/riscv/tables.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index eef6bf2ffdf7..c5bcab0661c7 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -18,6 +18,9 @@ #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> +#include <symbols.h> + +DECLARE_OPTIONAL_REGION(opensbi); void arch_write_tables(uintptr_t coreboot_table) { @@ -25,6 +28,9 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { + if (CONFIG(RISCV_OPENSBI) && REGION_SIZE(opensbi) > 0) + bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi), + BM_MEM_OPENSBI); } void lb_arch_add_records(struct lb_header *header) |