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| author | Maximilian Brune <maximilian.brune@9elements.com> | 2023-11-09 17:53:34 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-11-13 11:09:39 +0000 |
| commit | bd06a297d5c1a0d75056e505a4f35568708e190e (patch) | |
| tree | bb641240f12f2626caf7d986c74f99da297e8085 /src/arch/riscv | |
| parent | 7698ebe162306622265ee11bd8ab414949641c84 (diff) | |
| download | coreboot-bd06a297d5c1a0d75056e505a4f35568708e190e.tar.gz coreboot-bd06a297d5c1a0d75056e505a4f35568708e190e.tar.bz2 coreboot-bd06a297d5c1a0d75056e505a4f35568708e190e.zip | |
arch/riscv/ramstage.S: Add comments for passed arguments
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib1af1359249008d9eba351271637748a7edcec26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/ramstage.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 921c46d8a579..954b1555b3e6 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -7,7 +7,11 @@ .section ".text._start", "ax", %progbits .globl _start _start: - /* cbmem_top is passed via a2 */ + # The romstage may pass the following arguments: + # a0: the value of mhartid + # a1: a pointer to the flattened devicetree + # a2: cbmem_top + la t0, _cbmem_top_ptr #if __riscv_xlen == 32 sw a2, (t0) @@ -28,6 +32,7 @@ _start: # initialize hart-local storage csrr a0, mhartid + #NOTE a1 contains FDT and should not be cluttered above call hls_init li a0, CONFIG_RISCV_WORKING_HARTID |