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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-26 17:31:48 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-01-26 17:29:20 +0000 |
| commit | aaa4a0d39e438b0a3b60e673f6375d5048cafbc5 (patch) | |
| tree | aae7878312de3062cbf1b106353ae9b90e09560d /src/cpu/intel/common/fsb.c | |
| parent | 64d0ad347b5c9c698547f0ff15779e88a10014f4 (diff) | |
| download | coreboot-aaa4a0d39e438b0a3b60e673f6375d5048cafbc5.tar.gz coreboot-aaa4a0d39e438b0a3b60e673f6375d5048cafbc5.tar.bz2 coreboot-aaa4a0d39e438b0a3b60e673f6375d5048cafbc5.zip | |
cpu/intel/common/fsb.c: Add Broadwell CPUID models
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.
Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.
This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell
CPUIDs and microcode) and went unnoticed until now because the tests
were done with flashconsole enabled, which somehow boots properly even
though the console time tracking would not work (depends on TSC).
Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.
Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/common/fsb.c')
| -rw-r--r-- | src/cpu/intel/common/fsb.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 3d46bbc4b94a..68abe1c8755a 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -44,8 +44,10 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x3d: /* Broadwell-ULT BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ + case 0x47: /* Broadwell BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; |