Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

28 files changed, 89 insertions, 89 deletions

diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 04c4d9ff58c0..870490c07d31 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -1,5 +1,5 @@
 # Note: From here on down, we are socket-centric. Socket choice determines
-# what other cpu files are included. 
+# what other cpu files are included.
 #
 # Therefore: ONLY include Makefile.inc from socket directories!
 
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index f6a7e12e0d1e..41f3ce5b4d54 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -305,11 +305,11 @@ lout:
 	pushl	%eax  /* bist */
 	call	main
 
-	/* 
+	/*
 	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
 		It is only needed if we want to go back
 	*/
-	
+
         /* We don't need cache as ram for now on */
         /* disable cache */
 	movl    %cr0, %eax
@@ -396,7 +396,7 @@ lout:
 __main:
 	post_code(0x11)
 	cld			/* clear direction flag */
-	
+
 	movl	%ebp, %esi
 
 	movl $ROMSTAGE_STACK, %esp
@@ -404,7 +404,7 @@ __main:
 	pushl %esi
 	call copy_and_run
 
-.Lhlt:	
+.Lhlt:
 	post_code(0xee)
 	hlt
 	jmp	.Lhlt
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 5e77a765a82d..823d77c3a35a 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -43,7 +43,7 @@ void intel_sibling_init(device_t cpu)
 		}
 		return;
 	}
-	
+
 	/* I am the primary cpu start up my siblings */
 	for(i = 1; i < siblings; i++) {
 		struct device_path cpu_path;
@@ -61,7 +61,7 @@ void intel_sibling_init(device_t cpu)
 		}
 
 #if 1
-		printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", 
+		printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
 			cpu->path.apic.apic_id,
 			new->path.apic.apic_id);
 #endif
@@ -72,6 +72,6 @@ void intel_sibling_init(device_t cpu)
 				new->path.apic.apic_id);
 		}
 	}
-	
+
 }
 
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 22c3a11503bd..93d2a687fbb0 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -59,7 +59,7 @@ void intel_update_microcode(const void *microcode_updates)
 	const struct microcode *m;
 	const char *c;
 	msr_t msr;
-	
+
 	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
 	msr.lo = 0;
 	msr.hi = 0;
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index fc20c6047fe7..81978988471f 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -40,7 +40,7 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src) 
+static inline void strcpy(char *dst, char *src)
 {
 	while (*src) *dst++ = *src++;
 }
@@ -77,7 +77,7 @@ static void fill_processor_name(char *processor_name)
 
 	/* Skip leading spaces */
 	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
+	while (*processor_name_start == ' ')
 		processor_name_start++;
 
 	memset(processor_name, 0, 49);
@@ -197,7 +197,7 @@ static void configure_pic_thermal_sensors(void)
 #if CONFIG_USBDEBUG_DIRECT
 static unsigned ehci_debug_addr;
 #endif
-		
+
 static void model_1067x_init(device_t cpu)
 {
 	char processor_name[49];
@@ -214,7 +214,7 @@ static void model_1067x_init(device_t cpu)
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
-	if(!ehci_debug_addr) 
+	if(!ehci_debug_addr)
 		ehci_debug_addr = get_ehci_debug();
 	set_ehci_debug(0);
 #endif
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 767c488d4556..873c6e94791a 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -1,18 +1,18 @@
-/* 
+/*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007-2008 coresystems GmbH
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
@@ -206,7 +206,7 @@ clear_mtrrs:
 	xorl	%eax, %eax
 	movl	$((1024*1024) / 4), %ecx
 	rep stosl
-	
+
 	post_code(0x37)
 #endif
 
@@ -254,7 +254,7 @@ clear_mtrrs:
 __main:
 	post_code(0x11)
 	cld			/* clear direction flag */
-	
+
 	movl	%ebp, %esi
 
 	movl $ROMSTAGE_STACK, %esp
@@ -262,7 +262,7 @@ __main:
 	pushl %esi
 	call copy_and_run
 
-.Lhlt:	
+.Lhlt:
 	post_code(0xee)
 	hlt
 	jmp	.Lhlt
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 143a6f473a6d..65dfebba5b2e 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -39,7 +39,7 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src) 
+static inline void strcpy(char *dst, char *src)
 {
 	while (*src) *dst++ = *src++;
 }
@@ -64,7 +64,7 @@ static void fill_processor_name(char *processor_name)
 
 	/* Skip leading spaces */
 	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
+	while (*processor_name_start == ' ')
 		processor_name_start++;
 
 	memset(processor_name, 0, 49);
@@ -175,7 +175,7 @@ static void model_106cx_init(device_t cpu)
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
-	if(!ehci_debug_addr) 
+	if(!ehci_debug_addr)
 		ehci_debug_addr = get_ehci_debug();
 	set_ehci_debug(0);
 #endif
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index f2605ebd79be..b6ea237366cc 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -26,7 +26,7 @@ static void model_69x_init(device_t dev)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index a921fbd368af..783138ec836a 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
  *
@@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src) 
+static inline void strcpy(char *dst, char *src)
 {
 	while (*src) *dst++ = *src++;
 }
@@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
 
 	/* Skip leading spaces */
 	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
+	while (*processor_name_start == ' ')
 		processor_name_start++;
 
 	memset(processor_name, 0, 49);
@@ -96,7 +96,7 @@ static void model_6bx_init(device_t cpu)
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
-	if(!ehci_debug_addr) 
+	if(!ehci_debug_addr)
 		ehci_debug_addr = get_ehci_debug();
 	set_ehci_debug(0);
 #endif
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 936c67afc94d..26c1b994994a 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -26,7 +26,7 @@ static void model_6dx_init(device_t dev)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index d4f5d8bf5ecd..623b0a30a1cd 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -1,18 +1,18 @@
-/* 
+/*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007-2008 coresystems GmbH
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
@@ -206,7 +206,7 @@ clear_mtrrs:
 	xorl	%eax, %eax
 	movl	$((1024*1024) / 4), %ecx
 	rep stosl
-	
+
 	post_code(0x37)
 #endif
 
@@ -254,7 +254,7 @@ clear_mtrrs:
 __main:
 	post_code(0x11)
 	cld			/* clear direction flag */
-	
+
 	movl	%ebp, %esi
 
 	movl $ROMSTAGE_STACK, %esp
@@ -262,7 +262,7 @@ __main:
 	pushl %esi
 	call copy_and_run
 
-.Lhlt:	
+.Lhlt:
 	post_code(0xee)
 	hlt
 	jmp	.Lhlt
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index f879f348693c..4f1d2043b6b8 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src) 
+static inline void strcpy(char *dst, char *src)
 {
 	while (*src) *dst++ = *src++;
 }
@@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name)
 
 	/* Skip leading spaces */
 	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
+	while (*processor_name_start == ' ')
 		processor_name_start++;
 
 	memset(processor_name, 0, 49);
@@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu)
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
-	if(!ehci_debug_addr) 
+	if(!ehci_debug_addr)
 		ehci_debug_addr = get_ehci_debug();
 	set_ehci_debug(0);
 #endif
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index f46e5bdc480c..0717116d0ab4 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -1,18 +1,18 @@
-/* 
+/*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007-2008 coresystems GmbH
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
@@ -213,7 +213,7 @@ clear_mtrrs:
 	xorl	%eax, %eax
 	movl	$((1024*1024) / 4), %ecx
 	rep stosl
-	
+
 	post_code(0x37)
 #endif
 
@@ -268,7 +268,7 @@ clear_mtrrs:
 __main:
 	post_code(0x11)
 	cld			/* clear direction flag */
-	
+
 	movl	%ebp, %esi
 
 	movl $ROMSTAGE_STACK, %esp
@@ -276,7 +276,7 @@ __main:
 	pushl %esi
 	call copy_and_run
 
-.Lhlt:	
+.Lhlt:
 	post_code(0xee)
 	hlt
 	jmp	.Lhlt
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index f00aba8e33fa..3d1e9ba9a348 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
@@ -58,7 +58,7 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src) 
+static inline void strcpy(char *dst, char *src)
 {
 	while (*src) *dst++ = *src++;
 }
@@ -83,7 +83,7 @@ static void fill_processor_name(char *processor_name)
 
 	/* Skip leading spaces */
 	processor_name_start = temp_processor_name;
-	while (*processor_name_start == ' ') 
+	while (*processor_name_start == ' ')
 		processor_name_start++;
 
 	memset(processor_name, 0, 49);
@@ -214,7 +214,7 @@ static void configure_pic_thermal_sensors(void)
 #if CONFIG_USBDEBUG_DIRECT
 static unsigned ehci_debug_addr;
 #endif
-		
+
 static void model_6fx_init(device_t cpu)
 {
 	char processor_name[49];
@@ -231,7 +231,7 @@ static void model_6fx_init(device_t cpu)
 
 #if CONFIG_USBDEBUG_DIRECT
 	// Is this caution really needed?
-	if(!ehci_debug_addr) 
+	if(!ehci_debug_addr)
 		ehci_debug_addr = get_ehci_debug();
 	set_ehci_debug(0);
 #endif
diff --git a/src/cpu/intel/model_6xx/microcode_MU16810d.h b/src/cpu/intel/model_6xx/microcode_MU16810d.h
index ce207efa769f..ef1ff7dd1d6f 100644
--- a/src/cpu/intel/model_6xx/microcode_MU16810d.h
+++ b/src/cpu/intel/model_6xx/microcode_MU16810d.h
@@ -1,12 +1,12 @@
 	/*
-	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000. 
+	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000.
 
-	  These microcode updates are distributed for the sole purpose of 
+	  These microcode updates are distributed for the sole purpose of
 	  installation in the BIOS or Operating System of computer systems
 	  which include an Intel P6 family microprocessor sold or distributed
 	  to or by you.  You are authorized to copy and install this material
 	  on such systems.  You are not authorized to use this material for
-	  any other purpose.  
+	  any other purpose.
 	*/
 
 /*  MU16810d.inc  */
diff --git a/src/cpu/intel/model_6xx/microcode_MU16830c.h b/src/cpu/intel/model_6xx/microcode_MU16830c.h
index 2724e7bae4bf..602739c368a7 100644
--- a/src/cpu/intel/model_6xx/microcode_MU16830c.h
+++ b/src/cpu/intel/model_6xx/microcode_MU16830c.h
@@ -1,12 +1,12 @@
 	/*
-	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000. 
+	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000.
 
-	  These microcode updates are distributed for the sole purpose of 
+	  These microcode updates are distributed for the sole purpose of
 	  installation in the BIOS or Operating System of computer systems
 	  which include an Intel P6 family microprocessor sold or distributed
 	  to or by you.  You are authorized to copy and install this material
 	  on such systems.  You are not authorized to use this material for
-	  any other purpose.  
+	  any other purpose.
 	*/
 
 /*  MU16830c.inc  */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 7efdf2119e9e..6c795eab3275 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -16,7 +16,7 @@ static uint32_t microcode_updates[] = {
 	 * microcode update lengths.  They are encoded in int 8 and 9.  A
 	 * dummy header of nulls must terminate the list.
 	 */
-#include "microcode_MU16810d.h"	
+#include "microcode_MU16810d.h"
 #include "microcode_MU16830c.h"
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_6xx_init(device_t dev)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index c4d1ef085ee2..568d4d70ee98 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
 	 * microcode update lengths.  They are encoded in int 8 and 9.  A
 	 * dummy header of nulls must terminate the list.
 	 */
-	
+
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_f0x/multiplier.h b/src/cpu/intel/model_f0x/multiplier.h
index e2f81362e837..a3b1fcb3090f 100644
--- a/src/cpu/intel/model_f0x/multiplier.h
+++ b/src/cpu/intel/model_f0x/multiplier.h
@@ -1,5 +1,5 @@
 
-/* 
+/*
  ** NMI A20M IGNNE INTR
  * X8  H H H H
  * X9  H H H L projected
@@ -8,7 +8,7 @@
  * X12 H L H H
  * X13 H L H L
  * X14 H L L H
- * X15 H L L L 
+ * X15 H L L L
  * X16 L H H H
  * X17 L H H L
  * X18 L H L H
@@ -18,7 +18,7 @@
  * X22 L L L H  projected
  * X23 L L L L  projected
  *
- ** NMI INTR IGNNE A20M 
+ ** NMI INTR IGNNE A20M
  * X8  H H H H
  * X9  H L H H projected
  * X10 H H L H
@@ -26,7 +26,7 @@
  * X12 H H H L
  * X13 H L H L
  * X14 H H L L
- * X15 H L L L 
+ * X15 H L L L
  * X16 L H H H
  * X17 L L H H
  * X18 L H L H
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index a3a66783c426..f8dd1d85f751 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
 	 * microcode update lengths.  They are encoded in int 8 and 9.  A
 	 * dummy header of nulls must terminate the list.
 	 */
-	
+
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,
@@ -32,7 +32,7 @@ static void model_f1x_init(device_t dev)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_f1x/multiplier.h b/src/cpu/intel/model_f1x/multiplier.h
index e2f81362e837..a3b1fcb3090f 100644
--- a/src/cpu/intel/model_f1x/multiplier.h
+++ b/src/cpu/intel/model_f1x/multiplier.h
@@ -1,5 +1,5 @@
 
-/* 
+/*
  ** NMI A20M IGNNE INTR
  * X8  H H H H
  * X9  H H H L projected
@@ -8,7 +8,7 @@
  * X12 H L H H
  * X13 H L H L
  * X14 H L L H
- * X15 H L L L 
+ * X15 H L L L
  * X16 L H H H
  * X17 L H H L
  * X18 L H L H
@@ -18,7 +18,7 @@
  * X22 L L L H  projected
  * X23 L L L L  projected
  *
- ** NMI INTR IGNNE A20M 
+ ** NMI INTR IGNNE A20M
  * X8  H H H H
  * X9  H L H H projected
  * X10 H H L H
@@ -26,7 +26,7 @@
  * X12 H H H L
  * X13 H L H L
  * X14 H H L L
- * X15 H L L L 
+ * X15 H L L L
  * X16 L H H H
  * X17 L L H H
  * X18 L H L H
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index d7b77efb726c..9c7af7896940 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -37,7 +37,7 @@ static void model_f2x_init(device_t cpu)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_f3x/microcode_M1DF340E.h b/src/cpu/intel/model_f3x/microcode_M1DF340E.h
index a378fba8acdc..55854b583a64 100644
--- a/src/cpu/intel/model_f3x/microcode_M1DF340E.h
+++ b/src/cpu/intel/model_f3x/microcode_M1DF340E.h
@@ -9,7 +9,7 @@
         */
 
 	/*  M1DF340E.TXT - Noconoa D-0  */
-	
+
 
 	0x00000001, /* Header Version	*/
 	0x0000000e, /* Patch ID		*/
diff --git a/src/cpu/intel/model_f3x/microcode_M1DF3413.h b/src/cpu/intel/model_f3x/microcode_M1DF3413.h
index f2a0a8f79d39..676d67c06171 100644
--- a/src/cpu/intel/model_f3x/microcode_M1DF3413.h
+++ b/src/cpu/intel/model_f3x/microcode_M1DF3413.h
@@ -2,7 +2,7 @@
  * microcode update lengths.  They are encoded in int 8 and 9.  A
  * dummy header of nulls must terminate the list.
  */
-                                                                                
+
         /*
            Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000.
            These microcode updates are distributed for the sole purpose of
@@ -12,9 +12,9 @@
            on such systems.  You are not authorized to use this material for
            any other purpose.
         */
-                                                                                
+
         /*  M1DF3413.TXT - Noconoa D-0  */
-                                                                                
+
         0x00000001, /* Header Version   */
         0x00000013, /* Patch ID         */
         0x07302004, /* DATE             */
@@ -27,7 +27,7 @@
         0x00000000, /* reserved         */
         0x00000000, /* reserved         */
         0x00000000, /* reserved         */
- 
+
 	0x9fbf327a,
 	0x2b41b451,
 	0xb2abaca8,
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index cbdd50ac2f11..68b22c99a86b 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
 	 * microcode update lengths.  They are encoded in int 8 and 9.  A
 	 * dummy header of nulls must terminate the list.
 	 */
-	
+
 #include "microcode_M1DF3413.h"
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
@@ -33,7 +33,7 @@ static void model_f3x_init(device_t cpu)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index a48c7592ba3d..d6acddee09e4 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = {
 	 * microcode update lengths.  They are encoded in int 8 and 9.  A
 	 * dummy header of nulls must terminate the list.
 	 */
-	
+
 #include "microcode_MBDF410D.h"
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
@@ -33,7 +33,7 @@ static void model_f4x_init(device_t cpu)
 	x86_enable_cache();
 	x86_setup_mtrrs(36);
 	x86_mtrr_check();
-	
+
 	/* Update the microcode */
 	intel_update_microcode(microcode_updates);
 
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index faa74d33902d..2fc27cff782c 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -8,7 +8,7 @@ config CPU_INTEL_SOCKET_MPGA604
 	select UDELAY_TSC
 
 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
-# but the ramtest.c code on the Dell S1850 seems to choke on 
+# but the ramtest.c code on the Dell S1850 seems to choke on
 # enabling it, so disable it for now.
 config SSE2
 	bool
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 920984369e96..33898e3280a0 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or