diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-13 22:33:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-16 09:54:32 +0000 |
| commit | 1515a48cffbb14328e0f68850f60a10332043087 (patch) | |
| tree | 03460b9eefb6c93fd018a76b8b353b823f3728cd /src/cpu/intel | |
| parent | 1109246cd1462dee38804a5a7092e6bf69bf14b5 (diff) | |
| download | coreboot-1515a48cffbb14328e0f68850f60a10332043087.tar.gz coreboot-1515a48cffbb14328e0f68850f60a10332043087.tar.bz2 coreboot-1515a48cffbb14328e0f68850f60a10332043087.zip | |
cpu/intel/haswell: Enable MCA logging
Intel document 493770 (Haswell BIOS Writer's Guide) revision 1.8.0
recommends writing all ones to the IA32_MCi_CTL registers in order
to enable all MCA error reporting.
Change-Id: Ib5d2c759483026b5b4804c5a4b2b969d2269af22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55463
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 8ba1c937f0f4..9fcb527a167e 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -524,6 +524,12 @@ static void configure_mca(void) msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; + + /* Enable all error reporting */ + msr.lo = msr.hi = ~0; + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC0_CTL + (i * 4), msr); + msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears |