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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-04-24 12:29:44 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-25 15:56:28 +0000 |
| commit | 74f9fe6e58f949001a34866505cecca16aa0de03 (patch) | |
| tree | a46a7d5f92669425a05f8394918c1b6be1e74c91 /src/cpu/intel | |
| parent | 5417c84f7d525d1db8f4abbf3ef4da527dd52cd6 (diff) | |
| download | coreboot-74f9fe6e58f949001a34866505cecca16aa0de03.tar.gz coreboot-74f9fe6e58f949001a34866505cecca16aa0de03.tar.bz2 coreboot-74f9fe6e58f949001a34866505cecca16aa0de03.zip | |
cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.
Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/intel/socket_FCBGA559/Kconfig | 1 |
4 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 3fd8bb484a5b..5936953b5262 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON + select NO_FIXED_XIP_ROM_SIZE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 9481917ff8d0..ba2b7de74d86 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select NO_FIXED_XIP_ROM_SIZE config BOOTBLOCK_CPU_INIT string @@ -28,8 +29,4 @@ config SMM_TSEG_SIZE hex default 0x800000 -config XIP_ROM_SIZE - hex - default 0x20000 - endif diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 7f73da9ab4ef..f045e9aac510 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -25,15 +25,12 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP + select NO_FIXED_XIP_ROM_SIZE config BOOTBLOCK_CPU_INIT string default "cpu/intel/model_206ax/bootblock.c" -config XIP_ROM_SIZE - hex - default 0x20000 if USE_NATIVE_RAMINIT - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 6566a01cf817..b1b310d3cc98 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS select MMX select SSE select CPU_HAS_L2_ENABLE_MSR + select NO_FIXED_XIP_ROM_SIZE config DCACHE_RAM_BASE hex |