summaryrefslogtreecommitdiffstats
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2022-06-20 08:10:39 +0000
committerFelix Held <felix-coreboot@felixheld.de>2022-06-22 12:50:40 +0000
commit7734af81bcdc602b71811343dd8f8d092fc1028f (patch)
tree011f291a1c56ed84696de37edbae6c41a400830b /src/cpu/intel
parent861ec01b44a3ef2cfbc99d574af74c87b2ecb4b7 (diff)
downloadcoreboot-7734af81bcdc602b71811343dd8f8d092fc1028f.tar.gz
coreboot-7734af81bcdc602b71811343dd8f8d092fc1028f.tar.bz2
coreboot-7734af81bcdc602b71811343dd8f8d092fc1028f.zip
cpu/intel/microcode: Create helper function to load microcode patch
This patch refactors the microcode loading and reloading API with a helper function that perform the actual MSR write operation after taking the microcode pointer from the caller function. Also, convert the microcode loading failure msg type from `BIOS_INFO` to `BIOS_ERR` to catch the error in proper. TEST=Able to perform microcode loading on google/kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9a7cdc2d2c9211f1e0c7921015126f7a1be87761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65249 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/microcode/microcode.c57
1 files changed, 26 insertions, 31 deletions
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 5ed6190e2633..4c85a5609604 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -68,10 +68,30 @@ static inline u32 read_microcode_rev(void)
#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
-void intel_microcode_load_unlocked(const void *microcode_patch)
+static int load_microcode(const struct microcode *ucode_patch)
{
u32 current_rev;
msr_t msr;
+
+ msr.lo = (unsigned long)ucode_patch + sizeof(struct microcode);
+ msr.hi = 0;
+ wrmsr(IA32_BIOS_UPDT_TRIG, msr);
+
+ current_rev = read_microcode_rev();
+ if (current_rev == ucode_patch->rev) {
+ printk(BIOS_INFO, "microcode: updated to revision "
+ "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
+ ucode_patch->date & 0xffff, (ucode_patch->date >> 24) & 0xff,
+ (ucode_patch->date >> 16) & 0xff);
+ return 0;
+ }
+
+ return -1;
+}
+
+void intel_microcode_load_unlocked(const void *microcode_patch)
+{
+ u32 current_rev;
const struct microcode *m = microcode_patch;
if (!m)
@@ -93,20 +113,9 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
}
#endif
- msr.lo = (unsigned long)m + sizeof(struct microcode);
- msr.hi = 0;
- wrmsr(IA32_BIOS_UPDT_TRIG, msr);
-
- current_rev = read_microcode_rev();
- if (current_rev == m->rev) {
- printk(BIOS_INFO, "microcode: updated to revision "
- "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
- m->date & 0xffff, (m->date >> 24) & 0xff,
- (m->date >> 16) & 0xff);
- return;
- }
-
- printk(BIOS_INFO, "microcode: Update failed\n");
+ printk(BIOS_INFO, "microcode: load microcode patch\n");
+ if (load_microcode(m) < 0)
+ printk(BIOS_ERR, "microcode: Update failed\n");
}
uint32_t get_current_microcode_rev(void)
@@ -255,8 +264,6 @@ void intel_reload_microcode(void)
if (!CONFIG(RELOAD_MICROCODE_PATCH))
return;
- u32 current_rev;
- msr_t msr;
const struct microcode *m = intel_microcode_find();
if (!m) {
@@ -266,20 +273,8 @@ void intel_reload_microcode(void)
printk(BIOS_INFO, "microcode: Re-load microcode patch\n");
- msr.lo = (unsigned long)m + sizeof(struct microcode);
- msr.hi = 0;
- wrmsr(IA32_BIOS_UPDT_TRIG, msr);
-
- current_rev = read_microcode_rev();
- if (current_rev == m->rev) {
- printk(BIOS_INFO, "microcode: updated to revision "
- "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
- m->date & 0xffff, (m->date >> 24) & 0xff,
- (m->date >> 16) & 0xff);
- return;
- }
-
- printk(BIOS_ERR, "microcode: Re-load failed\n");
+ if (load_microcode(m) < 0)
+ printk(BIOS_ERR, "microcode: Re-load failed\n");
}
#if ENV_RAMSTAGE