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| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2022-07-28 10:24:23 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-07 19:39:43 +0000 |
| commit | debb8085c6869caaa83cf80d35e035cb9e97ddce (patch) | |
| tree | fae12c498866dd50db97a9fc5ce526e0ec9ed867 /src/device/pciexp_device.c | |
| parent | df864709a5d185602f9cb4ab42689dba02ecbc35 (diff) | |
| download | coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.tar.gz coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.tar.bz2 coreboot-debb8085c6869caaa83cf80d35e035cb9e97ddce.zip | |
vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01
Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01.
Changes include:
- Add UPD Lp5BankMode
- Update UPD Offset in FspmUpd.h
BUG=b:240373012
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pciexp_device.c')
0 files changed, 0 insertions, 0 deletions