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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-21 18:47:46 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:57:29 +0000 |
| commit | 8256ca0e14e57b17b27a81b16f220c94d728e117 (patch) | |
| tree | b1bf3a14aa5509c6105d7a7af09e7181f26a6b2b /src/drivers/intel/fsp1_1/cache_as_ram.S | |
| parent | 3c1e986119cdfece27e5bf953576fa01882bb773 (diff) | |
| download | coreboot-8256ca0e14e57b17b27a81b16f220c94d728e117.tar.gz coreboot-8256ca0e14e57b17b27a81b16f220c94d728e117.tar.bz2 coreboot-8256ca0e14e57b17b27a81b16f220c94d728e117.zip | |
soc/intel/braswell: Update microcode before FSP
The google FSP Braswell version has broken microcode update code and
FSP checks at some point if the installed microcode version is non
zero, so coreboot has to update it before calling FSP-T.
This is fixed with newer FSP releases by Intel, but doing updates in
coreboot won't hurt.
Tested with both Intel FSP and google FSP.
Change-Id: I3e81329854e823dc66fec191adbed617bb37d649
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.S')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index ffafe9b4f349..f4638d9c1891 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> /* @@ -43,6 +45,45 @@ bootblock_pre_c_entry: cache_as_ram: post_code(0x20) + /* Cache the rom and update the microcode */ +cache_rom: + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* The Google FSP release for Braswell has broken microcode update + code and FSP needs the installed microcode revision to be non zero. + It is better to have coreboot do it instead of relying on a fragile + blob. */ +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: + /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. |