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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-29 17:41:30 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-10-14 17:07:56 +0000 |
| commit | 909c512c88bd7de4d5c5e7e035f162cd1a039407 (patch) | |
| tree | 8c24047d5cdc235fdd743f81936a39dfec1ae191 /src/drivers/intel/fsp1_1/include/fsp/car.h | |
| parent | 75c51d9af15dfc599adaf7a8f6e892d452146f9c (diff) | |
| download | coreboot-909c512c88bd7de4d5c5e7e035f162cd1a039407.tar.gz coreboot-909c512c88bd7de4d5c5e7e035f162cd1a039407.tar.bz2 coreboot-909c512c88bd7de4d5c5e7e035f162cd1a039407.zip | |
fsp1_1: add verstage support
In order to support verstage the cache-as-ram split
is taken advantage of such that verstage has the
cache-as-ram setup and rosmtage has the cache-as-ram
tear down path. The verstage proper just initializes
the console and attempts to run romstage which triggers
the vboot verification of the firmware. In order to
pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning
to the assembly code which tears down cache-as-ram.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with verstage support as well as
VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.
Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/car.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/car.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 8234b37ea8f6..f2d1c74729a2 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -36,6 +36,7 @@ struct cache_as_ram_params { /* Entry points from the cache-as-ram assembly code. */ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params); asmlinkage void after_cache_as_ram(void *chipset_context); +asmlinkage void *romstage_after_verstage(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in ram after * exiting cache-as-ram mode. */ |