summaryrefslogtreecommitdiffstats
path: root/src/drivers/intel/fsp2_0/silicon_init.c
diff options
context:
space:
mode:
authorJulius Werner <jwerner@chromium.org>2021-04-12 16:28:37 -0700
committerJulius Werner <jwerner@chromium.org>2021-04-14 01:03:22 +0000
commitb3182fbb0021f725c302bf327663696ca0800a4d (patch)
treedcc2c9863f9265e38b508e2c43470d400c4356b1 /src/drivers/intel/fsp2_0/silicon_init.c
parentc074f61d8fb0fbad1ec7a19e32cb7d1524ad97f0 (diff)
downloadcoreboot-b3182fbb0021f725c302bf327663696ca0800a4d.tar.gz
coreboot-b3182fbb0021f725c302bf327663696ca0800a4d.tar.bz2
coreboot-b3182fbb0021f725c302bf327663696ca0800a4d.zip
vboot: ec_sync: Switch to new CBFS API
This patch changes the vboot EC sync code to use the new CBFS API. As a consequence, we have to map the whole EC image file at once (because the new API doesn't support partial mapping). This should be fine on the only platform that uses this code (Google_Volteer/_Dedede family) because they are x86 devices that support direct mapping from flash, but the code was originally written to more carefully map the file in smaller steps to be theoretically able to support Arm devices. EC sync in romstage for devices without memory-mapped flash would be hard to combine with CBFS verification because there's not enough SRAM to ever hold the whole file in memory at once, but we can't validate the file hash until we have loaded the whole file and for performance (or TOCTOU-safety, if applicable) reasons we wouldn't want to load anything more than once. The "good" solution for this would be to introduce a CBFS streaming API can slowly feed chunks of the file into a callback but in the end still return a "hash valid/invalid" result to the caller. If use cases like this become pressing in the future, we may have to implement such an API. However, for now this code is the only part of coreboot with constraints like that, it was only ever used on platforms that do support memory-mapped flash, and due to the new EC-EFS2 model used on more recent Chrome OS devices we don't currently anticipate this to ever be needed again. Therefore this patch goes the easier way of just papering over the problem and punting the work of implementing a more generic solution until we actually have a real need for it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7e263272aef3463f3b2924887d96de9b2607f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52280 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/silicon_init.c')
0 files changed, 0 insertions, 0 deletions