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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-09 13:30:57 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-29 10:53:33 +0000 |
| commit | e0165fbc944521171cd2776be4d3f655712079d2 (patch) | |
| tree | da303ac99860420f001a843c98e547576bc4cfc8 /src/drivers/intel/fsp2_0/silicon_init.c | |
| parent | cdaddde0672643a2457b163ea1b286a4ea77c0f1 (diff) | |
| download | coreboot-e0165fbc944521171cd2776be4d3f655712079d2.tar.gz coreboot-e0165fbc944521171cd2776be4d3f655712079d2.tar.bz2 coreboot-e0165fbc944521171cd2776be4d3f655712079d2.zip | |
stage_cache: Add resume_from_stage_cache()
Factor out the condition when an attempt to load
stage from cache can be tried.
Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0/silicon_init.c')
| -rw-r--r-- | src/drivers/intel/fsp2_0/silicon_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a4ffbda4cc52..08494603f53d 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -205,7 +205,7 @@ void fsps_load(bool s3wake) if (load_done) return; - if (s3wake && !CONFIG(NO_STAGE_CACHE)) { + if (resume_from_stage_cache()) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, fsps); if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) |