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| author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-06-10 15:24:57 +0000 |
|---|---|---|
| committer | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-06-10 15:24:57 +0000 |
| commit | f333ba09580c00a6f27e3ee0796431f5df936ecf (patch) | |
| tree | d9d961b45e248d59bf8e3e582b1619887d1921b9 /src/include/cpu/x86/msr.h | |
| parent | 1965a237124cc8e988cf760eb7e9a61efb2adabb (diff) | |
| download | coreboot-f333ba09580c00a6f27e3ee0796431f5df936ecf.tar.gz coreboot-f333ba09580c00a6f27e3ee0796431f5df936ecf.tar.bz2 coreboot-f333ba09580c00a6f27e3ee0796431f5df936ecf.zip | |
This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu/x86/msr.h')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index daa7e184224f..a201ef42f2ab 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -23,6 +23,12 @@ typedef struct msr_struct unsigned hi; } msr_t; +typedef struct msrinit_struct +{ + unsigned index; + msr_t msr; +} msrinit_t; + static inline msr_t rdmsr(unsigned index) { msr_t result; |