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path: root/src/include/cpu/x86/msr.h
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* security/intel/txt: Add helper function to disable TXTSubrata Banik2023-01-091-0/+1
* include/cpu/msr.h: transform into an unionArthur Heymans2022-11-121-9/+4
* treewide: Add 'IWYU pragma: export' commentElyes Haouas2022-11-031-1/+1
* arch/x86/include: Split msr access into separate fileMartin Roth2022-10-211-54/+2
* include: Add SPDX-License-Identifiers to files missing themMartin Roth2022-08-011-0/+2
* cpu/intel/common: Add support for energy performance preference (EPP)Cliff Huang2022-03-091-0/+3
* cpu/x86/lapic: Support switching to X2APIC modeKyösti Mälkki2022-02-051-0/+1
* soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik2021-08-161-0/+1
* soc/intel/common: Calculate and configure SF Mask 2Subrata Banik2021-08-151-0/+2
* include/cpu: Remove one space from bitfield macro definitionSubrata Banik2021-07-241-1/+1
* include/cpu: Use tab instead of spaceSubrata Banik2021-07-241-5/+5
* include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msrFelix Held2021-07-141-1/+0
* include/cpu/x86/msr: add mca_clear_status functionFelix Held2021-07-141-0/+10
* include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held2021-07-141-0/+4
* include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISCFelix Held2021-07-141-2/+2
* include/cpu/x86/msr: fix MCG_CTL_P definitionFelix Held2021-07-121-1/+1
* include/cpu/x86/msr: add mca_get_bank_count functionFelix Held2021-07-121-0/+7
* cpu/x86/msr: introduce helpers msr_read, msr_writeMichael Niewöhner2021-04-301-0/+26
* cpu/intel/common: rework code previously moved to common cpu codeMichael Niewöhner2020-10-241-1/+2
* include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner2020-10-161-13/+36
* src/include: Drop unneeded empty linesElyes HAOUAS2020-09-141-2/+0
* soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra2020-09-141-0/+3
* security/intel/stm: Check for processor STM supportEugene Myers2020-02-211-0/+1
* security/intel/stm: Add STM supportEugene Myers2020-02-051-0/+10
* Drop ROMCC code and header guardsArthur Heymans2019-12-191-16/+0
* Revert "include/cpu/x86: Add STM Support"Aaron Durbin2019-12-181-6/+0
* include/cpu/x86: Add STM SupportEugene D. Myers2019-12-181-0/+6
* cpu/x86: make set_msr_bit publicly availableMichael Niewöhner2019-10-311-0/+20
* cpu/x86/msr: Move IA32_MISC_ENABLE bits to common placeElyes HAOUAS2019-06-211-0/+2
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* cpuid: Add helper function for cpuid(1) functionsSubrata Banik2018-12-131-0/+2
* src: Replace common MSR addresses with macrosElyes HAOUAS2018-11-081-0/+1
* src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-301-0/+171
* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-10-181-0/+2
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-9/+39
* Move compiler.h to commonlibNico Huber2018-10-081-2/+0
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-141-8/+8
* src/include: add more msr definesMatt Delco2018-08-171-1/+7
* cpu/x86: move NXE and PAT accesses to paging moduleAaron Durbin2018-04-231-0/+12
* src/include: Wrap lines at 80 columnsLee Leahy2017-03-131-2/+4
* src/include: Open brace on same line as enum or structLee Leahy2017-03-121-4/+2
* src/include: Fix unsigned warningsLee Leahy2017-03-091-9/+9
* src/include: Improve code formattingElyes HAOUAS2016-09-051-6/+4
* src/include: Capitalize CPU, RAM and ROMElyes HAOUAS2016-07-311-1/+1
* cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy2016-07-271-1/+20
* remove trailing whitespaceStefan Reinauer2011-11-011-1/+1
* AMD Fam10 code breaks with gcc 4.5.0.Scott Duplichan2010-09-171-2/+12
* This commit updates the Geode LX GLCP delay control setup from the v2 way to ...Edwin Beasant2010-06-101-0/+6
* Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer2010-04-271-1/+1
* drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is moreStefan Reinauer2010-03-281-2/+1
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