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* cpu/x86/smm/pci_resource_store: Store DEV/VEN IDPatrick Rudolph2024-01-311-0/+2
* soc/intel: Add Lunar Lake device IDsAppukuttan V K2024-01-241-0/+1
* cpu/x86/smi_trigger: use enum cb_err as apm_control return typeFelix Held2024-01-101-1/+1
* x86: Separate CPU and SoC physical address sizeJeremy Compostella2023-12-221-0/+1
* drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth2023-12-131-1/+1
* src: Remove unnecessary semicolons from the end of macrosMartin Roth2023-11-101-1/+1
* cpu/x86/smm: Fix get_save_state calculationEugene D. Myers2023-11-101-0/+9
* */include/cpu: use unsigned int for number of address bitsFelix Held2023-09-291-1/+1
* arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella2023-09-121-0/+3
* src/*/post_code.h: Change post code prefix to POSTCODEYuchen He2023-08-051-20/+20
* include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNTFelix Held2023-07-181-0/+1
* treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski2023-07-121-11/+11
* soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz2023-07-121-0/+4
* arch/x86: Ensure LAPIC mode for exception handlerKyösti Mälkki2023-07-051-0/+12
* cpu/x86: Reduce scope of MTRR functions used locallyKyösti Mälkki2023-07-031-3/+1
* soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi2023-06-291-0/+1
* soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()Felix Held2023-06-072-0/+5
* cpu/x86/smm: Drop fxsave/fxrstor logicArthur Heymans2023-06-041-2/+0
* soc/amd/common/block/cpu: Refactor ucode allocationGrzegorz Bernacki2023-06-021-0/+3
* include/cpu/x86: Simplify en/dis cache functionsHimanshu Sahdev2023-06-021-8/+2
* include/cpu/x86: Skip `wbinvd` on CPUs with cache self-snooping (SS)Subrata Banik2023-06-011-1/+14
* cpu/x86/cache: Call wbinvd only once CR0.CD is setJeremy Compostella2023-06-011-1/+0
* cpu/x86/mp_init: Use clflush to write SIPI data back to RAMJeremy Compostella2023-05-311-0/+2
* treewide: Remove 'extern' from functions declarationElyes Haouas2023-05-261-9/+9
* include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gbFelix Held2023-04-231-1/+1
* include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gbFelix Held2023-04-211-1/+1
* include/cpu/amd/mtrr: rename functions to get top of memory regionsFelix Held2023-04-211-2/+2
* src/cpu/power9: move part of scom.h to scom.cSergii Dmytruk2023-04-181-5/+0
* soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi2023-04-151-0/+1
* cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans2023-04-061-0/+14
* cpu/smm_module_loader.c: Fix up CPU index locallyArthur Heymans2023-04-061-2/+0
* cpu/x86/mp_init.c: Generate a C header to get start32 offsetArthur Heymans2023-04-061-2/+0
* cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans2023-04-061-4/+0
* cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build errorJohnny Lin2023-03-241-6/+0
* soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held2023-03-231-2/+0
* soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki2023-03-231-0/+9
* soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang2023-03-191-0/+6
* cpu/x86/cache: CLFLUSH programs to memory before runningArthur Heymans2023-03-131-0/+4
* soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held2023-03-081-0/+3
* cpu/x86/smm: Add PCI resource store functionalityRobert Zieba2023-03-051-0/+26
* soc/amd: introduce and use PSTATE_MSR macroFelix Held2023-02-281-4/+1
* cpu/x86/smm: Enable setting SMM console log level from mainboardJohnny Lin2023-02-151-0/+2
* src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth2023-02-071-1/+0
* include/cpu/amd/mtrr: drop unused TOP_MEM_MASK definitionsFelix Held2023-02-021-3/+0
* tree: Drop Intel Ice Lake supportFelix Singer2023-01-191-2/+0
* security/intel/txt: Add helper function to disable TXTSubrata Banik2023-01-091-0/+1
* cpu/cpu.h: Change the function signatureArthur Heymans2022-12-101-1/+1
* treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas2022-12-101-1/+1
* mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki2022-12-071-1/+0
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-051-3/+5
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 22:24:09 +0000