diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-27 23:56:39 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-28 23:45:04 +0000 |
| commit | 0a466040e0dc3351ac819ba00146f284e5f70f05 (patch) | |
| tree | ac3ce1a7d8f14775d323acd05999d417f56d53ff /src/include/cpu | |
| parent | 54c80e1df16d356dc73030903daece5fcb50e7bc (diff) | |
| download | coreboot-0a466040e0dc3351ac819ba00146f284e5f70f05.tar.gz coreboot-0a466040e0dc3351ac819ba00146f284e5f70f05.tar.bz2 coreboot-0a466040e0dc3351ac819ba00146f284e5f70f05.zip | |
soc/amd: introduce and use PSTATE_MSR macro
Instead of adding the P-state number to the PSTATE_0_MSR number to get
the P-state MSR number for the rdmsr call, provide a macro that directly
calculates the MSR number for a given power state. Also drop the unused
PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs
available in the hardware.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/amd/msr.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 76e6a8d665e3..1fd7ec7dbc41 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -40,10 +40,7 @@ /* P-state Status Register */ #define PS_STS_REG 0xC0010063 #define PSTATE_0_MSR 0xC0010064 -#define PSTATE_1_MSR 0xC0010065 -#define PSTATE_2_MSR 0xC0010066 -#define PSTATE_3_MSR 0xC0010067 -#define PSTATE_4_MSR 0xC0010068 +#define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 |