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| author | Subrata Banik <subrata.banik@intel.com> | 2021-07-30 17:36:56 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-08-16 05:07:12 +0000 |
| commit | 0e2510f616bc8a23428bd5eec97aaa698948c666 (patch) | |
| tree | bb30d916eadcdc49da14435dee6b084371f97bb5 /src/include/cpu | |
| parent | ad08265740cecef94bf7fd895221aceb0fcd28b7 (diff) | |
| download | coreboot-0e2510f616bc8a23428bd5eec97aaa698948c666.tar.gz coreboot-0e2510f616bc8a23428bd5eec97aaa698948c666.tar.bz2 coreboot-0e2510f616bc8a23428bd5eec97aaa698948c666.zip | |
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC
Kconfig and here is modified flow as below:
Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS
Update eNEM init flow:
- Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1
Update eNEM teardown flow:
- Set MSR 0xC85 L3_Protected_ways = 0x00000
BUG=b:168820083
TEST=Verified filling up the entire cache with memcpy at the beginning
itself and then running the entire bootblock, verstage, debug FSP-M
without running into any issue. This proves that code caching and
eviction is working as expected in eNEM mode.
Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 9e7e6fd8ba35..a8d5e2211bd4 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -88,6 +88,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_L3_PROTECTED_WAYS 0xc85 #define IA32_SF_QOS_INFO 0xc87 #define IA32_SF_WAY_COUNT_MASK 0x3f #define IA32_PQR_ASSOC 0xc8f |