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| author | Subrata Banik <subrata.banik@intel.com> | 2021-07-30 17:01:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-08-15 06:58:09 +0000 |
| commit | 16ab9bdcd578612bb3822373547f939eb90afd82 (patch) | |
| tree | 2c92c93a063c57216182aaee0d13d7c244ef7877 /src/include/cpu | |
| parent | 83c9b3a599ede17e1c656feb8ef240ce0e3ad287 (diff) | |
| download | coreboot-16ab9bdcd578612bb3822373547f939eb90afd82.tar.gz coreboot-16ab9bdcd578612bb3822373547f939eb90afd82.tar.bz2 coreboot-16ab9bdcd578612bb3822373547f939eb90afd82.zip | |
soc/intel/common: Calculate and configure SF Mask 2
As per TGL EDS, two ways will be controlled with one bit of SF QoS
register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to
allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS
recommendation.
Calculate SF masks 2:
1. if CONFIG_SF_MASK_2WAYS_PER_BIT:
a. data_ways = data_ways / 2
Also, program SF Mask#2 using below logic:
2. Set SF_MASK_2 = (1 << data_ways) - 1
Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 26f1dcb6cffd..9e7e6fd8ba35 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -88,6 +88,8 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_SF_QOS_INFO 0xc87 +#define IA32_SF_WAY_COUNT_MASK 0x3f #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) |