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| author | Hung-Te Lin <hungte@chromium.org> | 2021-09-03 15:44:04 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-09-11 08:04:28 +0000 |
| commit | e5cf666b9a5fa60d1253a94fc1e62c8ba86f28ce (patch) | |
| tree | 44daf4a6775155c58f4c5e88d20c080975c60e73 /src/mainboard/google/asurada | |
| parent | 2ef4b7ed18f10c9e391e98434178709840c9a708 (diff) | |
| download | coreboot-e5cf666b9a5fa60d1253a94fc1e62c8ba86f28ce.tar.gz coreboot-e5cf666b9a5fa60d1253a94fc1e62c8ba86f28ce.tar.bz2 coreboot-e5cf666b9a5fa60d1253a94fc1e62c8ba86f28ce.zip | |
mb/google/asurada: fine tune the data lane trail for ANX7625
The ANX7625 display bridge requires customized
hs_da_trail time.
This patch is based on CB:51433 (commit 6482b16,
"mb/google/kukui: fine tune the data lane trail")
BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/asurada')
| -rw-r--r-- | src/mainboard/google/asurada/mainboard.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index c8faffcfcd69..7704899f1678 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -64,6 +64,12 @@ static void register_reset_to_bl31(void) register_bl31_aux_param(¶m_reset.h); } +/* Override hs_da_trail for ANX7625 */ +void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) +{ + timing->da_hs_trail += 9; +} + /* Set up backlight control pins as output pin and power-off by default */ static void configure_backlight_and_bridge(void) { |