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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 20:36:50 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:05:36 +0000 |
| commit | 9a369718d668601da13030e9b57cd1a3e313cf5d (patch) | |
| tree | c35f3283c38070998541b02a39910235c9617558 /src/mainboard/google/beltino/romstage.c | |
| parent | d7bf3ad9397a367021e57d204438a178022aaa8c (diff) | |
| download | coreboot-9a369718d668601da13030e9b57cd1a3e313cf5d.tar.gz coreboot-9a369718d668601da13030e9b57cd1a3e313cf5d.tar.bz2 coreboot-9a369718d668601da13030e9b57cd1a3e313cf5d.zip | |
haswell: Factor out `max_ddr3_freq`
All mainboards choose the maximum speed of DDR3-1600.
Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino/romstage.c')
| -rw-r--r-- | src/mainboard/google/beltino/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index fe3275e9d9bb..525edf467f98 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -51,7 +51,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Enable 2x refresh mode */ pei_data->ddr_refresh_2x = 1; pei_data->dq_pins_interleaved = 1; - pei_data->max_ddr3_freq = 1600; pei_data->usb_xhci_on_resume = 1; struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { |