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| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-11-10 20:58:49 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-11 15:50:42 +0000 |
| commit | 03c3d5d68ea5c4758c0e3dc9dd15a7013b2105bd (patch) | |
| tree | be3ea454135168de7232d4559aed168d84800b7c /src/mainboard/google/brya/variants/gimble | |
| parent | 5164e4b03f8f05917e869456d481d0fd0ae3a69b (diff) | |
| download | coreboot-03c3d5d68ea5c4758c0e3dc9dd15a7013b2105bd.tar.gz coreboot-03c3d5d68ea5c4758c0e3dc9dd15a7013b2105bd.tar.bz2 coreboot-03c3d5d68ea5c4758c0e3dc9dd15a7013b2105bd.zip | |
mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C port
- Set MAX OC1 to USB2_C1
BUG=b:205676803
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/gimble')
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index c015009c0077..842dd00c0665 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -34,6 +34,7 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port |