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| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:18:17 +0000 |
| commit | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (patch) | |
| tree | 2b871fd211af0a239a0926f28c787e3cd406cc90 /src/mainboard/google/dedede/variants/baseboard/ramstage.c | |
| parent | 9bf38c7d672dbfe0771a15574a7e0c59f38c139c (diff) | |
| download | coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.tar.gz coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.tar.bz2 coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.zip | |
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/dedede/variants/baseboard/ramstage.c')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/ramstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c index e14e95650d77..d43d08f8561c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -6,6 +6,7 @@ #include <drivers/usb/acpi/chip.h> #include <fw_config.h> #include <gpio.h> +#include <soc/pci_devs.h> #include <ec/google/chromeec/ec.h> #include <device/pci_ops.h> #include <intelblocks/power_limit.h> |