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| author | Angel Pons <th3fanbus@gmail.com> | 2019-12-19 22:41:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-31 15:16:57 +0000 |
| commit | 408d1dac9e23250c0e485bbf934771f769b717c1 (patch) | |
| tree | 984d2a88f61cb8e09cf3a42803dc40fa7c3edb61 /src/mainboard/google/eve | |
| parent | ae863e2e25dba8ca80871551599fa79f7fac8e07 (diff) | |
| download | coreboot-408d1dac9e23250c0e485bbf934771f769b717c1.tar.gz coreboot-408d1dac9e23250c0e485bbf934771f769b717c1.tar.bz2 coreboot-408d1dac9e23250c0e485bbf934771f769b717c1.zip | |
mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/google/eve')
| -rw-r--r-- | src/mainboard/google/eve/dsdt.asl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 90463c85aa6d..5615e43e5446 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ |