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| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2021-03-15 10:31:37 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-22 03:50:08 +0000 |
| commit | 8f7fca53709e7ddd81efece6906d3bd019e878c0 (patch) | |
| tree | fe633ee9ecda0a2f111b2d6d64a4155187c48c97 /src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | |
| parent | 699a709bdcee250136a8b5f7af13a6d534598f1d (diff) | |
| download | coreboot-8f7fca53709e7ddd81efece6906d3bd019e878c0.tar.gz coreboot-8f7fca53709e7ddd81efece6906d3bd019e878c0.tar.bz2 coreboot-8f7fca53709e7ddd81efece6906d3bd019e878c0.zip | |
mb/google/guybrush: Enable AP <-> H1 communication
Configure H1 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for H1 device and enable the required
config items.
BUG=b:180528902
TEST=Build Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/guybrush/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3205d21680c3..4d57b5281095 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -132,4 +132,13 @@ chip soc/amd/cezanne end end end # domain + + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end end # chip soc/amd/cezanne |